Abstract: A semiconductor device includes a lead frame having a down bond area, a die attach area and a dam formed between the down bond area and the die attach area. A bottom of the dam is attached on a surface of the lead frame. The dam prevents contamination of the down bond area from die attach material, which may occur during a die attach process.

Abstract: Embodiments described herein relate to a method of manufacturing a packaged circuit having a solder flow-impeding plug on a lead frame. The method includes partially etching an internal surface of a lead frame at dividing lines between future sections of the lead frame as first partial etch forming a trench. A non-conductive material that is adhesive to the lead frame is applied in the trench, such that the non-conductive material extends across the trench to form the solder flow-impeding plug. One or more components are attached to the internal surface of the lead frame and encapsulated. An external surface of the lead frame is etched at the dividing lines to disconnect different sections of lead frame as a second partial etch.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead frame having a die attach paddle pad and a peripheral lead pad with an inner lead pad between the die attach paddle pad and the peripheral lead pad; forming a component side of the lead frame for exposing an upper portion of a peripheral lead under the peripheral lead pad; forming an encapsulation on the lead frame and the upper portion of the peripheral lead; exposing the peripheral lead pad; depositing a conductive shielding layer on the encapsulation connected to the peripheral lead pad; and forming a mounting side of the lead frame for forming a lower portion of the peripheral lead over a peripheral lead contact pad.

Abstract: A small form factor near chip scale package is provided that includes input/output contacts not only along the periphery of the package, but also along the package bottom area. Embodiments provide these additional contacts through use of an array lead frame coupled to under die signal contacts through the use of flip chip bonding techniques. The array lead frame contacts are electrically isolated through the use of a partial sawing process performed during package singulation.

Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.

Abstract: A semiconductor device of the present invention includes a semiconductor element having an electrode pad; a substrate over which the semiconductor element is mounted and which has an electrical bonding part; and a bonding wire electrically connecting the electrode pad to the electrical bonding part, wherein a main metal component of the electrode pad is the same as or different from a main metal component of the bonding wire, and when the main metal component of the electrode pad is different from the main metal component of the bonding wire, a rate of interdiffusion of the main metal component of the bonding wire and the main metal component of the electrode pad at a junction of the bonding wire and the electrode pad under a post-curing temperature of an encapsulating resin is lower than that of interdiffusion of gold (Au) and aluminum (Al) at a junction of aluminum (Al) and gold (Au) under the post-curing temperature.

Abstract: An integrated circuit package having a die attach paddle, a power die mounted on the die attach paddle and a controller die mounted on the die attach paddle. The die attach paddle has at least one recessed portion at least partially underlying the controller die.

Abstract: Packages for an integrated circuit die and methods and lead frames for making such packages are disclosed. The package includes a die, a die pad, peripheral metal contacts, bond wares, and an encapsulant. The die pad and contacts are located at a lower surface of the package. The die pad and the contacts have side surfaces which include reentrant portions and asperities to engage the encapsulant.

Abstract: Embodiments of microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the fabrication method includes printing a patterned die attach material onto the backside of a wafer including an array of non-singulated microelectronic die each having an interior keep-out area, such as a central keep-out area. The die attach material, such as a B-stage epoxy, is printed onto the wafer in a predetermined pattern such that the die attach material does not encroaching into the interior keep-out areas. The wafer is singulated to produce singulated microelectronic die each including a layer of die attach material. The singulated microelectronic die are then placed onto leadframes or other package substrates with the die attach material contacting the package substrates. The layer of die attach material is then fully cured to adhere an outer peripheral portion of the singulated microelectronic die to its package substrate.

Abstract: The present invention provides a Quad Flat Non-leaded (QFN) package, which comprises a chip, a lead frame, a plurality of composite bumps and an encapsulant. The chip has a plurality of pads, and the lead frame has a plurality of leads. Each of the plurality of composite bumps has a first conductive layer and a second conductive layer. The first conductive layer is electrically connected between one of the pads and the second conductive layer, and the second conductive layer is electrically connected between the first conductive layer and one of the leads. The encapsulant encapsulates the chip, the leads and the composite bumps. Thereby, a QFN package with composite bumps and a semi-cured encapsulant is forming between the spaces of leads of lead frame before chip bonded to the lead frame are provided.

Abstract: Disclosed herein are various chip lead frame and packaging structures, and methods of fabrication. In one embodiment, a lead frame can include: (i) a horizontal plate arranged at a bottom of the lead frame, where the horizontal plate is conductive; and (ii) a plurality of conductive bumps arranged on a surface of the horizontal plate, where the plurality of conductive bumps are configured to support and electrically connect to at least one chip. In one embodiment, a method of making the lead frame can include: (i) forming the horizontal plate by a mold; (ii) arranging a mask with a through-hole on the surface of the horizontal plate; (iii) electroplating conducting material on a portion of the horizontal plate that is exposed by the through-hole; and (iv) removing the mask after formation of the plurality of conductive bumps. Also, a package structure can be formed using the lead frame.

Abstract: A method for manufacturing a chip arrangement in accordance with various embodiments may include: placing a chip on a carrier within an opening of a metal structure disposed over the carrier; fixing the chip to the metal structure; removing the carrier to thereby expose at least one contact of the chip; and forming an electrically conductive connection between the at least one contact of the chip and the metal structure.

Abstract: A semiconductor device includes a semiconductor die having a first major surface and a second major surface opposite the first major surface, a first minor surface and a second minor surface opposite the first minor surface, a plurality of contact pads on the first major surface, and a notch which extends from the first minor surface and the second major surface into the semiconductor die. The notch has a notch depth measured from the second major surface into the semiconductor die, wherein the notch depth is less than a thickness of the semiconductor die, and a notch length measured from the first minor surface into the semiconductor die, wherein the notch length is less than a length of the semiconductor die measured between the first and second minor surfaces. The device includes a lead having a first end in the notch, and an encapsulant over the first major surface.

Abstract: A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.

Abstract: Embodiments of a method for preparing a leadframe for integrated circuit (IC) die packaging in a molded package with an exposed die pad are disclosed. In one embodiment, a method involves producing a leadframe with a die pad, wherein the die pad has a top surface, a bottom surface, and a perimeter edge. The die pad is then planarized to flatten burrs that may exist at the perimeter edge of the die pad, wherein planarizing the die pad comprises embedding tool markings in the die pad at the perimeter edge of the die pad, the tool markings including a series of peaks and valleys that run parallel to the perimeter edge at all locations around the perimeter edge. Embodiments of a leadframe for IC die packaging in a molded package are also disclosed.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead array having an innermost space with an innermost lead having an inner lead profile different around an inner non-horizontal side of the innermost lead; forming a middle lead having a middle lead profile the same around a lead side of the middle lead; placing an integrated circuit in the innermost space adjacent to the innermost lead; and forming a package encapsulation over the integrated circuit, the innermost lead, and the middle lead.

Abstract: The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask.

Abstract: A semiconductor package is manufactured by providing a semiconductor die with a terminal at a first side of the die, providing a material coupled to the die at an opposing second side of the die and embedding the die in a molding compound so that the die is covered by the molding compound on all sides except the first side. The molding compound is thinned at a side of the molding compound adjacent the second side of the die, to expose the material at the second side of the die without exposing the second side of the die. An electrical connection is formed to the terminal at the first side of the die. In the case of a transistor die, the terminal can be a source terminal and the transistor die can be attached source-down to a metal block such as a die paddle of a lead frame.

Abstract: A semiconductor chip for a TAB package includes a surface including a set of input pads connected to internal circuitry of the chip and for receiving external signals The surface includes output pads. A plurality of input pads are adjacent a first edge and are in a first row substantially parallel to the first edge and extending in a first direction; a plurality of first output pads are adjacent a second edge, and are in a second row substantially parallel to the second edge and extending in the first direction; and a plurality of second output pads are located between the first row and the second row. The plurality of second output pads include first and second outermost pads located a certain distance from a respective third edge and fourth edge, and first and second inner pads located a greater distance from the respective third edge and fourth edge.

Abstract: The present invention discloses a stacked dual MOSFET package structure and a preparation method thereof. The stacked dual MOSFET package structure comprises a lead frame unit having a die paddle, a first lead and a second lead; a first chip flipped and attached on a top surface of a main paddle of the die paddle; a second chip attached on a bottom surface of the main paddle; and a metal clip mounted on the back of the flipped first chip and electrically connecting an electrode at the back of the first chip to the first lead. A top surface of a metal bump arranged on each electrode at the front of the second chip, a bottom surface of the die pin of the die paddle, a bottom surface of a lead pin of the second lead, and a bottom surface of the first lead are located on the same plane.

Abstract: Embodiments of a leadframe for a device packaging are used not only for structural support and connectivity to the I/O pins to the external world, but also for housing and/or mounting devices above and below the leadframe. Being electrically conductive, the leadframe also serves as a low resistance interconnect and good current carrier between the bondpads on one device or between the bondpads on different devices above and/or below the leadframe.

Abstract: The present disclosure relates to a semiconductor package and a method of fabricating the same. The semiconductor package includes a substrate, a grounding layer, a chip, a package body, and a shielding layer. The substrate includes a lateral surface and a bottom surface. The grounding layer is buried in the substrate and extends horizontally in the substrate. The chip is arranged on the substrate. The package body envelops the chip and includes a lateral surface. The shielding layer covers the lateral surface of the package body and the lateral surface of the substrate, and is electrically connected to the grounding layer, where a bottom surface of the shielding layer is separated from a bottom surface of the substrate.

Abstract: According to one embodiment, a semiconductor device includes a metal holder, a semiconductor chip on the holder, and a reinforcing portion. The reinforcing portion is formed by bending a portion of the holder, the reinforcing portion includes a groove depressed from a surface of the holder and a protrusion on a back of the groove.

Abstract: A lead frame includes at least one row of a plurality of unit regions arranged in a first direction. Each of the unit regions includes: a first lead; a second lead; and an isolation region configured to isolate the first lead from the second lead, the isolation region including a bent portion that is located at an end part of the second lead. The first lead has an extending portion extending along the end part of the second lead. The plurality of unit regions includes a first unit region, and a second unit region that is adjacent to the first unit region in the first direction. The first lead of the first unit region is connected to the first lead or second lead of the second unit region via the extending portion.

Abstract: A chip is attached to a substrate with wires spanning from the chip to the substrate is loaded in a heated cavity of a mold. The wire surfaces are coated with an adsorbed layer of molecules of a heterocyclic compound. A pressure chamber of the mold is loaded with a solid pellet of a packaging material including a polymerizable resin. The chamber is connected to the cavity. The vapor of resin molecules is allowed to spread from the chamber to the assembly inside the cavity during the time interval needed to heat the solid pellet for rendering it semi-liquid and to pressurize it through runners before filling the mold cavity, wherein the resin molecules arriving in the cavity are cross-linked by the adsorbed heterocyclic compound molecules into an electrically insulating at least one monolayer of polymeric structures on the wire surfaces.

Abstract: A metal tab die attach paddle (DAP) disposed between the lead frame and a power device die in a power device package reduces the stress exerted on the semiconductor power device die caused by the different coefficients of thermal expansion (CTE) of the semiconductor power device die and the lead frame. In addition the power device package substantially prevents impurities from penetrating into the power device package by increasing the surface creepage distance of a sealant resulting from the metal tab DAP and an optional swaging of the lead frame.

Abstract: Disclosed are a lead frame and a method for manufacturing the same. The lead frame includes a copper substrate and a rough copper layer having surface roughness of 110 nm to 300 nm on a surface of the copper substrate.

Abstract: A method for manufacturing an LED (light emitting diode) is disclosed wherein a metal substrate is provided. A chip fastening area with a depression and two wire fixing areas on the first metal substrate are defined on the metal substrate. The chip fastening area and the wire fixing areas are separated by a plurality of first grooves. An LED chip is provided in the depression of the chip fastening area and electrically connected to the wire fixing areas by wires. An encapsulant is formed to cover and connect the chip fastening area and the wire fixing areas. Portions of the metal substrate except the chip fastening area and the wire fixing areas are removed.

Abstract: An integrated passives package includes an encapsulation compound and a plurality of electrically conductive pads embedded in the encapsulation compound. Each of the pads has opposing first and second sides. The first side of the pads is uncovered by the encapsulation compound and forms array of external electrical connections at a first side of the package. The integrated passives package further includes a plurality of passive components embedded in the encapsulation compound. Each of the passive components has a first terminal attached to one of the pads and a second terminal attached to a different one the pads at the second side of the pads. Corresponding semiconductor modules and methods of manufacturing are also provided.

Abstract: According to the disclosure, a lead frame is provided, which includes: a first island and a second island that are arranged side by side; an outer peripheral frame; first leads that extend in a second direction perpendicular to the first direction; second leads that extend in the second direction; a first coupling portion that couples the first leads to the frame; a second coupling portion that couples the second leads to the frame; an intermediate portion formed between the first and second coupling portions in the first direction such that it extends in the second direction to terminate before the space between the first and second islands; and a deformation restraining portion formed or provided in at least one of the first leads, the second leads, the first and the second coupling portions and configured to restrain deformations of the first and second leads during a molding process.

Abstract: A method of forming an electronic component includes masking a lead frame to form a mask defining an exposed area, oxidizing the exposed area of the lead frame, wherein the mask inhibits oxidation of an unexposed area, and removing the mask from the lead frame following oxidizing. A lead frame can include a metal sheet patterned to define a pad region and leads. The metal sheet includes metal oxide in a select area. The pad region is substantially free of metal oxide.

Abstract: The present invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device has a plurality of power units placed in parallel in a predetermined direction, wherein each of the power units includes a plurality of semiconductor elements placed on a metal plate having predetermined gaps with each other. The semiconductor elements of each of the two power units include a near-sided semiconductor element that is closer to an inlet of the resin among the two semiconductor elements having the predetermined gap therebetween. A structure is positioned on a passage and downstream in a resin flow direction relative to a predetermined position that corresponds to end parts of the near-sided semiconductor elements. The structure is a joint to connect the two power units placed adjacent to each other in the predetermined direction, and to be integrally sealed with the resin, along with the power unit.

Abstract: A semiconductor device includes a semiconductor element that is mounted on a substrate, an electrode pad that contains aluminum as a main component and is provided in the semiconductor element, a copper wire that contains copper as a main component and connects a connection terminal provided on the substrate and the electrode pad, and an encapsulant resin that encapsulates the semiconductor element and the copper wire. When the semiconductor device is heated at 200° C. for 16 hours in the atmosphere, a barrier layer containing any metal selected from palladium and platinum is farmed at a junction between the copper wire and the electrode pad.

Abstract: In a semiconductor device, a lead frame made of a copper alloy prevents exfoliation occurring near the surface of the lead frame. A copper oxide layer is formed on the base material made of a copper alloy by immersing the base material into a solution of a strong oxidizer. The copper oxide layer serves as an outermost layer and consists of a copper oxide other than a copper oxide in the form of needle crystals.

Abstract: An integrated circuit package system includes: interconnection pads; a first device mounted below the interconnection pads; a bond wire, or a solder ball connecting the first device to the interconnection pads; a lead connected to the interconnection pad or to the first device; an encapsulation having a top surface encapsulating the first device; and a recess in the top surface of the encapsulation with the interconnection pads exposed therefrom.

Abstract: The present invention has a tray corresponding to a heat sink, a circuit part is accommodated in an accommodating part of the tray, and the circuit part is potting-sealed with a sealing resin such that external electrodes are exposed. The sealing resin covers and seals a top part of the tray.

Abstract: A semiconductor device is provided which complies with restrictions on layout on a mounting substrate side. The semiconductor device includes a wiring substrate having a plurality of bonding leads at an upper surface having a rectangular shape, a semiconductor chip mounted over the upper surface of the wiring substrate, and having a plurality of electrode pads at a main surface having a rectangular shape similar to a square shape, and a plurality of metal wires for coupling the bonding leads of the wiring substrate to the electrode pads of the semiconductor chip. In a BGA, the metal wires are arranged at three sides of a main surface of the semiconductor chip, the bonding leads are provided in lines at the upper surface of the wiring substrate outside the respective opposed short sides of the main surface of the semiconductor chip, and the metal wires are coupled to the bonding leads.

Abstract: A semiconductor device with plated pillars and leads is disclosed and may include a semiconductor die comprising a conductive pillar, a conductive lead electrically coupled to the conductive pillar, a metal plating layer covering the conductive lead and conductive pillar, and an encapsulant material encapsulating the semiconductor die and at least a portion of the plating layer. The pillar, lead, and plating layer may comprise copper, for example. The plating layer may fill a gap between the pillar and the lead. A portion of the metal plating layer may, for example, comprise an external lead. The metal plating layer may cover a side surface of the pillar and a top surface, side surface, and at least a portion of a bottom surface of the lead. The metal plating layer may cover side and bottom surfaces of the pillar and top, side, and at least a portion of bottom surfaces of the conductive lead.

Abstract: A lead frame and a semiconductor package including the lead frame are provided. The lead frame includes: a base material; a first metal layer which is formed on at least one side of the base material, of which a surface is roughly formed, and which includes copper or nickel; a second metal layer which is formed on a surface of the first metal layer, of which a surface is roughly formed, and which includes palladium or a palladium alloy; a third metal layer which is formed on a surface of the second metal layer, of which a surface is roughly formed, and which includes gold or a gold alloy; and a fourth metal layer which is formed on a surface of the third metal layer, of which a surface is roughly formed, and which includes metal that includes silver.

Abstract: An integrated circuit package system includes an in-line strip, attaching an integrated circuit die over the in-line strip, and applying a molding material with a molded segment having a molded strip protrusion formed therefrom over the in-line strip.

Abstract: A semiconductor package includes a lead spaced apart from a semiconductor die. The die includes a diaphragm disposed at a first side of the die and is configured to change an electrical parameter responsive to a pressure difference across the diaphragm. The die further includes a second side opposite the first side, a lateral edge extending between the first and second sides and a terminal at the first side. An electrical conductor connects the terminal to the lead. An encapsulant is disposed along the lateral edge of the die so that the terminal and the electrical conductor are spaced apart from the encapsulant. The encapsulant has an elastic modulus of less 10 MPa at room temperature. A molding compound covers and contacts the lead, the electrical conductor, the encapsulant, the terminal and part of the first side of the die so that the diaphragm is uncovered by the molding compound.

Abstract: An electronic package includes a leadframe, a plurality of pins, a gallium-nitride (GaN) transistor, and a GaN diode. The GaN transistor includes a drain region, a drift region, a source region, and a gate region; the drain region includes a GaN substrate and a drain contact, the drift region includes a first GaN epitaxial layer coupled to the GaN substrate, the source region includes a source contact and is separated from the GaN substrate by the drift region, and the gate region includes a second GaN epitaxial layer and a gate contact. The GaN diode includes an anode region and a cathode region, the cathode region including the GaN substrate and a cathode contact, and the anode region including a third GaN epitaxial layer coupled to the GaN substrate and an anode contact. The drain contact and the anode contact are electrically connected to the leadframe.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a trench; mounting an integrated circuit device on the leadframe; forming a top encapsulation on the leadframe and the trench; forming a lead having a lead protrusion and a peripheral groove, the lead protrusion and the peripheral groove formed from etching the trench at a leadframe bottom side; and forming a bottom encapsulation surrounding a lead bottom side of the lead.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle group having a first package paddle electrically isolated from a second package paddle; attaching an integrated circuit device on the first package paddle and the second package paddle; forming a standoff terminal adjacent the package paddle group and electrically connected to the integrated circuit device; connecting a paddle connector to the integrated circuit device and the first package paddle and another paddle connector to the integrated circuit device and the second package paddle; and forming an encapsulation over the integrated circuit device, the first package paddle, the second package paddle, and the standoff terminal, the encapsulation exposing a portion of the first package paddle, the second package paddle, and the standoff terminal.

Abstract: A semiconductor device includes a first substrate having opposing first and second main surfaces, a first die disposed on the first main surface of the first substrate, a first bond wire coupled to the first die, a first packaging material encapsulating the first die and the first bond wire, and a lead frame disposed on the first main surface of the first substrate and in electrical communication with the first bond wire. At least a portion of the lead frame extends outside of the packaging material. A top package includes first and second main surfaces and an electrical contact on the second main surface. The electrical contact is electrically connected to the lead frame and connects the top package to either the first die and/or external circuitry.

Abstract: A Quad Flat Package (QFP) semiconductor device has a multi-stepped lead frame for forming rows of external contacts. A semiconductor die is attached to a die pad of the lead frame and electrically connected to lead with bond wires. The die and bond wires are encapsulated with a mold compound and then multiple cuts are made to the lead frame to form the rows of external contacts.

Abstract: A semiconductor device (100) includes a leadframe having a chip pad (110) and a lead (111) with a first end (112) proximate to the pad and a second end (113) remote from the pad, the leadframe having a base metal (120) including copper and a stack of a plated first layer (121) of nickel in contact with the base metal and a plated second layer (122) of a noble metal in contact with the nickel layer, the second lead end free of the noble metal. Further included is a copper wire (104) having a ball bond (104a) on a semiconductor chip (101) attached to the chip pad, and a stitch bond (104b) on the proximate lead end, the stitch bond penetrating the second layer; furthermore a packaging compound (130) encapsulating the chip, the wire, and the first end of the lead, the compound leaving the second end of the lead un-encapsulated; and the unencapsulated second lead end covered with a plated third layer (123) of solder.

Abstract: A double-side exposed semiconductor device includes an electric conductive first lead frame attached on top of a thermal conductive but electrical nonconductive second lead frame and a semiconductor chip flipped and attached on top of the first lead frame. The gate and source electrodes on top of the flipped chip form electrical connections with gate and source pins of the first lead frame respectively. The flipped chip and center portions of the first and second lead frames are then encapsulated with a molding compound, such that the heat sink formed at the center of the second lead frame and the drain electrode at bottom of the semiconductor chip are exposed on two opposite sides of the semiconductor device. Thus, heat dissipation performance of the semiconductor device is effectively improved without increasing the size of the semiconductor device.

Abstract: A semiconductor device includes a semiconductor die having a first major surface and a second major surface opposite the first major surface, a first minor surface and a second minor surface opposite the first minor surface, a plurality of contact pads on the first major surface, and a notch which extends from the first minor surface and the second major surface into the semiconductor die. The notch has a notch depth measured from the second major surface into the semiconductor die, wherein the notch depth is less than a thickness of the semiconductor die, and a notch length measured from the first minor surface into the semiconductor die, wherein the notch length is less than a length of the semiconductor die measured between the first and second minor surfaces. The device includes a lead having a first end in the notch, and an encapsulant over the first major surface.

Abstract: A semiconductor device has a die support and external leads formed integrally from a single sheet of electrically conductive material. A die mounting substrate is mounted on the die support, with bonding pads coupled to respective external connection pads on an external connector side of the substrate. A die is attached to the die mounting substrate with die connection pads. Bond wires selectively electrically couple the die connection pads to the external leads and the bonding pads and electrically conductive external protrusions are mounted to the external connection pads. An encapsulant covers the die and bond wires. The external protrusions are located at a central region of a surface mounting side of the package and the external leads project outwardly from locations near the die support towards peripheral edges of the package.