Abstract: A semiconductor device has a die support and external leads formed integrally from a single sheet of electrically conductive material. A die mounting substrate is mounted on the die support, with bonding pads coupled to respective external connection pads on an external connector side of the substrate. A die is attached to the die mounting substrate with die connection pads. Bond wires selectively electrically couple the die connection pads to the external leads and the bonding pads and electrically conductive external protrusions are mounted to the external connection pads. An encapsulant covers the die and bond wires. The external protrusions are located at a central region of a surface mounting side of the package and the external leads project outwardly from locations near the die support towards peripheral edges of the package.

Abstract: A lead frame includes: a chip-mounting region provided on a front surface; a lead region including a plurality of concave and convex sections arranged in an in-plane direction of the chip-mounting region; and a terminal arranged in the concave section. A thickness of the lead region from the front surface is smaller than a thickness of the terminal from the front surface.

Abstract: A module (1) includes a first functional device (2) and a second functional device (3). The first functional device (2) includes a base electrode, an emitter electrode and a collector electrode. The second functional device (3) includes at least one electrode. The module (1) further includes a conductive frame (4). One of the base electrode, the emitter electrode, and the collector electrode of the first functional device (2) is directly connected to the frame (4). The electrode of the second functional device (3) is also directly connected to the frame (4). The frame (4) includes a portion serving as a terminal for external connection.

Abstract: A package structure and a package process are provided. The package structure comprises a carrier having a carrying portion and a plurality of supporting bar remnants disposed around and extending outward from the carrying portion, a chip mounted to the carrying portion, and an encapsulant disposed on the carrier and covering the chip, wherein the supporting bar remnants are encapsulated by the encapsulant, and each of the supporting bar remnants has a distal end shrank from an outer surface of the encapsulant. A package process for fabricating the package structure is also provided.

Abstract: The present invention specifies a leadframe for electronic components and a corresponding manufacturing process, in which the bonding islands are formed by welding individual, prefabricated segments of a bonding-capable material onto a stamped leadframe.

Abstract: Embodiments of the present disclosure are directed to a leadframe packages that include a leadframe having a surface that is selectively treated with chemicals that reduce the wettability of the surface and thereby reduce adhesive flow on the surface and methods of forming a packing comprising same. In one embodiment there is provided a leadframe having an upper surface that includes a first portion that is treated with an anti-epoxy bleed out chemical and a second portion that was not treated with the anti-epoxy bleed out chemical. A semiconductor die is attached to the upper surface of the leadframe at the second portion via an epoxy adhesive.

Abstract: A packaged semiconductor device includes a lead frame having a plurality of leads; a semiconductor die mounted onto the lead frame; and an encapsulant surrounding the semiconductor die. At least a portion of each of the leads is surrounded by the encapsulant, wherein, each lead includes a thin portion external to the encapsulant and a thick portion that is surrounded by the encapsulant, wherein the thin portion is thinner than the thick portion.

Abstract: A semiconductor device includes: a semiconductor chip including a main surface electrode; a first mounting lead; a second mounting lead; a connection lead which overlaps with the main surface electrode, the first mounting lead and the second mounting lead when viewed in a thickness direction of the semiconductor chip and makes electrical conduction between the main surface electrode, the first mounting lead and the second mounting lead; and a resin portion which covers the semiconductor chip, the first mounting lead and the second mounting lead, wherein the resin portion has a resin bottom lying on the same plane as a bottom of the first mounting lead and a bottom of the second mounting lead.

Abstract: A process for assembly of an integrated device, envisages: providing a first body of semiconductor material integrating at least one electronic circuit and having a top surface; providing a second body of semiconductor material integrating at least one microelectromechanical structure and having a bottom surface; and stacking the second body on the first body with the interposition, between the top surface of the first body and the bottom surface of the second body, of an elastic spacer material. Prior to the stacking step, the step is envisaged of providing, in an integrated manner, at the top surface of the first body a confinement and spacing structure that confines inside it the elastic spacer material and supports the second body at a distance from the first body during the stacking step.

Abstract: A method of manufacturing integrated circuit (IC) devices includes the steps of providing a first frame that has openings each having a perimeter with shaped notches, placing a first die in at least one of the openings, and placing a second frame over the first frame. The second frame has a first partial dam bar with a first shaped tip that fits into a first shaped notch of the first frame. The method also includes the step of placing a third frame over the second frame. The third frame has a second partial dam bars with a second shaped tip that fits into a second shaped notch of the first frame. Each perimeter and the respective first and second partial dam bars cooperate to form a continuous dam completely encircling the die within the respective opening.

Abstract: Processes of assembling microelectronic packages with lead frames and/or other suitable substrates are described herein. In one embodiment, a method for fabricating a semiconductor assembly includes forming an attachment area and a non-attachment area on a lead finger of a lead frame. The attachment area is more wettable to the solder ball than the non-attachment area during reflow. The method also includes contacting a solder ball carried by a semiconductor die with the attachment area of the lead finger, reflowing the solder ball while the solder ball is in contact with the attachment area of the lead finger, and controllably collapsing the solder ball to establish an electrical connection between the semiconductor die and the lead finger of the lead frame.

Abstract: A circuit board includes a first metal pattern which includes a marking and a first solder resist, a semiconductor memory element mounted on a circuit board, a connection terminal, and a mold resin covering the semiconductor memory element. The semiconductor memory device displays information through the marking which is formed by laser processing on the first metal pattern in areas where the test terminal and the electrode terminal are not provided and the semiconductor memory element is sealed with a mold resin.

Abstract: A lead frame for a semiconductor device has a die pad for supporting a semiconductor die and intermediate lead fingers extending from a periphery of the package towards the die pad, and each having a bonding end near the die pad. Outer lead fingers are located adjacent respective tie bars edges, each outer lead finger extending from the periphery of the package towards the die pad. Each outer lead finger has a transverse region coupling two spaced longitudinal regions. The two spaced longitudinal regions each have a bonding region near the die pad. A semiconductor die is attached to the die pad and bond wires electrically couple connection pads of the semiconductor die to the bonding regions of each outer lead finger. Only one of the bond wires is bonded to the bonding region of the second longitudinal region.

Abstract: A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are coupled to a lead frame that is subsequently embedded in an encapsulated semiconductor device package. The free end of signal conduits is exposed while the other end remains coupled to a lead frame. The signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package and the leads.

Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.

Abstract: A leadframe that includes a die attachment pad and a lead having a bondwire attach portion with a thickness less than 50% of the thickness of an adjacent portion of the lead. Also a method of forming a leadframe includes forming a lead having a bond wire attach portion with an original thickness and coining the bond wire attach portion to a thickness less than 50% of the original thickness. An integrated circuit package and a method of forming an integrated circuit package are also disclosed.

Abstract: The semiconductor device includes; a semiconductor element in which a metallization layer is formed on the backside side; a metallic lead frame that is arranged in parallel, with a distance spaced apart from the semiconductor element; a first bonding layer that is provided between the semiconductor element and the lead frame, and is bonded to the metallization layer; and a second bonding layer that is provided between the semiconductor element and the lead frame, and bonds the first bonding layer to the lead frame. The first bonding layer is expanded at a central portion toward the lead frame.

Abstract: A method of manufacturing an electronic device is provided. The method comprises providing a carrier sheet, etching the lead frame material sheet to form a recess on a first surface of the lead frame material sheet, placing an electronic chip into the recess of the carrier sheet, and thereafter, selectively etching a second surface of the lead frame material sheet, the second surface being opposite to the first surface.

Abstract: A lead frame based semiconductor die package includes a lead frame having a die pad that supports a semiconductor die and lead fingers that surround the die and die pad. The die is electrically connected to the lead fingers with bond wires. The die and bond wires are covered with an encapsulant with ends of the lead fingers projecting out from the encapsulant. One set of the lead fingers are bent and project down and another set of the lead fingers are bent and project inwardly, and under a bottom surface of the encapsulant. The encapsulant includes a slot or groove for receiving the lead fingers of the second set.

Abstract: A semiconductor device permitting the reduction of cost is disclosed. In a semiconductor package wherein electrode pads of a semiconductor chip and corresponding inner leads are electrically coupled with each other through a plurality of bonding wires, sensing wires (second and fourth bonding wires) are made thinner than other bonding wires (first and third bonding wires) coupled to inner leads same as those with the sensing wires coupled thereto, thereby reducing the cost of gold wires to attain the reduction in cost of the semiconductor package.

Abstract: Processes of assembling microelectronic packages with lead frames and/or other suitable substrates are described herein. In one embodiment, a method for fabricating a semiconductor assembly includes forming an attachment area and a non-attachment area on a lead finger of a lead frame. The attachment area is more wettable to the solder ball than the non-attachment area during reflow. The method also includes contacting a solder ball carried by a semiconductor die with the attachment area of the lead finger, reflowing the solder ball while the solder ball is in contact with the attachment area of the lead finger, and controllably collapsing the solder ball to establish an electrical connection between the semiconductor die and the lead finger of the lead frame.

Abstract: A technique capable of enhancing a reliability of a semiconductor device is provided. A semiconductor device has a die pad on which a semiconductor chip is mounted. The die pad is sealed with resin so that a lower surface located on an opposite side of an upper surface on which the semiconductor chip is mounted is exposed. Also, the die pad has a central part including a region in which the semiconductor chip is mounted and a peripheral edge part provided next to the central part in a planar view. In addition, a step surface formed so that a height of the peripheral edge part becomes higher than a height of the central part is provided at a boundary between the central part and the peripheral edge part.

Abstract: A smart card module for use in a smart card includes a microchip and a contact zone for making contact with the microchip by means of a reader. The microchip can be enclosed by an encapsulation which can enclose the microchip completely from all sides.

Abstract: A vertical semiconductor power device includes a top surface and a bottom surface of a semiconductor substrate constituting a vertical current path for conducting a current there through. The semiconductor power device further includes an over current protection layer composed of a material having a resistance with a positive temperature coefficient (PTC) and the over current protection layer constituting as a part of the vertical current path connected to a source electrode and providing a feedback voltage a gate electrode of the vertical semiconductor power device for limiting a current passing there through for protecting the semiconductor power device at any voltage.

Abstract: A semiconductor device has a substrate with a cavity. A conductive layer is formed within the cavity and over the substrate outside the cavity. A plurality of indentations can be formed in a surface of the substrate opposite the cavity for stress relief. A first semiconductor die is mounted within the cavity. A plurality of conductive vias can be formed through the first semiconductor die. An insulating layer is disposed between the first semiconductor die and substrate with the first conductive layer embedded within the first insulating layer. An encapsulant is deposited over the first semiconductor die and substrate. An interconnect structure is formed over the encapsulant. The interconnect structure is electrically connected to the first semiconductor die and first conductive layer. The substrate is removed to expose the first conductive layer. A second semiconductor die is mounted to the conductive layer over the first semiconductor die.

Abstract: To stably remove a resin body formed in a supply route of a resin in a sealing step. A leadframe has, in a sub-runner portion thereof, a sub-through-hole. The sub-through-hole has, along a first direction along which the sub-runner portion extends, a first portion located on the side of a main-runner portion and a second portion located on the side of a gate portion relative to the first portion. In a plan view, an opening width of the sub-through-hole in the first direction is greater than that of the sub-through-hole in a second direction perpendicular to the first direction. In a plan view, an opening width of the sub-through-hole in the second direction gradually decreases from the first portion to an end portion of the second portion on the side of the gate portion.

Abstract: An electronic package includes a leadframe and a plurality of pins. The electronic package also includes a first gallium nitride (GaN) transistor comprising a source, gate, and drain and a second GaN transistor comprising a source, gate, and drain. The source of the first GaN transistor is electrically connected to the leadframe and the drain of the second GaN transistor is electrically connected to the leadframe. The electronic package further includes a first GaN diode comprising an anode and cathode and a second GaN diode comprising an anode and cathode. The anode of the first GaN diode is electrically connected to the leadframe and the cathode of the second GaN diode is electrically connected to the leadframe.

Abstract: An integrated-circuit module includes an integrated-circuit device having a first surface and a plurality of bond pads disposed on the first surface. The module further includes metallic bond wires or metallic ribbons, which are attached between respective ones of a first subset of the bond pads and a package substrate or leadframe, such that a second subset of the bond pads are not attached to either a package substrate or leadframe. A metallic stud bump is affixed to each of one or more of the second subset of the bond pads. The integrated-circuit module further comprises a molding compound that contacts at least the first surface of the integrated-circuit device and substantially surrounds the bond wires or ribbon wires and the metallic stud bumps.

Abstract: A method for manufacturing semiconductor devices includes providing a stack having a semiconductor wafer and a glass substrate with openings and at least one trench attached to the semiconductor wafer. The semiconductor wafer includes a plurality of semiconductor devices. The openings of the glass substrate leave respective areas of the semiconductor devices uncovered by the glass substrate and the trench connects the openings. A metal layer is formed at least on exposed walls of the trench and the openings and on the uncovered areas of the semiconductor devices of the semiconductor wafer. A metal region is formed by electroplating metal in the openings and the trench and by subsequently grinding the glass substrate to remove the trenches. The stack of the semiconductor wafer and the attached glass substrate is cut to separate the semiconductor devices.

Abstract: “Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels.

Abstract: An integrated circuit package includes an electronic sensor protected by a lid structure. The electronic sensor includes a transducer placed on a backside surface of a lead frame assembly. The lid structure is placed over the transducer and is attached to the lead frame assembly on the backside surface. The lid can define an air cavity around the transducer, such that mold compound, gel, or other protective chemical material is not placed in contact with the transducer. The transducer is therefore protected without a chemical protectant, lowering the cost of the integrated circuit package and maintaining the sensitivity and performance of the transducer.

Abstract: A quad flat no-lead (QFN) integrated circuit package is provided. The QFN integrated circuit package includes an insulating adhesive layer, a semiconductor chip attached to the insulating adhesive layer, and a lead frame bent to be electrically connected to the semiconductor chip and attached to the insulating adhesive layer. The QFN integrated circuit package according the present invention does not use a die paddle and is thus thin. Accordingly, the volume of the package can be minimized.

Abstract: A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform.

Abstract: A method of making a stacked semiconductor package having at least a leadframe, a first die mounted above and soldered to the lead frame and a first clip mounted above and soldered to the first die. The method includes positioning the leadframe, first die and first clip in a vertically stacked relationship and nonsolderingly locking the first clip in laterally nondisplaceble relationship with the leadframe. A stacked semiconductor package and an intermediate product produced in making a stacked semiconductor package are also disclosed.

Abstract: A semiconductor device includes a first semiconductor element; a first thick plate portion that is electrically connected to an electrode on a lower surface side of the first semiconductor element, and is formed by a conductor; a second semiconductor element that is arranged such that a main surface of the second semiconductor element faces a main surface of the first semiconductor element; a second thick plate portion that is electrically connected to an electrode on a lower surface side of the second semiconductor element, and is formed by a conductor; a third thick plate portion that is electrically connected to an electrode on an upper surface side of the first semiconductor element, and is formed by a conductor; a fourth thick plate portion that is electrically connected to an electrode on an upper surface side of the second semiconductor element, and is formed by a conductor; a first thin plate portion that is provided on the second thick plate portion, is formed by a conductor, and is thinner than the

Abstract: A leadframe (e.g., incorporated in a device package) includes a feature (e.g., a die pad or lead) with a vent hole formed between first and second opposed surfaces. The cross-sectional area of the vent hole varies substantially between the surfaces (e.g., the vent hole has a constricted portion). The vent hole may be formed from a first opening extending from the first surface toward the second surface to a first depth that is less than a thickness of the leadframe feature, and a second opening extending from the second surface toward the first surface to a second depth that is less than the thickness of the leadframe feature, but that is large enough for the second opening to intersect the first opening. Vertical central axes of the openings are horizontally offset from each other, and the constricted portion of the vent hole corresponds to the intersection of the openings.

Abstract: A method includes providing a semiconductor chip having a first main surface and a layer of solder material deposited on the first main surface, wherein the layer of solder material has a roughness of at least 1 ?m. The semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. The semiconductor chip is pressed on the carrier with a pressure of at least 1 Newton per mm2 of surface area of the first main surface and heat is applied to the solder material.

Abstract: There is provided a method of manufacturing a lead frame, the method including: preparing a lead frame raw material; forming openings in the lead frame raw material so that the lead frame material includes: a die pad; a die pad supporting portion supporting the die pad; a rail portion supporting the die pad supporting portion; a lead supporting portion having both ends fixed to the die pad supporting portion; and a plurality of leads having a first end connected to the rail portion and a second end connected to the lead supporting portion; plating the lead frame raw material having the openings with a plating layer; and removing the lead supporting portion.

Abstract: The purpose of the present invention is to increase the reliability of a semiconductor device in which a semiconductor element and a substrate are connected by solder and which is molded by resin. Solder containing easily volatized metals (Zn, Mg, Sb) is used for a solder material 106, and after a semiconductor element 104 is connected to a lead frame 102 and wire bonding is carried out, vacuum heat treatment is applied, the easily volatized metals in the solder are volatized to adhere to a substrate surface, and an alloy 103 with the lead frame is formed, thereby roughening the substrate surface and improving the adhesive strength of a sealing resin 101 and the substrate.

Abstract: In one embodiment, a micro lead frame structure includes one or more stiffness reinforcing structures formed on leads and/or connecting structures. The stiffness reinforcing structures can be formed by leaving predetermined portions of the micro lead frame at full thickness including, for example, portions of an inner lead, portions of an outer lead, and portions of a connecting bar, combinations thereof, and other structures. The stiffness reinforcing structures are configured to reduce deformation defects and electrical short defects caused by assembly processes.

Abstract: A semiconductor device has a die support and external leads formed integrally from a single sheet of electrically conductive material. A die mounting substrate is mounted on the die support, with bonding pads coupled to respective external connection pads on an external connector side of the substrate. A die is attached to the die mounting substrate with die connection pads. Bond wires selectively electrically couple the die connection pads to the external leads and the bonding pads and electrically conductive external protrusions are mounted to the external connection pads. An encapsulant covers the die and bond wires. The external protrusions are located at a central region of a surface mounting side of the package and the external leads project outwardly from locations near the die support towards peripheral edges of the package.

Abstract: One embodiment is directed towards a method of manufacturing a packaged circuit. The method includes partially etching an internal surface of a lead frame at dividing lines between future sections of the lead frame as first partial etch. One or more dies are attached to the internal surface of the lead frame and encapsulated. The method also includes partially etching an external surface of the lead frame at the dividing lines to disconnect different sections of lead frame as a second partial etch, wherein the second partial etch removes a laterally wider portion of the lead frame than the first partial etch of the internal surface; and partially etching the external surface of the lead frame as a third partial etch, wherein the third partial etch overlaps a portion of the second partial etch and extends deeper into the lead frame than the second partial etch.

Abstract: A quad flat no-lead (QFN) packaging structure. The QFN packaging structure includes a metal substrate, a first outer die pad formed on the metal substrate, and a first die coupled to a top surface of the first outer die pad. The QFN packaging structure also includes a plurality of I/O pads formed on the metal substrate, and a first metal layer containing a plurality of inner leads corresponding to the plurality of I/O pads and extending to proximity of the die. The first metal layer is formed on the metal substrate by a multi-layer electrical plating process such that a lead pitch of the plurality of inner leads is significantly reduced. Further, the QFN packaging structure includes metal wires connecting die and the plurality of inner leads, and a second metal layer formed on a back surface of the plurality of I/O pads and the die pad.

Abstract: A lead frame includes a die pad and a plurality of lead portions each including an internal terminal and an external terminal. The external terminals of the plurality of lead portions are arranged in an alternately staggered form such that the respective external terminals of a pair of lead portions adjacent to each other are alternatively located on an inside or an outside. A lead portion has an inside region located on the inside of a first external terminal, an outside region located on the outside of the first external terminal, and an external terminal region having the first external terminal. The inside region and the outside region are each formed thin by means of half etching. A maximum thickness of the outside region is larger than a maximum thickness of the inside region.

Abstract: An electronic device package 100 comprising a lead frame 105 having at least one lead 110 with a notch 205. The notch includes at least one reentrant angle 210 of greater than 180 degrees and the notch is located distal to a cut end 1010 of the lead.

Abstract: To enhance the reliability of a semiconductor device. The semiconductor device includes die pads, over which a first semiconductor chip and a second semiconductor chip are mounted respectively, a plurality of support pins that support each of the die pads, a plurality of inner leads and outer leads arranged around the die pads, a plurality of wires that electrically couple the semiconductor chips to the inner leads, and a sealing body that seals the semiconductor chips, the inner leads, and the wires. Each of the die pads is supported by three support pins integrally formed together with the die pad, and each of second support pins of each pair of the three support pins is arranged between the inner leads adjacent to each other.

Abstract: Embodiments described herein relate to manufacturing a device. The method includes etching at least one recess pattern in an internal surface of a lead frame, the at least one recess pattern including a perimeter recess that defines a perimeter of a mounting area. The method also includes attaching a component to the internal surface of the lead frame such that a single terminal of the component is attached in the mounting area and the single terminal covers the perimeter recess, wherein the perimeter recess has a size and shape such that the recess is proximate a perimeter of the single terminal.

Abstract: A semiconductor package having a die having a plurality of electrically continuous die wire bonding sites includes a first die wire bonding site and a second die wire bonding site. The package includes a substrate having a plurality of electrically continuous substrate wire bonding sites including a first substrate wire bonding site and a second substrate wire bonding site. A first bondwire is connected between the first die wire bonding site and the first substrate wire bonding site and a second bondwire is connected between the second die wire bonding site and the second substrate wire bonding site. The first and second bondwires lie in adjacent, substantially parallel bondwire planes. The second bondwire is substantially skewed with respect to said first bondwire.

Abstract: A method and apparatus for packaging a semiconductor chip is presented. A semiconductor device includes a chip, a lead, and an encapsulant. The encapsulant includes a stabilization layer, a laminate molding layer connected to the stabilization layer, and a conductive strip connected to the laminate molding layer. The conductive strip electrically connects the contact area of the chip to the lead.

Abstract: A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies.