Abstract: A semiconductor device comprises a carrier. Further, the semiconductor devices comprises a semiconductor chip comprising a first main surface and a second main surface opposite to the first main surface, wherein a first electrode is arranged on the first main surface and the semiconductor chip is mounted on the carrier with the second main surface facing the carrier. Further, an encapsulation body embedding the semiconductor chip is provided. The semiconductor device further comprises a contact clip, wherein the contact clip is an integral part having a bond portion bonded to the first electrode and having a terminal portion forming an external terminal of the semiconductor device.

Abstract: A packaged semiconductor device may include a leadframe and a die carrier mounted to the leadframe. The die carrier is formed from an electrically and thermally conductive material. A die is mounted to a surface of the die carrier with die attach material having a melting point in excess of 240° C. A first electrical interconnect couples the die and the leadframe. A housing covers portions of the leadframe, die carrier, die and first electrical interconnect.

Abstract: A semiconductor package and a method for fabricating the same are provided. A leadframe including a die pad and a plurality of peripheral leads is provided. A carrier, having a plurality of connecting pads formed thereon, is attached to the die pad, wherein a planar size of the carrier s greater than that of the die pad, allowing the connecting pads on the carrier to be exposed from the die pad. At least a semiconductor chip is attached to a side of an assembly including the die pad and the carrier, and is electrically connected to the connecting pads of the carrier and the leads via bonding wires. A package encapsulant encapsulates the semiconductor chip, the bonding wires, a part of the carrier and a part of the leadframe, allowing a bottom surface of the carrier and a part of the leads to be exposed from the package encapsulant.

Abstract: A semiconductor package according to the present invention includes: a semiconductor element where a high frequency signal is input or output; a planar lead terminal having an end electrically connected to an input terminal or an output terminal of the semiconductor element; an encapsulation resin for encapsulating the lead terminal and the semiconductor element, the lead terminal having another end exposed from the resin; and a ground enhancing metal body encapsulated in the encapsulation resin, having a first main surface facing the lead terminal and a second main surface exposed from the encapsulation resin, wherein the ground enhancing metal body has a shape with a cross section parallel to the second main surface and having a smaller area than an area of the first main surface.

Abstract: A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding.

Abstract: A method of manufacturing an LED package includes mounting a large panel frame/substrate (LPF/S) having a substantially square shape to a ring. The LPF/S includes a plurality of die pads and a corresponding plurality of leads arranged in a matrix pattern. Each of the die pads includes a planar chip attach surface. An LED chip is attached to the planar chip attach surface of each of the die pads. An encapsulant material is applied overlaying the LED chips and at least a part of the LPF/S. Each die pad and corresponding leads are separated from the LPF/S to form individual LED packages. The steps of attaching the LED chips and applying the encapsulant material are performed while the LPF/S is mounted to the ring.

Abstract: A semiconductor device has a die support and external leads formed integrally from a single sheet of electrically conductive material. A die mounting substrate is mounted on the die support, with bonding pads coupled to respective external connection pads on an external connector side of the substrate. A die is attached to the die mounting substrate with die connection pads. Bond wires selectively electrically couple the die connection pads to the external leads and the bonding pads and electrically conductive external protrusions are mounted to the external connection pads. An encapsulant covers the die and bond wires. The external protrusions are located at a central region of a surface mounting side of the package and the external leads project outwardly from locations near the die support towards peripheral edges of the package.

Abstract: A semiconductor memory card includes a lead frame having external connection terminals, a controller chip mounted on the lead frame and a memory chip mounted on the lead frame. The lead frame, the controller chip, and the memory chip are sealed with a sealing resin layer that has a surface at which the external connection terminals are exposed and a recess surrounding the external connection terminals.

Abstract: Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition.

Abstract: A wireless multichip module has a leadframe structure 10 with potions for receiving flip-chip mounted dies, including an integrated circuit 20 and high and low side mosfets 30, 40 to form a half-bridge circuit encapsulated in molding compound 70. The module is assembled without any bond wires. The module may also carry passive components including an external input capacitor 150 or an internal input capacitor 350.

Abstract: To enhance the reliability of a semiconductor device. The semiconductor device includes die pads, over which a first semiconductor chip and a second semiconductor chip are mounted respectively, a plurality of support pins that support each of the die pads, a plurality of inner leads and outer leads arranged around the die pads, a plurality of wires that electrically couple the semiconductor chips to the inner leads, and a sealing body that seals the semiconductor chips, the inner leads, and the wires. Each of the die pads is supported by three support pins integrally formed together with the die pad, and each of second support pins of each pair of the three support pins is arranged between the inner leads adjacent to each other.

Abstract: Disclosed are flip-chip package structures and methods for an integrated switching power supply. In one embodiment, a flip-chip package structure can include: (i) a die with an integrated switching power supply, where a first surface of the die includes first bumps with different polarities; (ii) a redistribution layer including redistribution layer units, each having a first surface to connect bumps with a same polarity from the first bumps, the redistribution layer having a second surface including second bumps to redistribute polarities; (iii) a lead frame having pins, where a first surface of the lead frame can connect bumps with a same polarity from the second bumps; and (iv) a flip-chip package configured to package the die, the redistribution layer, the first and second bumps, and the lead frame, where a second surface of the lead frame provides electrical connectivity between the integrated switching power supply and a PCB.

Abstract: Provided is a coupling assembly of a power semiconductor device and a printed circuit board (PCB). The coupling assembly of the power semiconductor device and the printed circuit board (PCB) includes a PCB, a power semiconductor device comprising a plurality of legs electrically connected to a circuit pattern disposed on the PCB, a connection member disposed above the power semiconductor device, the connection member being formed of an electrically conductive material, a main fixing unit fixing the power semiconductor device to the PCB, and a housing disposed outside the PCB. Thus, a coupling force between the power semiconductor device and the PCB and electric efficiency may be improved to a heat generation amount. In addition, heat may be more quickly dissipated through the connection member to improve a cooling effect.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having a single integral structure with a paddle central portion surrounded by a paddle peripheral portion; forming a terminal adjacent the package paddle; mounting an integrated circuit over the paddle central portion; and forming an encapsulation over the integrated circuit and the terminal, the encapsulation free of delamination with the encapsulation directly on the paddle peripheral portion.

Abstract: To provide an inexpensive lead component which can be easily connected to a semiconductor chip and which has satisfactory connectability. There is provided a lead component including a base material having a connection part for connecting to a semiconductor chip, comprising: a solder part having a Zn layer made of a Zn-bonding material rolled and clad-bonded on the base material, and an Al layer made of an Al-bonding material rolled and clad-bonded on the Zn layer, in a prescribed region including the connection part on the base material; and the solder part further comprising a metal thin film composed of one kind or two kinds or more of Au, Ag, Cu, Ni, Pd, and Pt covering a surface of the Al layer.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent the package paddle, the lead having a lead overhang protruding from a lead non-horizontal side and a lead ridge protruding from the lead non-horizontal side; mounting an integrated circuit over the package paddle; connecting an electrical connector to the lead and the integrated circuit; and forming an encapsulation over the integrated circuit, the lead, and the package paddle, the encapsulation under the lead overhang.

Abstract: A method of establishing conductive connections is disclosed. The method includes providing an integrated circuit die having a plurality of solder balls each of which has an oxide layer on an outer surface of the solder ball. The method also includes performing a heating process to heat at least the solder balls and applying a force causing each of a plurality of piercing bond structures on a substrate to pierce one of the solder balls and its associated oxide layer to thereby establish a conductive connection between the solder ball and the piercing bond structure.

Abstract: A leadframe (e.g., incorporated in a device package) includes a feature (e.g., a die pad or lead) with a vent hole formed between first and second opposed surfaces. The cross-sectional area of the vent hole varies substantially between the surfaces (e.g., the vent hole has a constricted portion). The vent hole may be formed from a first opening extending from the first surface toward the second surface to a first depth that is less than a thickness of the leadframe feature, and a second opening extending from the second surface toward the first surface to a second depth that is less than the thickness of the leadframe feature, but that is large enough for the second opening to intersect the first opening. Vertical central axes of the openings are horizontally offset from each other, and the constricted portion of the vent hole corresponds to the intersection of the openings.

Abstract: Disclosed herein is a power module package including: a first substrate; a second substrate having a pad for connection to the first substrate formed on one side or both sides of one surface thereof and having external connection terminals for connection to the outside formed on the other surface thereof; and a lead frame having one end bonded to the first substrate and the other end bonded to the pad of the second substrate to thereby vertically connect the first and second substrates to each other.

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract: A process of manufacturing an LED lamp strip includes the steps of forming a plurality of through holes on an adhesive tape, mounting the adhesive tape to a top side of a scrollable lead frame, bonding a plurality of LED chips to the top side of the scrollable lead frame according to the positions of the through holes, packaging the LED chips respectively, and finally cutting the scrollable lead frame. In light of this, the LED lamp strip can be produced under the circumstances of low production cost and less production time.

Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections.

Abstract: In a semiconductor device, a lead frame made of a copper alloy prevents exfoliation occurring near the surface of the lead frame. A copper oxide layer is formed on the base material made of a copper alloy by immersing the base material into a solution of a strong oxidizer. The copper oxide layer serves as an outermost layer and consists of a copper oxide other than a copper oxide in the form of needle crystals.

Abstract: A semiconductor device which can reduce a heat stress to a solder layer while suppressing an increase of thermal resistance is provided. A semiconductor device includes a semiconductor element, a solder layer which is arranged on at least one surface of the semiconductor element and a lead frame which is arranged on the solder layer so that a porous nickel plating part is sandwiched between the lead frame and the solder layer. Compared with a case that the semiconductor element and the lead frame are jointed by a solder directly, an increased part of a thermal resistance of the solder junction is held down only to a part of the porous nickel plating part and a thermal resistance applied to the solder layer can be reduced.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a die paddle having an internal portion with a trench along a perimeter of the die paddle; forming an interconnect having a concave indentation and an upper portion, the upper portion, opposite the concave indentation, aligned horizontally to the internal portion; attaching an integrated circuit device on the die paddle, the trench between the integrated circuit device and the perimeter; attaching an electrical connector to the integrated circuit device and to the upper portion; and applying an encapsulation over the integrated circuit device, the electrical connector, the die paddle, and the interconnect, the concave indentation exposed below the encapsulation.

Abstract: The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an array of leads having a jumper lead and a covered contact; coupling an insulated bonding wire between the jumper lead and the covered contact; attaching an integrated circuit die over the covered contact; and coupling a bond wire between the integrated circuit die and the jumper lead including coupling the integrated circuit die to the covered contact through the insulated bonding wire.

Abstract: A plastic package includes a plurality of terminal members each having an outer terminal, an inner terminal, and a connecting part connecting the outer and the inner terminal; a semiconductor device provided with terminal pads connected to the inner terminals with bond wires; and a resin molding sealing the terminal members, the semiconductor device and the bond wires therein. The inner terminals of the terminal members are thinner than the outer terminals and have contact surfaces. The upper, the lower and the outer side surfaces of the outer terminals, and the lower surfaces of the semiconductor device are exposed outside. The inner terminals, the bond wires, the semiconductor device and the resin molding are included in the thickness of the outer terminals.

Abstract: An integrated circuit package system includes: forming an anti-peel pad having both a concave ring and an external terminal with the concave ring, having a peripheral wall, surrounding the external terminal; connecting an integrated circuit with the anti-peel pad; and forming an encapsulation over the integrated circuit, the concave ring, and the external terminal with the encapsulation under the peripheral wall.

Abstract: A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package.

Abstract: A chip packaging method includes the steps of: attaching a first tape to a metal plate; patterning the metal plate to form a plurality of terminal pads and a plurality of leads, wherein the plurality of terminal pads and the plurality of leads are disposed on two opposite sides of a central void region, the plurality of terminal pads on each side are arranged in at least two rows spaced apart from each other in the direction away from the central void region, and each lead has a first end portion extending to the central void region and a second end portion connecting to a corresponding terminal pad; attaching a second tape having openings to the plurality of terminal pads, wherein each of the openings exposes the central void region and the first end portions of the leads; removing the first tape; attaching a chip to the plurality of terminal pads and the plurality of leads, wherein a plurality of bond pads on the chip are corresponding to the central void region; and connecting the bond pads to the first en

Abstract: The multi-chip leadless module 200 has integrated circuit (IC) 150, dual re-channel mosfet 110, IC leads 210, 211, 212, gate leads 213, 213, and source leads 217-220 encapsulated in resin 250. The IC 150 and the dual n-channel mosfet 110 are mounted face down on the leads. IC leads 210, 211, 212 are made of planar metal and connect, respectively, to the electrodes TEST, VDD and VM on the IC 150 using a flip chip technique to assemble the leads on copper pillars or copper studs.

Abstract: A wiring board includes a substrate having a cavity, and an electronic component accommodated in the cavity of the substrate. The substrate has a thickness which is greater than a thickness of the electronic component such that a ratio of the thickness of the substrate to the thickness of the electronic component is set in a range of 0.3 or greater and 0.7 or less.

Abstract: This invention is directed to provide a method of manufacturing a resin molded semiconductor device with high reliability by preventing a resin leakage portion from occurring due to burrs on a lead frame formed by punching. The method of manufacturing the resin molded semiconductor device according to the invention includes bonding a semiconductor die on an island in a lead frame, electrically connecting the semiconductor die with the lead frame, resin-molding the lead frame on which the semiconductor die is bonded, and applying prior to the resin-molding a compressive pressure that is higher than a clamping pressure applied in the resin-molding to a region of the lead frame being clamped by molds in the resin-molding of the lead frame.

Abstract: A semiconductor device of an illustrative embodiment includes a die, a lead frame including a plurality of leads having substantial portions arranged in a lead plane and electrically connected to the die. Most preferably, the package includes at least a substantial portion of one conductive element arranged in a plane positioned adjacent the lead frame and substantially parallel to the lead plane, the conductive element being capacitively coupled to the leads such that the conductive element and at least one of the leads cooperatively define a controlled-impedance conduction path, and an encapsulant which encapsulates the leads and the conductive element. The leads and, desirably, the conductive element have respective connection regions which are not covered by the encapsulant.

Abstract: A semiconductor device includes a first semiconductor element; a first thick plate portion that is electrically connected to an electrode on a lower surface side of the first semiconductor element, and is formed by a conductor; a second semiconductor element that is arranged such that a main surface of the second semiconductor element faces a main surface of the first semiconductor element; a second thick plate portion that is electrically connected to an electrode on a lower surface side of the second semiconductor element, and is formed by a conductor; a third thick plate portion that is electrically connected to an electrode on an upper surface side of the first semiconductor element, and is formed by a conductor; a fourth thick plate portion that is electrically connected to an electrode on an upper surface side of the second semiconductor element, and is formed by a conductor; a first thin plate portion that is provided on the second thick plate portion, is formed by a conductor, and is thinner than the

Abstract: There is provided a semiconductor package including: at least one internal lead having at least one electronic component mounted on a surface thereof; a molding unit sealing the electronic component and the internal lead; at least one external lead extending from the internal lead and protruding outwardly from ends of the molding unit; and a stopper provided on the external lead.

Abstract: A semiconductor device and method is disclosed. One embodiment provides a method comprising placing a first semiconductor chip on a carrier. After placing the first semiconductor chip on the carrier, an electrically insulating layer is deposited on the carrier. A second semiconductor chip is placed on the electrically insulating layer.

Abstract: A lead frame has a flag, a peripheral frame, and main tie bars coupling the flag to the peripheral frame. At least one cross tie bar extends between two of the main tie bars and an inner row of external connector pads extending from an inner side of the cross tie bar and an outer row of external connector pads extending from an outer side of the cross tie bar. Both an inner non-electrically conductive support bar and an outer non-electrically conductive support bar are attached across the two of the main tie bars. The inner non-electrically conductive support bar is attached to upper surfaces of the two of the main tie bars and to upper surfaces of the inner row of the external connector pads.

Abstract: An integrated circuit package system comprising: forming a paddle having a hole and an external interconnect; mounting an integrated circuit device having an active side to the paddle with the active side facing the paddle and the hole; connecting a first internal interconnect between the active side and the external interconnect through the hole; and encapsulating the integrated circuit device, the paddle, the first internal interconnect, and the external interconnect with the external interconnect partially exposed.

Abstract: A wafer-level semiconductor package method comprising the step of providing a first wafer comprising a plurality of first dies each having a first, a second and a third electrodes formed on its front surface; attaching a second die having a fourth and a fifth electrodes formed on its front surface and a sixth electrode formed at its back surface onto each of the first die of the first wafer with the sixth electrode at the back surface of the second die attached and electrically connected to the second electrode at the front surface of the first die; and cutting the first wafer to singulate individual semiconductor packages.

Abstract: An ultra-thin Quad Flat No-Lead (QFN) semiconductor chip package having a leadframe with lead terminals formed by recesses from both the top and bottom surfaces and substantially aligned contact areas formed on either the top or bottom surfaces. A die is electrically connected to the plurality of lead terminals and a molding compound encapsulates the leadframe and die together so as to form the ultra-thin QFN package. Accordingly, the substantially aligned contact areas are exposed on both the top and bottom surfaces of the package. The present disclosure also provides an ultra-thin Optical Quad Flat No-Lead (OQFN) semiconductor chip package, a stacked semiconductor module comprising at least two QFN semiconductor chip packages, and a method for manufacturing an ultra-thin Quad Flat No-Lead (QFN) semiconductor packages.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead bottom body, a lead top body, and a lead top conductive layer directly on the lead top body, the lead top conductive layer having a top protrusion and a top non-vertical portion, the lead bottom body having a horizontally contiguous structure; connecting an integrated circuit to the top protrusion; and forming an encapsulation covering the integrated circuit and exposing a top non-vertical upper side of the top non-vertical portion.

Abstract: A process for assembling a Chip-On-Lead packaged semiconductor device includes the steps of: mounting and sawing a wafer to provide individual semiconductor dies; performing a first molding operation on a lead frame; depositing epoxy on the lead frame via a screen printing process; attaching one of the singulated dies on the lead frame with the epoxy, where the die attach is done at room temperature; and curing the epoxy in an oven. Throughput improvements may be ascribed to not including a hot die attach process. An optional plasma cleaning step may be performed, which greatly improves wire bonding quality and a second molding quality. In addition, since a first molding operation is performed before the formation of epoxy to avoid the problem of the epoxy hanging in the air, the delamination risk between the epoxy and the die is avoided.

Abstract: An electronic device and method of manufacturing. One embodiment includes attaching a first semiconductor chip to a first metallic clip. The first semiconductor chip is placed over a leadframe after the attachment of the first semiconductor chip to the first metallic clip.

Abstract: A circuit board includes an insulation layer, an electrically conductive layer, and a solder mask layer. The insulation layer has a plurality of through holes passing through. The electrically conductive layer is formed on a surface of the insulation layer and covers the through holes. The electrically conductive layer has a plurality of portions exposed in the through holes to serve as a plurality of first conductive pads. The solder mask layer covers the electrically conductive layer and defines a plurality of openings to expose parts of the electrically conductive layer. Parts of the electrically conductive layer are exposed to the solder mask layer to serve as a plurality of second conductive pads. The second conductive pads are electrically connected to the first conductive pads respectively. This disclosure further relates to a chip package and a method of manufacturing the same.

Abstract: According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.

Abstract: A system and method for manufacturing an electric device package are disclosed. An embodiment comprises comprising a first carrier contact, a first electric component, the first electric component having a first top surface and a first bottom surface, the first electric component comprising a first component contact disposed on the first top surface, the first bottom surface being connected to the carrier and an connection element comprising a second electric component and an interconnect element, the connection element having a connection element top surface and a connection element bottom surface, wherein the connection element bottom surface comprises a first connection element contact and a second connection element contact, and wherein the first connection element contact is connected to the first component contact and the second connection element contact is connected to the first carrier contact. The packaged device further comprises an encapsulant encapsulating the first electric component.

Abstract: Ball grid array to pin grid array conversion methods are provided. An example method can include coupling a plurality of solder balls to a respective plurality of pin grid array contact pads. Each of the plurality of solder balls is encapsulated in a fixed material. A portion of the plurality of solder balls and a portion of the fixed material is removed to provide a plurality of exposed solder balls. The exposed solder balls are softened and each of a plurality of pin members is inserted in a softened, exposed, solder ball. The plurality of pin members forms a pin grid array package.

Abstract: Methods and systems for altering the electrical resistance of a wiring path. The electrical resistance of the wiring path is compared with a target electrical resistance value. If the electrical resistance of the wiring path exceeds the target electrical resistance value, an electrical current is selectively applied to the wiring path to physically alter a portion of the wiring path. The current may be selected to alter the wiring path such that the electrical resistance drops to a value less than or equal to the target electrical resistance value.