And Encapsulating Patents (Class 438/124)
  • Patent number: 11443997
    Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a first substrate, a second substrate, and a barrier structure. The first substrate has a first surface and a second surface opposite to the first surface. The second substrate has a first surface facing the second surface of the first substrate. The first substrate electrically bonds to the second substrate through a conductive terminal disposed between the second surface of the first substrate and the first surface of the second substrate. The barrier structure is disposed adjacent to the first surface of the first substrate.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: September 13, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei Chih Cho, Chun Chen Chen, Shao-Lun Yang
  • Patent number: 11419217
    Abstract: A power electronic substrate includes a metallic baseplate having a first and second surface opposing each other. An electrically insulative layer also has first and second surfaces opposing each other, its first surface coupled to the second surface of the metallic baseplate. A plurality of metallic traces each include first and second surfaces opposing each other, their first surfaces coupled to the second surface of the electrically insulative layer. At least one of the metallic traces has a thickness measured along a direction perpendicular to the second surface of the metallic baseplate that is greater than a thickness of another one of the metallic traces also measured along a direction perpendicular to the second surface of the metallic baseplate. In implementations the electrically insulative layer is an epoxy or a ceramic material. In implementations the metallic traces are copper and are plated with a nickel layer at their second surfaces.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: August 16, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng Lin, Sadamichi Takakusaki
  • Patent number: 11410898
    Abstract: A manufacturing method of a mounting structure, the method including: a step of preparing a mounting member including a first circuit member and a plurality of second circuit members placed on the first circuit member via bumps, the mounting member having a space between the first circuit member and the second circuit member; a step of preparing a sheet having a space maintaining layer; a disposing step of disposing the sheet on the mounting member such that the space maintaining layer faces the second circuit members; and a sealing step of pressing the sheet against the first circuit member and heating the sheet, to seal the second circuit members so as to maintain the space, and to cure the sheet. The bumps are solder bumps. The space maintaining layer after curing has a glass transition temperature of higher than 125° C., and a coefficient of thermal expansion at 125° C. or lower of 20 ppm/K or less.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: August 9, 2022
    Assignee: NAGASE CHEMTEX CORPORATION
    Inventors: Takayuki Hashimoto, Takuya Ishibashi, Kazuki Nishimura
  • Patent number: 11195780
    Abstract: A chip package assembly and method for fabricating the same are provided which incorporate phase change materials within the chip package assembly for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die stacked on the substrate, a dielectric filler layer, a cover and a phase change material. The phase change material is sealed within a recess formed between the first IC dies and the cover.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: December 7, 2021
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Gamal Refai-Ahmed, Suresh Ramalingam
  • Patent number: 11181704
    Abstract: A technique for fabricating bumps on a substrate is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared. A bump base is formed on each pad of the substrate. Each bump base has a tip extending outwardly from the corresponding pad. A resist layer is patterned on the substrate to have a set of holes through the resist layer. Each hole is aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad. The set of the holes in the resist layer is filled with conductive material to form a set of bumps on the substrate. The resist layer is stripped from the substrate with leaving the set of the bumps.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: November 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji Nakamura, Masao Tokunari
  • Patent number: 11166385
    Abstract: A component carrier is disclosed. The component carrier includes: i) at least one electrically insulating layer structure and at least one electrically conductive layer structure, wherein the electrically conductive layer structure is formed in or below the electrically insulating layer structure, and ii) a laser via formed in the electrically insulating layer structure and extending down to the electrically conductive layer structure, wherein the laser via is at least partially filled with an electrically conductive material. Hereby, a connection diameter at a first end of the laser via at the electrically conductive layer structure is equal to or larger than an opening diameter at a second end of the laser via facing away from the electrically conductive layer structure.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: November 2, 2021
    Assignee: AT&S (China) Co. Ltd.
    Inventors: Yee-Bing Ling, Kenny Cao, Jackson Xu
  • Patent number: 11139229
    Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Jack E. Murray
  • Patent number: 11112570
    Abstract: A technique for fabricating bumps on a substrate is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared. A bump base is formed on each pad of the substrate. Each bump base has a tip extending outwardly from the corresponding pad. A resist layer is patterned on the substrate to have a set of holes through the resist layer. Each hole is aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad. The set of the holes in the resist layer is filled with conductive material to form a set of bumps on the substrate. The resist layer is stripped from the substrate with leaving the set of the bumps.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: September 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji Nakamura, Masao Tokunari
  • Patent number: 11107768
    Abstract: A display device comprises a display panel substrate and a glass substrate over said display panel substrate, wherein said display panel substrate comprises multiple contact pads, a display area, a first boundary, a second boundary, a third boundary and a fourth boundary, wherein said display area comprises a first edge, a second edge, a third edge and a fourth edge, wherein said first boundary is parallel to said third boundary and said first and third edges, wherein said second boundary is parallel to said fourth boundary and said second and fourth edges, wherein a first least distance between said first boundary and said first edge, wherein a second least distance between said second boundary and said second edge, a third least distance between said third boundary and said third edge, a fourth distance between said fourth boundary and said fourth edge, and wherein said first, second, third and fourth least distances are smaller than 100 micrometers, and wherein said glass substrate comprising multiple meta
    Type: Grant
    Filed: January 26, 2020
    Date of Patent: August 31, 2021
    Inventor: Ping-Jung Yang
  • Patent number: 11101246
    Abstract: In a semiconductor device, a first semiconductor chip and a second semiconductor chip are disposed between a first support member and a second support member. A first underlayer bonding material is disposed between the first semiconductor chip and the first support member. A second underlayer bonding material is disposed between the second semiconductor chip and the first support member. A first upper layer bonding material is disposed between the first semiconductor chip and the second support member. A second upper layer bonding material is disposed between the second semiconductor chip and the second support member.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: August 24, 2021
    Assignee: DENSO CORPORATION
    Inventors: Tomohito Iwashige, Takeshi Endo, Kazuhiko Sugiura
  • Patent number: 11062916
    Abstract: A heat sink (4) having a step in a bottom surface corner and a rectangular planar shape is disposed in an interior of a cavity (5) of a metal mold (1) and a first pin (2) is caused to project from a bottom surface of the cavity (5) to position the heat sink (4). A second pin (3) projecting from the bottom surface of the cavity (5) is disposed at the step of the positioned heat sink (4). After the heat sink (4) is positioned, the first pin (2) is lowered to the bottom surface of the cavity (5) and the heat sink (4) is sealed with the mold resin (10) with the second pin (3) being left projecting.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: July 13, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Ken Sakamoto
  • Patent number: 10867902
    Abstract: A power semiconductor module arrangement including two or more individual semiconductor devices each semiconductor device having a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame. The power semiconductor module arrangement further includes a frame surrounding the two or more individual semiconductor devices, and a casting compound at least partly filling a capacity within the frame, thereby at least partly enclosing the two or more individual semiconductor devices.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: December 15, 2020
    Assignee: Infineon Technologies AG
    Inventors: Olaf Hohlfeld, Peter Kanschat
  • Patent number: 10849232
    Abstract: A printed circuit board includes: a first insulating material; a metal layer disposed on a first surface of the first insulating material; a second insulating material disposed on the first surface of the first insulating material; a cavity penetrating through the second insulating material in an area of the second insulating material corresponding to the metal layer; and an insulating film disposed on a surface of the metal layer that is exposed by the cavity.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: November 24, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Byung-Seung Min
  • Patent number: 10770311
    Abstract: A stack package and a method of manufacturing the stack package are provided. The method includes: attaching a first semiconductor device onto a first surface of a first package substrate; attaching a molding resin material layer onto a first surface of a second package substrate; arranging the first surface of the first package substrate and the first surface of the second package substrate to face each other; compressing the first package substrate and the second package substrate while reflowing the molding resin material layer; and hardening the reflowed molding resin material layer.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: September 8, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-in Won, Jong-kak Jang, Dong-woo Kang, Do-yeon Kim
  • Patent number: 10707154
    Abstract: A semiconductor device includes leads, a semiconductor element and a sealing resin covering the leads and the semiconductor element. The sealing resin includes an obverse surface, a reverse surface, and an end surface between the obverse surface and the reverse surface. The leads include a peripheral lead with a reverse surface exposed from the reverse surface of the resin and with an outer end surface exposed from the end surface of the resin. The outer end surface is located inward from the end surface of the resin. The sealing resin includes an interior top surface connected to its end surface and the outer end surface of the lead. The interior top surface and the reverse surface of the resin face in the same direction.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: July 7, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Masato Ikeda, Motoharu Haga
  • Patent number: 10629565
    Abstract: A semiconductor device has a carrier with an adhesive layer formed over the carrier. Alignment marks are provided for picking and placing the electrical component on the carrier or adhesive layer. An electrical component is disposed on the adhesive layer by pressing terminals of the electrical component into the adhesive layer. The electrical component can be a semiconductor die, discrete component, electronic module, and semiconductor package. A leadframe is disposed over the adhesive layer. A shielding layer is formed over the electrical component. An encapsulant is deposited over the electrical component. The carrier and adhesive layer are removed so that the terminals of the electrical component extend out from the encapsulant for electrical interconnect. A substrate includes a plurality of conductive traces. The semiconductor device is disposed on the substrate with the terminals of the electrical component in contact with the conductive traces.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: April 21, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: JinHee Jung, OhHan Kim, InSang Yoon
  • Patent number: 10598874
    Abstract: A technique for fabricating bumps on a substrate is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared. A bump base is formed on each pad of the substrate. Each bump base has a tip extending outwardly from the corresponding pad. A resist layer is patterned on the substrate to have a set of holes through the resist layer. Each hole is aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad. The set of the holes in the resist layer is filled with conductive material to form a set of bumps on the substrate. The resist layer is stripped from the substrate with leaving the set of the bumps.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: March 24, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji Nakamura, Masao Tokunari
  • Patent number: 10600690
    Abstract: A method for handling a product substrate includes bonding a carrier to the product substrate by: applying a layer of a temporary adhesive having a first coefficient of thermal expansion onto a surface of the carrier; and bonding the carrier to the product substrate using the applied temporary adhesive. A surface of the temporary adhesive is in direct contact to a surface of the product substrate. The temporary adhesive includes or is adjacent a filler material having a second coefficient of thermal expansion which is smaller than the first coefficient of thermal expansion, so that stress occurs inside the temporary adhesive layer or at an interface to the product substrate or the carrier during cooling down of the temporary adhesive layer.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: March 24, 2020
    Assignee: Infineon Technologies AG
    Inventors: Georg Meyer-Berg, Claus von Waechter, Michael Bauer, Holger Doepke, Dominic Maier, Daniel Porwol, Tobias Schmidt
  • Patent number: 10418341
    Abstract: A semiconductor device has a carrier with an adhesive layer formed over the carrier. Alignment marks are provided for picking and placing the electrical component on the carrier or adhesive layer. An electrical component is disposed on the adhesive layer by pressing terminals of the electrical component into the adhesive layer. The electrical component can be a semiconductor die, discrete component, electronic module, and semiconductor package. A leadframe is disposed over the adhesive layer. A shielding layer is formed over the electrical component. An encapsulant is deposited over the electrical component. The carrier and adhesive layer are removed so that the terminals of the electrical component extend out from the encapsulant for electrical interconnect. A substrate includes a plurality of conductive traces. The semiconductor device is disposed on the substrate with the terminals of the electrical component in contact with the conductive traces.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: September 17, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: JinHee Jung, OhHan Kim, InSang Yoon
  • Patent number: 10373886
    Abstract: A preformed lead frame includes a metallic substrate, a plurality of spaced-apart conductive lead frame units and intersecting trenches, a molding layer, and a plurality of conductive pads. The lead frame units and the molding layer are formed on the substrate. Each of the lead frame units includes a die supporting portion, a plurality of lead portions surrounding and spaced apart from the die supporting portion, and a gap formed among the die supporting portion and the lead portions. The trenches are formed among the conductive lead frame units. The molding layer fills the gaps and the trenches. Each of the conductive pads is formed on a top surface of the die supporting portion of a respective one of the lead frame units.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: August 6, 2019
    Assignee: Chang Wah Technology Co., Ltd.
    Inventor: Chia-Neng Huang
  • Patent number: 10332816
    Abstract: Provided is a circuit device in which encapsulating resin to encapsulate a circuit board is optimized in shape, and a method of manufacturing the circuit device. A hybrid integrated circuit device, which is a circuit device according to the present invention includes a circuit board, a circuit element mounted on a top surface of the circuit board, and encapsulating resin encapsulating the circuit element, and coating the top surface, side surfaces, and a bottom surface of the circuit board. In addition, the encapsulating resin is partly recessed and thereby provided with recessed areas at two sides of the circuit board. The providing of the recessed areas reduces the amount of resin to be used, and prevents the hybrid integrated circuit device from being deformed by the cure shrinkage of the encapsulating resin.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: June 25, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Hideyuki Sakamoto
  • Patent number: 10325826
    Abstract: A substrate having a die attach area for receiving a semiconductor die includes a recessed area for receiving die attach adhesive. The recessed area prevents die attach adhesive from bleeding into the surrounding area and onto substrate connection sites, where it could compromise a wire bond formed on such a connection site. The recessed area has a zig-zag pattern, which allows for sufficient amounts of adhesive to be used to securely attach the die to the substrate, yet does not enlarge the recessed area such that the package size may be adversely affected.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: June 18, 2019
    Assignee: NXP USA, INC.
    Inventors: Ly Hoon Khoo, Chin Teck Siong, Vanessa Wyn Jean Tan
  • Patent number: 10128192
    Abstract: A semiconductor package structure including a redistribution layer (RDL) structure having a first surface and a second surface opposite thereto is provided. The RDL structure includes an inter-metal dielectric (IMD) layer and a first conductive layer disposed at a first layer-level of the IMD layer. A molding compound covers the first surface of the RDL structure. A first semiconductor die is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. A plurality of bump structures is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: November 13, 2018
    Assignee: MEDIATEK INC.
    Inventors: Min-Chen Lin, Che-Ya Chou, Nan-Cheng Chen
  • Patent number: 10085344
    Abstract: An electronic component includes an inner electrode inside of a main body and exposed at a surface of the main body, and an outer electrode on a surface of the main body and electrically connected to the inner electrode, wherein a plurality of recesses are provided in a surface of the outer electrode, and each of the plurality of recesses includes a portion in which a diameter of an opening of the recess gradually decreases toward an opening side of the recess.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: September 25, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masaki Hirota, Yoshikazu Sasaoka, Yasunori Taseda, Shinichiro Kuroiwa
  • Patent number: 10079190
    Abstract: A method of fabricating a package structure is provided, including forming a plurality of openings by removing a portion of the material on one side of a conductive layer, forming an insulating material as an insulating layer in the openings, removing a portion of the material on the other side of the conductive layer to serve as a wiring layer, disposing an electronic component on the wiring layer, and forming an encapsulating layer to cover the electronic component, thereby allowing the single wiring layer to be connected to the electronic component on one side and connected to solder balls on the other side thereof to shorten the signal transmission path. The present invention further provides a package structure thus fabricated.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: September 18, 2018
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD
    Inventors: Shih-Ping Hsu, Chin-Wen Liu, Tang-I Wu, Shu-Wei Hu
  • Patent number: 9870964
    Abstract: The present disclosure provides a technique including a method of manufacturing a semiconductor device, which is capable of improving a processing uniformity of a plurality of substrates. The method may include: (a) subjecting a substrate accommodated in one of a plurality of process chambers to a thermal process: (b) transferring the substrate processed in (a) by a transfer robot provided in a vacuum transfer chamber connected to the plurality of process chambers from the one of a plurality of process chambers to a loadlock chamber connected to the vacuum transfer chamber; and (c) cooling the substrate accommodated in the loadlock chamber by supplying an inert gas to the substrate accommodated in the loadlock chamber according to a cooling recipe.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: January 16, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC, INC.
    Inventors: Teruo Yoshino, Takeshi Yasui
  • Patent number: 9698116
    Abstract: A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer having a thickness of at least four (4) micrometers disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: July 4, 2017
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla
  • Patent number: 9554471
    Abstract: A packaging structure including: a cover secured to a first substrate and forming first and second distinct cavities between the cover and the first substrate, first and second channels formed in the first substrate and/or in the cover and/or between the first substrate and the cover, the first channel including a first end leading into the first cavity and a second end leading off the first cavity via a first hole passing through the cover, the second channel including a first end leading into the second cavity and a second end leading off the second cavity via a second hole passing through the cover, a height HA of the first channel at its second end is lower than a height HB of the second channel at its second end.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: January 24, 2017
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventor: Xavier Baillin
  • Patent number: 9530818
    Abstract: An image sensor die may include a pixel array formed in an image sensor substrate. The image sensor die may be mounted to a thin metal interconnect layer that has been deposited on a sacrificial carrier substrate. The thin metal interconnect layer may include one or more metal layers that are patterned to form metal traces that serve as contact pads, signal lines, and other interconnects in the interconnect layer. The image sensor die may be wire bonded, flip-chip mounted, or otherwise mechanically and electrically coupled to the metal interconnect layer. The sacrificial carrier substrate may be etched or otherwise removed to expose the metal interconnects on the metal interconnect layer. An array of solder balls may be formed on the exposed metal interconnects to form a ball grid array package, or the exposed contact pads may be plated to form a leadless chip carrier package.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: December 27, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Jonathan Michael Stern
  • Patent number: 9449907
    Abstract: Various methods and apparatus for joining stacked substrates to a circuit board are disclosed. In one aspect, a method of manufacturing is provided that includes coupling plural substrates to form a stack. At least one of the plural substrates is a semiconductor chip. Plural conductive vias are formed in a first of the plural substrates. Each of the plural conductive vias includes a first end positioned in the first substrate and a second end projecting out of the first substrate.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: September 20, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lei Fu, Frank Gottfried Kuechenmeister, Michael Zhuoying Su
  • Patent number: 9443791
    Abstract: A method of forming semiconductor devices on a leadframe structure. The leadframe structure comprising an array of leadframe sub-structures each having a semiconductor die arranged thereon. The method comprises; providing electrical connections between terminals of said lead frame sub-structures and said leadframe structure; encapsulating said leadframe structure, said electrical connections and said terminals in an encapsulation layer; performing a first series of parallel cuts extending through the leadframe structure and the encapsulation layer to expose a side portion of said terminals; electro-plating said terminals to form metal side pads; and performing a second series of parallel cuts angled with respect to the first series of parallel cuts, the second series of cuts extending through the lead frame structure and the encapsulation layer to singulate a semiconductor device from the leadframe structure.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: September 13, 2016
    Assignee: NXP B.V.
    Inventors: Chi Ho Leung, Ke Xue, Soenke Habenicht, Wai Hung William Hor, San Ming Chan, Wai Keung Ng
  • Patent number: 9362222
    Abstract: Embodiments of mechanisms for forming a semiconductor device structure are provided. The semiconductor device structure includes a metal-insulator-metal (MIM) capacitor formed on a substrate. The semiconductor device structure also includes an inductor formed on the MIM capacitor. The semiconductor device structure further includes a via formed between the MIM capacitor and the inductor, and the via is formed in a plurality of dielectric layers, and the dielectric layers comprise an etch stop layer.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: June 7, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hung Hsueh, Yen-Hsiang Hsu, Kuan-Chi Tsai
  • Patent number: 9257380
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: February 9, 2016
    Assignee: Intel Corporation
    Inventors: Ravi K. Nalla, John S. Guzek, Javier Soto Gonzalez, Drew W. Delaney, Hamid R. Azimi
  • Patent number: 9219019
    Abstract: A semiconductor device has a leadframe with a pad and a row of elongated leads with a solderable surfaces in a common plane; a package encapsulating the leadframe with an assembled semiconductor device, leaving the common-plane lead surfaces un-encapsulated and coplanar with the package material between adjacent leads, the row of aligned leads positioned along a package edge; and grooves in the package material cut in the common-plane surface, the grooves extend along a portion of each lead length, have a width and a depth about twice the width, and expose solderable lead surfaces.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: December 22, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Alok Kumar Lohia, Reynaldo Corpuz Javier, Andy Quang Tran
  • Patent number: 9129948
    Abstract: A semiconductor device has a die support and external leads formed integrally from a single sheet of electrically conductive material. A die mounting substrate is mounted on the die support, with bonding pads coupled to respective external connection pads on an external connector side of the substrate. A die is attached to the die mounting substrate with die connection pads. Bond wires selectively electrically couple the die connection pads to the external leads and the bonding pads and electrically conductive external protrusions are mounted to the external connection pads. An encapsulant covers the die and bond wires. The external protrusions are located at a central region of a surface mounting side of the package and the external leads project outwardly from locations near the die support towards peripheral edges of the package.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: September 8, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Meiquan Huang, Huan Wang, Jinsheng Wang, Naikou Zhou
  • Patent number: 9064873
    Abstract: A singulated semiconductor structure comprises a molding compound; a first conductive post in the molding compound having a first geometric shape in a top view; a second conductive post or an alignment mark in the molding compound having a second geometric shape in a top view, wherein the second geometric shape is different from the first geometric shape. The second conductive post or an alignment mark can be positioned at the corner, the center, the edge, or the periphery of the singulated semiconductor structure. The second geometric shape can be any geometric construct distinguishable from the first geometric shape. The second conductive post or an alignment mark can be placed at an active area or a non-active area of the singulated semiconductor structure.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: June 23, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Chun Miao, Shih-Wei Liang, Kai-Chiang Wu, Ming-Kai Liu, Yen-Ping Wang
  • Patent number: 9054115
    Abstract: According to one exemplary embodiment, an overmolded package includes a component situated on a substrate. The overmolded package further includes an overmold situated over the component and the substrate. The overmolded package further includes a wirebond cage situated over the substrate and in the overmold, where the wirebond cage surrounds the component, and where the wirebond cage includes a number of wirebonds. The wirebond cage forms an EMI shield around the component. According to this exemplary embodiment, the overmolded package further includes a conductive layer situated on a top surface of the overmold and connected to the wirebond cage, where the conductive layer forms an EMI shield over the component.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: June 9, 2015
    Assignee: Skyworks Solutions, Inc.
    Inventors: Dinhphuoc V. Hoang, Thomas E. Noll, Anil K. Agarwal, Robert W. Warren, Matthew S. Read, Anthony LoBianco
  • Patent number: 9048199
    Abstract: A semiconductor package and a method of manufacturing the semiconductor package are disclosed. A semiconductor package in accordance with an embodiment of the present invention includes a substrate, which has a ground circuit formed thereon, a semiconductor chip, which is mounted on the substrate, a conductive first shield, which is formed on an upper surface of the semiconductor chip and connected with the ground circuit, and a conductive second shield, which covers the substrate and the semiconductor chip and is connected with the first shield. With a semiconductor package in accordance with an embodiment of the present invention, grounding is possible between semiconductor chips because a shield is also formed on an upper surface of the semiconductor chip, and the shielding property can be improved by a double shielding structure.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: June 2, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Do-Jae Yoo, Jae-Cheon Doh
  • Publication number: 20150145126
    Abstract: A semiconductor device has a stress relief buffer mounted to a temporary substrate in locations designated for bump formation. The stress relief buffer can be a multi-layer composite material such as a first compliant layer, a silicon layer formed over the first compliant layer, and a second compliant layer formed over the silicon layer. A semiconductor die is also mounted to the temporary substrate. The stress relief buffer can be thinner than the semiconductor die. An encapsulant is deposited between the semiconductor die and stress relief buffer. The temporary substrate is removed. An interconnect structure is formed over the semiconductor die, encapsulant, and stress relief buffer. The interconnect structure is electrically connected to the semiconductor die. A stiffener layer can be formed over the stress relief buffer and encapsulant. A circuit layer containing active devices, passive devices, conductive layers, and dielectric layers can be formed within the stress relief buffer.
    Type: Application
    Filed: December 9, 2014
    Publication date: May 28, 2015
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Yaojian Lin, II Kwon Shim, Seng Guan Chow
  • Patent number: 9040353
    Abstract: A method for manufacturing a semiconductor light emitting device comprises a sealing step of sealing a semiconductor chip fixed on a lead frame with a sealing member, a removal step of removing the sealing member until a surface of the semiconductor chip becomes exposed, an irregularity formation step of forming fine irregularities on a bond surface formed in the removal step, and a bonding step of bonding a wavelength conversion member to the bond surface.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: May 26, 2015
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Takayoshi Yajima, Hiroshi Ito
  • Patent number: 9040357
    Abstract: A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: May 26, 2015
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Jun Lu, Kai Liu, Yan Xun Xue
  • Patent number: 9040359
    Abstract: A method for fabricating a molded interposer package includes performing a first anisotropic etching process to remove a portion of the metal sheet from a top surface of the metal sheet, thereby forming a plurality of first recesses in the metal sheet, forming a molding material covering the top surface, filling the first recesses, forming a plurality of first via openings in the molding material, wherein the first via openings expose the top surface, forming a plurality of first metal vias in the first via openings and a plurality of first redistribution layer patterns respectively on the first metal vias, performing a second anisotropic etching process to remove a portion of the metal sheet from a bottom surface of the metal sheet until a bottom of the molding material is exposed, and forming a solder mask layer on the molding material, leaving the first redistribution layer patterns exposed.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: May 26, 2015
    Assignee: MEDIATEK INC.
    Inventors: Thomas Matthew Gregorich, Andrew C. Chang, Tzu-Hung Lin
  • Publication number: 20150137351
    Abstract: A semiconductor device includes a die, a conductive post disposed adjacent to the die, and a molding surrounding the conductive post and the die, the molding includes a protruded portion protruded from a sidewall of the conductive post and disposed on a top surface of the conductive post. Further, a method of manufacturing a semiconductor device includes disposing a die, disposing a conductive post adjacent to the die, disposing a molding over the conductive post and the die, removing some portions of the molding from a top of the molding, and forming a recess of the molding above a top surface of the conductive post.
    Type: Application
    Filed: November 18, 2013
    Publication date: May 21, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: LI-HUI CHENG, PO-HAO TSAI, JUI-PIN HUNG
  • Patent number: 9034693
    Abstract: A method of manufacturing an integrated circuit package includes: forming a substrate including: forming a core layer, and forming vias in the core layer; forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: May 19, 2015
    Assignee: ST ASSEMBLY TEST SERVICES LTD.
    Inventors: Il Kwon Shim, Kwee Lan Tan, Jian Jun Li, Dario S. Filoteo, Jr.
  • Patent number: 9029203
    Abstract: This disclosure provides a semiconductor package and a method of fabricating the same. The semiconductor package includes an insulating layer; a plurality of traces and connection pads disposed in the insulating layer and protruded from the insulating layer; a plurality of bumps formed on the plurality of traces; a semiconductor chip disposed on the bumps; and an encapsulant formed on the insulating layer to encapsulate the semiconductor chip, the plurality of bumps, traces and connection pads. When the encapsulant is formed, voids can be prevented from being generated in the traces and the connection pads and thus the yield of process is significantly increased.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: May 12, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Pang-Chun Lin, Yueh-Ying Tsai, Yong-Liang Chen
  • Patent number: 9029194
    Abstract: A method of making an integrated circuit module starts with a top leadframe strip comprising a plurality of integrally connected top leadframes. A plurality of flipchip dies are mounted on the top leadframe strip with solder bumps of each flipchip bonded to predetermined pad portions on each of the top leadframes. The top leadframe strip is attached to a bottom leadframe strip. The bottom leadframe strip has a plurality of integrally connected bottom leadframes each having a central die attach pad (DAP) portion and a peripheral frame portion. A back face of each flipchip die contacts the DAP portion of each bottom leadframe. Lead portions of each top leadframe are attached to the peripheral frame portion of each bottom leadframe. The top leadframe strip is attached to the bottom leadframe strip with a back face of each flipchip die contacting the DAP portion of each bottom leadframe and with lead portions of each top leadframe attached to the peripheral frame portion of each bottom leadframe.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: May 12, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Lee Han Meng@Eugene Lee, Anis Fauzi bin Abdul Aziz, Susan Goh Geok Ling, Ng Swee Tiang
  • Patent number: 9029202
    Abstract: A semiconductor device package (100) includes a heat spreader (503) formed by depositing a first thin film layer (301) of a first metal on a top surface (150) of a die (110) and to exposed portions of a top surface of an encapsulant (208), depositing a second thin film layer (402) of a second metal on a top surface of the first thin film layer, and depositing a third layer (503) of a third metal on a top surface of the second thin film layer.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: May 12, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Weng Foong Yap, Jinbang Tang
  • Patent number: 9027238
    Abstract: A multilayered printed circuit board or a substrate for mounting a semiconductor device includes a semiconductor device, a first resin insulating layer accommodating the semiconductor device, a second resin insulating layer provided on the first resin insulating layer, a conductor circuit provided on the second resin insulating layer, and via holes for electrically connecting the semiconductor device to the conductor circuit, wherein the semiconductor device is accommodated in a recess provided in the first resin insulating layer, and a metal layer for placing the semiconductor device is provided on the bottom face of the recess. A multilayered printed circuit board in which the installed semiconductor device establishes electrical connection through the via holes is provided.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: May 12, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Sotaro Ito, Michimasa Takahashi, Yukinobu Mikado
  • Patent number: 9024427
    Abstract: A three dimensional package includes a substrate having a columnar part including a sidewall, and stairs or steps arranged along the sidewall of the columnar part in the form of multiple helixes twisted around the columnar part. Semiconductor integrated circuits (IC dies) are attached on one or both of the supporting surfaces of the stairs. The columnar part, the stairs and the IC dies can be encapsulated with a mold compound.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: May 5, 2015
    Assignee: Freescale Semiconductor. Inc
    Inventors: Huan Wang, Aipeng Shu, Shu An Yao
  • Publication number: 20150108621
    Abstract: Shielded device packages and related fabrication methods are provided. An exemplary device package includes one or more electrical components, a molding compound overlying the one or more electrical components, a frame structure circumscribing the one or more electrical components, and a shielding structure overlying the frame structure and the one or more electrical components. The shielding structure contacts a first surface of the frame structure, at least a portion of the molding compound resides between the shielding structure and the one or more electrical components, and the first surface of the frame structure is aligned with a second surface of the portion of the molding compound.
    Type: Application
    Filed: October 17, 2013
    Publication date: April 23, 2015
    Inventors: EDUARD J. PABST, ZHIWEI GONG