And Encapsulating Patents (Class 438/124)
  • Patent number: 10629565
    Abstract: A semiconductor device has a carrier with an adhesive layer formed over the carrier. Alignment marks are provided for picking and placing the electrical component on the carrier or adhesive layer. An electrical component is disposed on the adhesive layer by pressing terminals of the electrical component into the adhesive layer. The electrical component can be a semiconductor die, discrete component, electronic module, and semiconductor package. A leadframe is disposed over the adhesive layer. A shielding layer is formed over the electrical component. An encapsulant is deposited over the electrical component. The carrier and adhesive layer are removed so that the terminals of the electrical component extend out from the encapsulant for electrical interconnect. A substrate includes a plurality of conductive traces. The semiconductor device is disposed on the substrate with the terminals of the electrical component in contact with the conductive traces.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: April 21, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: JinHee Jung, OhHan Kim, InSang Yoon
  • Patent number: 10598874
    Abstract: A technique for fabricating bumps on a substrate is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared. A bump base is formed on each pad of the substrate. Each bump base has a tip extending outwardly from the corresponding pad. A resist layer is patterned on the substrate to have a set of holes through the resist layer. Each hole is aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad. The set of the holes in the resist layer is filled with conductive material to form a set of bumps on the substrate. The resist layer is stripped from the substrate with leaving the set of the bumps.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: March 24, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji Nakamura, Masao Tokunari
  • Patent number: 10600690
    Abstract: A method for handling a product substrate includes bonding a carrier to the product substrate by: applying a layer of a temporary adhesive having a first coefficient of thermal expansion onto a surface of the carrier; and bonding the carrier to the product substrate using the applied temporary adhesive. A surface of the temporary adhesive is in direct contact to a surface of the product substrate. The temporary adhesive includes or is adjacent a filler material having a second coefficient of thermal expansion which is smaller than the first coefficient of thermal expansion, so that stress occurs inside the temporary adhesive layer or at an interface to the product substrate or the carrier during cooling down of the temporary adhesive layer.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: March 24, 2020
    Assignee: Infineon Technologies AG
    Inventors: Georg Meyer-Berg, Claus von Waechter, Michael Bauer, Holger Doepke, Dominic Maier, Daniel Porwol, Tobias Schmidt
  • Patent number: 10418341
    Abstract: A semiconductor device has a carrier with an adhesive layer formed over the carrier. Alignment marks are provided for picking and placing the electrical component on the carrier or adhesive layer. An electrical component is disposed on the adhesive layer by pressing terminals of the electrical component into the adhesive layer. The electrical component can be a semiconductor die, discrete component, electronic module, and semiconductor package. A leadframe is disposed over the adhesive layer. A shielding layer is formed over the electrical component. An encapsulant is deposited over the electrical component. The carrier and adhesive layer are removed so that the terminals of the electrical component extend out from the encapsulant for electrical interconnect. A substrate includes a plurality of conductive traces. The semiconductor device is disposed on the substrate with the terminals of the electrical component in contact with the conductive traces.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: September 17, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: JinHee Jung, OhHan Kim, InSang Yoon
  • Patent number: 10373886
    Abstract: A preformed lead frame includes a metallic substrate, a plurality of spaced-apart conductive lead frame units and intersecting trenches, a molding layer, and a plurality of conductive pads. The lead frame units and the molding layer are formed on the substrate. Each of the lead frame units includes a die supporting portion, a plurality of lead portions surrounding and spaced apart from the die supporting portion, and a gap formed among the die supporting portion and the lead portions. The trenches are formed among the conductive lead frame units. The molding layer fills the gaps and the trenches. Each of the conductive pads is formed on a top surface of the die supporting portion of a respective one of the lead frame units.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: August 6, 2019
    Assignee: Chang Wah Technology Co., Ltd.
    Inventor: Chia-Neng Huang
  • Patent number: 10332816
    Abstract: Provided is a circuit device in which encapsulating resin to encapsulate a circuit board is optimized in shape, and a method of manufacturing the circuit device. A hybrid integrated circuit device, which is a circuit device according to the present invention includes a circuit board, a circuit element mounted on a top surface of the circuit board, and encapsulating resin encapsulating the circuit element, and coating the top surface, side surfaces, and a bottom surface of the circuit board. In addition, the encapsulating resin is partly recessed and thereby provided with recessed areas at two sides of the circuit board. The providing of the recessed areas reduces the amount of resin to be used, and prevents the hybrid integrated circuit device from being deformed by the cure shrinkage of the encapsulating resin.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: June 25, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Hideyuki Sakamoto
  • Patent number: 10325826
    Abstract: A substrate having a die attach area for receiving a semiconductor die includes a recessed area for receiving die attach adhesive. The recessed area prevents die attach adhesive from bleeding into the surrounding area and onto substrate connection sites, where it could compromise a wire bond formed on such a connection site. The recessed area has a zig-zag pattern, which allows for sufficient amounts of adhesive to be used to securely attach the die to the substrate, yet does not enlarge the recessed area such that the package size may be adversely affected.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: June 18, 2019
    Assignee: NXP USA, INC.
    Inventors: Ly Hoon Khoo, Chin Teck Siong, Vanessa Wyn Jean Tan
  • Patent number: 10128192
    Abstract: A semiconductor package structure including a redistribution layer (RDL) structure having a first surface and a second surface opposite thereto is provided. The RDL structure includes an inter-metal dielectric (IMD) layer and a first conductive layer disposed at a first layer-level of the IMD layer. A molding compound covers the first surface of the RDL structure. A first semiconductor die is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. A plurality of bump structures is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: November 13, 2018
    Assignee: MEDIATEK INC.
    Inventors: Min-Chen Lin, Che-Ya Chou, Nan-Cheng Chen
  • Patent number: 10085344
    Abstract: An electronic component includes an inner electrode inside of a main body and exposed at a surface of the main body, and an outer electrode on a surface of the main body and electrically connected to the inner electrode, wherein a plurality of recesses are provided in a surface of the outer electrode, and each of the plurality of recesses includes a portion in which a diameter of an opening of the recess gradually decreases toward an opening side of the recess.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: September 25, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masaki Hirota, Yoshikazu Sasaoka, Yasunori Taseda, Shinichiro Kuroiwa
  • Patent number: 10079190
    Abstract: A method of fabricating a package structure is provided, including forming a plurality of openings by removing a portion of the material on one side of a conductive layer, forming an insulating material as an insulating layer in the openings, removing a portion of the material on the other side of the conductive layer to serve as a wiring layer, disposing an electronic component on the wiring layer, and forming an encapsulating layer to cover the electronic component, thereby allowing the single wiring layer to be connected to the electronic component on one side and connected to solder balls on the other side thereof to shorten the signal transmission path. The present invention further provides a package structure thus fabricated.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: September 18, 2018
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD
    Inventors: Shih-Ping Hsu, Chin-Wen Liu, Tang-I Wu, Shu-Wei Hu
  • Patent number: 9870964
    Abstract: The present disclosure provides a technique including a method of manufacturing a semiconductor device, which is capable of improving a processing uniformity of a plurality of substrates. The method may include: (a) subjecting a substrate accommodated in one of a plurality of process chambers to a thermal process: (b) transferring the substrate processed in (a) by a transfer robot provided in a vacuum transfer chamber connected to the plurality of process chambers from the one of a plurality of process chambers to a loadlock chamber connected to the vacuum transfer chamber; and (c) cooling the substrate accommodated in the loadlock chamber by supplying an inert gas to the substrate accommodated in the loadlock chamber according to a cooling recipe.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: January 16, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC, INC.
    Inventors: Teruo Yoshino, Takeshi Yasui
  • Patent number: 9698116
    Abstract: A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer having a thickness of at least four (4) micrometers disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: July 4, 2017
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla
  • Patent number: 9554471
    Abstract: A packaging structure including: a cover secured to a first substrate and forming first and second distinct cavities between the cover and the first substrate, first and second channels formed in the first substrate and/or in the cover and/or between the first substrate and the cover, the first channel including a first end leading into the first cavity and a second end leading off the first cavity via a first hole passing through the cover, the second channel including a first end leading into the second cavity and a second end leading off the second cavity via a second hole passing through the cover, a height HA of the first channel at its second end is lower than a height HB of the second channel at its second end.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: January 24, 2017
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventor: Xavier Baillin
  • Patent number: 9530818
    Abstract: An image sensor die may include a pixel array formed in an image sensor substrate. The image sensor die may be mounted to a thin metal interconnect layer that has been deposited on a sacrificial carrier substrate. The thin metal interconnect layer may include one or more metal layers that are patterned to form metal traces that serve as contact pads, signal lines, and other interconnects in the interconnect layer. The image sensor die may be wire bonded, flip-chip mounted, or otherwise mechanically and electrically coupled to the metal interconnect layer. The sacrificial carrier substrate may be etched or otherwise removed to expose the metal interconnects on the metal interconnect layer. An array of solder balls may be formed on the exposed metal interconnects to form a ball grid array package, or the exposed contact pads may be plated to form a leadless chip carrier package.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: December 27, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Jonathan Michael Stern
  • Patent number: 9449907
    Abstract: Various methods and apparatus for joining stacked substrates to a circuit board are disclosed. In one aspect, a method of manufacturing is provided that includes coupling plural substrates to form a stack. At least one of the plural substrates is a semiconductor chip. Plural conductive vias are formed in a first of the plural substrates. Each of the plural conductive vias includes a first end positioned in the first substrate and a second end projecting out of the first substrate.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: September 20, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lei Fu, Frank Gottfried Kuechenmeister, Michael Zhuoying Su
  • Patent number: 9443791
    Abstract: A method of forming semiconductor devices on a leadframe structure. The leadframe structure comprising an array of leadframe sub-structures each having a semiconductor die arranged thereon. The method comprises; providing electrical connections between terminals of said lead frame sub-structures and said leadframe structure; encapsulating said leadframe structure, said electrical connections and said terminals in an encapsulation layer; performing a first series of parallel cuts extending through the leadframe structure and the encapsulation layer to expose a side portion of said terminals; electro-plating said terminals to form metal side pads; and performing a second series of parallel cuts angled with respect to the first series of parallel cuts, the second series of cuts extending through the lead frame structure and the encapsulation layer to singulate a semiconductor device from the leadframe structure.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: September 13, 2016
    Assignee: NXP B.V.
    Inventors: Chi Ho Leung, Ke Xue, Soenke Habenicht, Wai Hung William Hor, San Ming Chan, Wai Keung Ng
  • Patent number: 9362222
    Abstract: Embodiments of mechanisms for forming a semiconductor device structure are provided. The semiconductor device structure includes a metal-insulator-metal (MIM) capacitor formed on a substrate. The semiconductor device structure also includes an inductor formed on the MIM capacitor. The semiconductor device structure further includes a via formed between the MIM capacitor and the inductor, and the via is formed in a plurality of dielectric layers, and the dielectric layers comprise an etch stop layer.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: June 7, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hung Hsueh, Yen-Hsiang Hsu, Kuan-Chi Tsai
  • Patent number: 9257380
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: February 9, 2016
    Assignee: Intel Corporation
    Inventors: Ravi K. Nalla, John S. Guzek, Javier Soto Gonzalez, Drew W. Delaney, Hamid R. Azimi
  • Patent number: 9219019
    Abstract: A semiconductor device has a leadframe with a pad and a row of elongated leads with a solderable surfaces in a common plane; a package encapsulating the leadframe with an assembled semiconductor device, leaving the common-plane lead surfaces un-encapsulated and coplanar with the package material between adjacent leads, the row of aligned leads positioned along a package edge; and grooves in the package material cut in the common-plane surface, the grooves extend along a portion of each lead length, have a width and a depth about twice the width, and expose solderable lead surfaces.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: December 22, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Alok Kumar Lohia, Reynaldo Corpuz Javier, Andy Quang Tran
  • Patent number: 9129948
    Abstract: A semiconductor device has a die support and external leads formed integrally from a single sheet of electrically conductive material. A die mounting substrate is mounted on the die support, with bonding pads coupled to respective external connection pads on an external connector side of the substrate. A die is attached to the die mounting substrate with die connection pads. Bond wires selectively electrically couple the die connection pads to the external leads and the bonding pads and electrically conductive external protrusions are mounted to the external connection pads. An encapsulant covers the die and bond wires. The external protrusions are located at a central region of a surface mounting side of the package and the external leads project outwardly from locations near the die support towards peripheral edges of the package.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: September 8, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Meiquan Huang, Huan Wang, Jinsheng Wang, Naikou Zhou
  • Patent number: 9064873
    Abstract: A singulated semiconductor structure comprises a molding compound; a first conductive post in the molding compound having a first geometric shape in a top view; a second conductive post or an alignment mark in the molding compound having a second geometric shape in a top view, wherein the second geometric shape is different from the first geometric shape. The second conductive post or an alignment mark can be positioned at the corner, the center, the edge, or the periphery of the singulated semiconductor structure. The second geometric shape can be any geometric construct distinguishable from the first geometric shape. The second conductive post or an alignment mark can be placed at an active area or a non-active area of the singulated semiconductor structure.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: June 23, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chia-Chun Miao, Shih-Wei Liang, Kai-Chiang Wu, Ming-Kai Liu, Yen-Ping Wang
  • Patent number: 9054115
    Abstract: According to one exemplary embodiment, an overmolded package includes a component situated on a substrate. The overmolded package further includes an overmold situated over the component and the substrate. The overmolded package further includes a wirebond cage situated over the substrate and in the overmold, where the wirebond cage surrounds the component, and where the wirebond cage includes a number of wirebonds. The wirebond cage forms an EMI shield around the component. According to this exemplary embodiment, the overmolded package further includes a conductive layer situated on a top surface of the overmold and connected to the wirebond cage, where the conductive layer forms an EMI shield over the component.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: June 9, 2015
    Assignee: Skyworks Solutions, Inc.
    Inventors: Dinhphuoc V. Hoang, Thomas E. Noll, Anil K. Agarwal, Robert W. Warren, Matthew S. Read, Anthony LoBianco
  • Patent number: 9048199
    Abstract: A semiconductor package and a method of manufacturing the semiconductor package are disclosed. A semiconductor package in accordance with an embodiment of the present invention includes a substrate, which has a ground circuit formed thereon, a semiconductor chip, which is mounted on the substrate, a conductive first shield, which is formed on an upper surface of the semiconductor chip and connected with the ground circuit, and a conductive second shield, which covers the substrate and the semiconductor chip and is connected with the first shield. With a semiconductor package in accordance with an embodiment of the present invention, grounding is possible between semiconductor chips because a shield is also formed on an upper surface of the semiconductor chip, and the shielding property can be improved by a double shielding structure.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: June 2, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Do-Jae Yoo, Jae-Cheon Doh
  • Publication number: 20150145126
    Abstract: A semiconductor device has a stress relief buffer mounted to a temporary substrate in locations designated for bump formation. The stress relief buffer can be a multi-layer composite material such as a first compliant layer, a silicon layer formed over the first compliant layer, and a second compliant layer formed over the silicon layer. A semiconductor die is also mounted to the temporary substrate. The stress relief buffer can be thinner than the semiconductor die. An encapsulant is deposited between the semiconductor die and stress relief buffer. The temporary substrate is removed. An interconnect structure is formed over the semiconductor die, encapsulant, and stress relief buffer. The interconnect structure is electrically connected to the semiconductor die. A stiffener layer can be formed over the stress relief buffer and encapsulant. A circuit layer containing active devices, passive devices, conductive layers, and dielectric layers can be formed within the stress relief buffer.
    Type: Application
    Filed: December 9, 2014
    Publication date: May 28, 2015
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Yaojian Lin, II Kwon Shim, Seng Guan Chow
  • Patent number: 9040359
    Abstract: A method for fabricating a molded interposer package includes performing a first anisotropic etching process to remove a portion of the metal sheet from a top surface of the metal sheet, thereby forming a plurality of first recesses in the metal sheet, forming a molding material covering the top surface, filling the first recesses, forming a plurality of first via openings in the molding material, wherein the first via openings expose the top surface, forming a plurality of first metal vias in the first via openings and a plurality of first redistribution layer patterns respectively on the first metal vias, performing a second anisotropic etching process to remove a portion of the metal sheet from a bottom surface of the metal sheet until a bottom of the molding material is exposed, and forming a solder mask layer on the molding material, leaving the first redistribution layer patterns exposed.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: May 26, 2015
    Assignee: MEDIATEK INC.
    Inventors: Thomas Matthew Gregorich, Andrew C. Chang, Tzu-Hung Lin
  • Patent number: 9040357
    Abstract: A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: May 26, 2015
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Jun Lu, Kai Liu, Yan Xun Xue
  • Patent number: 9040353
    Abstract: A method for manufacturing a semiconductor light emitting device comprises a sealing step of sealing a semiconductor chip fixed on a lead frame with a sealing member, a removal step of removing the sealing member until a surface of the semiconductor chip becomes exposed, an irregularity formation step of forming fine irregularities on a bond surface formed in the removal step, and a bonding step of bonding a wavelength conversion member to the bond surface.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: May 26, 2015
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Takayoshi Yajima, Hiroshi Ito
  • Publication number: 20150137351
    Abstract: A semiconductor device includes a die, a conductive post disposed adjacent to the die, and a molding surrounding the conductive post and the die, the molding includes a protruded portion protruded from a sidewall of the conductive post and disposed on a top surface of the conductive post. Further, a method of manufacturing a semiconductor device includes disposing a die, disposing a conductive post adjacent to the die, disposing a molding over the conductive post and the die, removing some portions of the molding from a top of the molding, and forming a recess of the molding above a top surface of the conductive post.
    Type: Application
    Filed: November 18, 2013
    Publication date: May 21, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: LI-HUI CHENG, PO-HAO TSAI, JUI-PIN HUNG
  • Patent number: 9034693
    Abstract: A method of manufacturing an integrated circuit package includes: forming a substrate including: forming a core layer, and forming vias in the core layer; forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: May 19, 2015
    Assignee: ST ASSEMBLY TEST SERVICES LTD.
    Inventors: Il Kwon Shim, Kwee Lan Tan, Jian Jun Li, Dario S. Filoteo, Jr.
  • Patent number: 9029194
    Abstract: A method of making an integrated circuit module starts with a top leadframe strip comprising a plurality of integrally connected top leadframes. A plurality of flipchip dies are mounted on the top leadframe strip with solder bumps of each flipchip bonded to predetermined pad portions on each of the top leadframes. The top leadframe strip is attached to a bottom leadframe strip. The bottom leadframe strip has a plurality of integrally connected bottom leadframes each having a central die attach pad (DAP) portion and a peripheral frame portion. A back face of each flipchip die contacts the DAP portion of each bottom leadframe. Lead portions of each top leadframe are attached to the peripheral frame portion of each bottom leadframe. The top leadframe strip is attached to the bottom leadframe strip with a back face of each flipchip die contacting the DAP portion of each bottom leadframe and with lead portions of each top leadframe attached to the peripheral frame portion of each bottom leadframe.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: May 12, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Lee Han Meng@Eugene Lee, Anis Fauzi bin Abdul Aziz, Susan Goh Geok Ling, Ng Swee Tiang
  • Patent number: 9029203
    Abstract: This disclosure provides a semiconductor package and a method of fabricating the same. The semiconductor package includes an insulating layer; a plurality of traces and connection pads disposed in the insulating layer and protruded from the insulating layer; a plurality of bumps formed on the plurality of traces; a semiconductor chip disposed on the bumps; and an encapsulant formed on the insulating layer to encapsulate the semiconductor chip, the plurality of bumps, traces and connection pads. When the encapsulant is formed, voids can be prevented from being generated in the traces and the connection pads and thus the yield of process is significantly increased.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: May 12, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Pang-Chun Lin, Yueh-Ying Tsai, Yong-Liang Chen
  • Patent number: 9027238
    Abstract: A multilayered printed circuit board or a substrate for mounting a semiconductor device includes a semiconductor device, a first resin insulating layer accommodating the semiconductor device, a second resin insulating layer provided on the first resin insulating layer, a conductor circuit provided on the second resin insulating layer, and via holes for electrically connecting the semiconductor device to the conductor circuit, wherein the semiconductor device is accommodated in a recess provided in the first resin insulating layer, and a metal layer for placing the semiconductor device is provided on the bottom face of the recess. A multilayered printed circuit board in which the installed semiconductor device establishes electrical connection through the via holes is provided.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: May 12, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Sotaro Ito, Michimasa Takahashi, Yukinobu Mikado
  • Patent number: 9029202
    Abstract: A semiconductor device package (100) includes a heat spreader (503) formed by depositing a first thin film layer (301) of a first metal on a top surface (150) of a die (110) and to exposed portions of a top surface of an encapsulant (208), depositing a second thin film layer (402) of a second metal on a top surface of the first thin film layer, and depositing a third layer (503) of a third metal on a top surface of the second thin film layer.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: May 12, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Weng Foong Yap, Jinbang Tang
  • Patent number: 9024427
    Abstract: A three dimensional package includes a substrate having a columnar part including a sidewall, and stairs or steps arranged along the sidewall of the columnar part in the form of multiple helixes twisted around the columnar part. Semiconductor integrated circuits (IC dies) are attached on one or both of the supporting surfaces of the stairs. The columnar part, the stairs and the IC dies can be encapsulated with a mold compound.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: May 5, 2015
    Assignee: Freescale Semiconductor. Inc
    Inventors: Huan Wang, Aipeng Shu, Shu An Yao
  • Publication number: 20150108621
    Abstract: Shielded device packages and related fabrication methods are provided. An exemplary device package includes one or more electrical components, a molding compound overlying the one or more electrical components, a frame structure circumscribing the one or more electrical components, and a shielding structure overlying the frame structure and the one or more electrical components. The shielding structure contacts a first surface of the frame structure, at least a portion of the molding compound resides between the shielding structure and the one or more electrical components, and the first surface of the frame structure is aligned with a second surface of the portion of the molding compound.
    Type: Application
    Filed: October 17, 2013
    Publication date: April 23, 2015
    Inventors: EDUARD J. PABST, ZHIWEI GONG
  • Patent number: 9013035
    Abstract: Methods and apparatuses for improved integrated circuit (IC) packages are described herein. In an aspect, an IC device package includes an IC die having a contact pad, where the contact pad is located on a hotspot of the IC die. The hotspot is thermally coupled to a thermal interconnect member. In an aspect, the package is encapsulated in a mold compound. In a further aspect, a heat spreader is attached to the mold compound, and is thermally coupled to the thermal interconnect member. In another aspect, a thermal interconnect member thermally is coupled between the heat spreader and the substrate.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: April 21, 2015
    Assignee: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Rezaur Rahman Khan
  • Patent number: 9012268
    Abstract: Embodiments of the present disclosure are directed to leadframe strips and methods of forming packages that include first separating adjacent leads of a leadframe strip and subsequently singulating components into individual packages. In one embodiment, the adjacent leads are separated by etching through the leads, thereby providing electrical isolation of the adjacent packages. In that regard, if desired, the individual adjacent packages may be electrically tested in leadframe strip form. Subsequently, the individual packages are formed by sawing through the encapsulation material.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics, Inc.
    Inventors: Jonathan Jaurigue, Rogelio Real, Francis Ann Llana, Ricky Calustre, Rodolfo Gacusan
  • Patent number: 9012269
    Abstract: Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics PTE Ltd.
    Inventors: Yonggang Jin, Xavier Baraton, Faxing Che
  • Patent number: 9012267
    Abstract: Embodiments of the subject application provide for a circuit comprising: a lead frame having a first plurality of exposed terminals, the lead frame defining a plane; a laminate substrate in the plane defined by the lead frame, adjacent to the lead frame, and electrically coupled to the lead frame, the laminate substrate having a first surface including a second plurality of exposed terminals and a second surface opposite the first surface; a first one or more dies mounted on the lead frame and electrically coupled to the lead frame; and a second one or more dies mounted on the second surface of the laminate substrate and electrically coupled to the laminate substrate.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: April 21, 2015
    Assignee: Intersil Americas LLC
    Inventors: Jian Yin, Nikhil Vishwanath Kelkar, Loyde Milton Carpenter, Jr.
  • Patent number: 9006039
    Abstract: A fabrication method of a packaging substrate includes: providing a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; forming a first encapsulant in the first openings; forming a second encapsulant in the second openings; and forming a surface circuit layer on the first encapsulant and the first core circuit layer.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: April 14, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chi-Ching Ho, Yu-Chih Yu, Ying-Chou Tsai
  • Patent number: 9000544
    Abstract: A MEMS package structure, including a substrate, an interconnecting structure, an upper metallic layer, a deposition element and a packaging element is provided. The interconnecting structure is disposed on the substrate. The MEMS structure is disposed on the substrate and within a first cavity. The upper metallic layer is disposed above the MEMS structure and the interconnecting structure, so as to form a second cavity located between the upper metallic layer and the interconnecting structure and communicates with the first cavity. The upper metallic layer has at least a first opening located above the interconnecting structure and at least a second opening located above the MEMS structure. Area of the first opening is greater than that of the second opening. The deposition element is disposed above the upper metallic layer to seal the second opening. The packaging element is disposed above the upper metallic layer to seal the first opening.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: April 7, 2015
    Assignee: Pixart Imaging Inc.
    Inventors: Hsin-Hui Hsu, Sheng-Ta Lee, Chuan-Wei Wang
  • Patent number: 8999763
    Abstract: Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having an interposer including at least one topological feature, such as a depression in a surface of the interposer, a die coupled to the surface of the interposer, and an encapsulant material formed over the die and the interposer, and disposed in the at least one depression to resist movement of the encapsulant material relative to the interposer. Other embodiments may be described and claimed.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: April 7, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Steven Eskildsen, Aravind Ramamoorthy
  • Patent number: 8999762
    Abstract: A process for encapsulating a micro-device in a cavity formed between a first and a second substrate is provided, including producing the micro-device in or on the first substrate; attaching and securing the second substrate to the first substrate, thereby forming the cavity in which the micro-device is placed; producing at least one hole through one of the two substrates, leading into the cavity opposite a portion of the other of the two substrates; depositing at least one getter material portion through the hole on said portion of the other of the two substrates; and hermetically sealing the cavity by closing the hole.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: April 7, 2015
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Xavier Baillin, Jean-Louis Pornin
  • Patent number: 8994155
    Abstract: Packaging devices, methods of manufacture thereof, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging device includes a substrate including an integrated circuit die mounting region. An underfill material flow prevention feature is disposed around the integrated circuit die mounting region.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Yu-Chang Lin, Ying Ching Shih, Wei-Min Wu, Yian-Liang Kuo, Chia-Wei Tu
  • Patent number: 8994156
    Abstract: Electronic devices including a semiconductor device package, a substrate, and first and second solder joints. The semiconductor device package includes a die pad, leads and enhancement elements surrounding the die pad, a chip electrically connected to the leads, and a package body encapsulating the chip, portions of the leads, and portions of the enhancement elements, but leaving exposed at least a side surface of each enhancement element. Side surfaces of the enhancement elements and the package body are coplanar. The substrate includes first pads corresponding to the leads and second pads corresponding to the enhancement elements. The first solder joints are disposed between the first pads and the leads. The second solder joints are disposed between the second pads and the enhancement elements. The second solder joints contact side surfaces of the enhancement elements. The surface area of the second pads is greater than the surface area of the corresponding enhancement elements.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: March 31, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Po-Shing Chiang, Ping-Cheng Hu, Yu-Fang Tsai
  • Patent number: 8987063
    Abstract: A manufacturing method of a semiconductor device of a thin resin sealed multichip rectangular package having wire connection between the chips, wherein: at least one chip is fixed to a die pad thinned more than a die pad support lead, the die pad is supported by die pad support leads arranged to respectively connect a pair of long sides of the rectangle, and sealing resin is introduced from one side of the pair of long sides when resin molding is performed.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: March 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Ryoji Harata, Hiroaki Narita
  • Patent number: 8987064
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead-frame having a metal connector mounted thereon and having a peripheral mounting region; forming an insulation cover on the lead-frame and on the metal connector; connecting an integrated circuit die over the insulation cover; forming a top encapsulation on the integrated circuit die with the peripheral mounting region exposed from the top encapsulation; forming a routing layer, having a conductive land, from the lead-frame; and forming a bottom encapsulation partially encapsulating the routing layer and the insulation cover.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: March 24, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8980693
    Abstract: A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon. The first package further includes first and second microelectronic elements, each having element contacts electrically connected with the substrate contacts and being spaced apart from one another on the first surface so as to provide an interconnect area of the first surface between the first and second microelectronic elements. A plurality of package terminals at the second surface are electrically interconnected with the substrate contacts for connecting the package with a component external thereto. A plurality of stack terminals are exposed at the first surface in the interconnect area for connecting the package with a component overlying the first surface of the substrate.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: March 17, 2015
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Kyong-Mo Bang
  • Patent number: 8980694
    Abstract: Disclosed are a flip-chip carrier having individual pad masks (IPMs) and a fabricating method of a MPS-C2 package utilized from the same. The flip-chip carrier primarily comprises a substrate and a plurality of the IPMs. The substrate has a top surface and a plurality of connecting pads on the top surface. The IPMs cover the corresponding connecting pads in one-on-one alignment where each IPM consists of a photo-sensitive adhesive layer on the corresponding connecting pad and a pick-and-place body pervious to light formed on the photo-sensitive adhesive layer. After the photo-sensitive adhesive layers are irradiated by light penetrating through the pick-and-place bodies, the pick-and-place bodies can be pulled out by a pick-and-place process to expose the connecting pads from an encapsulant. The issues of solder bridging and package warpage can easily be solved in conventional MPS-C2 packages.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: March 17, 2015
    Assignee: Powertech Technology, Inc.
    Inventor: Shou-Chian Hsu
  • Publication number: 20150069605
    Abstract: A semiconductor device is disclosed, which includes: a substrate having a plurality of connecting pads; a semiconductor component having a plurality of bonding pads formed on a surface thereof and corresponding to the connecting pads and a UBM layer formed on the bonding pads; a plurality of conductive elements each having a first conductive portion and a second conductive portion sequentially formed on the UBM layer, wherein the second conductive portion is less in width than the first conductive portion; and a plurality of solder balls formed between the second conductive portions and the connecting pads for connecting the semiconductor component and the substrate, thereby preventing solder bridging from occurring between the adjacent conductive elements and reducing stresses between the conductive elements and the UBM layer.
    Type: Application
    Filed: May 8, 2014
    Publication date: March 12, 2015
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chang-Fu Lin, Chin-Tsai Yao, Hung-Ming Chang, Ming-Chin Chuang, Fu-Tang Huang