Insulative Housing Or Support Patents (Class 438/125)
  • Patent number: 10388685
    Abstract: The present invention provides a portable electronic device and an image-capturing module thereof, and an image-sensing assembly thereof. The image-sensing assembly includes an image-sensing chip, a spacer structure, and a filter element. The image-sensing chip has an image sensing area and a non-image sensing area surrounding the image sensing area. The spacer structure is disposed on the non-image sensing area. The filter element is disposed on the spacer structure so as to separate the filter element from the image-sensing chip by a predetermined distance. The image-sensing assembly can be applied to the image-capturing module, and the image-capturing module can be applied to the portable electronic device.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: August 20, 2019
    Assignee: AZUREWAVE TECHNOLOGIES, INC.
    Inventors: Tseng-Chieh Lee, Kung-An Lin
  • Patent number: 10271433
    Abstract: A method of packaging an electrical device including following steps is provided. A circuit board including a substrate and a first conductive pattern is provided. The electrical device having an electrode is disposed on the circuit board. A dielectric layer is formed on the circuit board to cover the electrical device, the electrode and the first conductive pattern, wherein a first caving pattern is formed in the dielectric layer by the first conductive pattern. The dielectric layer is patterned to form a through hole and a second caving pattern connecting with the through hole and exposing the electrode. A conductive material is filled in the through hole and the second caving pattern to form a conductive via in the through hole and a second conductive pattern in the second caving pattern. The substrate is removed.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: April 23, 2019
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Shu-Sheng Chiang, Tsung-Yuan Chen, Shih-Lian Cheng
  • Patent number: 10199303
    Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a molded package body having an upper peripheral edge portion, an air cavity around which the upper peripheral edge portion extends, and a cover piece bonded to the upper peripheral edge portion to enclose the air cavity. The cover piece has a lower peripheral edge portion, which cooperates with the upper peripheral edge portion to define a cover-body interface. The cover-body interface includes an annular channel extending around the cover-body interface, as taken about the package centerline, and first and second hardstop features formed on the upper peripheral edge portion of the molded package body and on the lower peripheral edge portion of the cover piece, respectively. The hardstop features contact to determine a vertical height of the annular channel, as taken along the package centerline.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: February 5, 2019
    Assignee: NXP USA, INC.
    Inventors: Audel Sanchez, Lakshminarayan Viswanathan, Fernando A. Santos, Jaynal A. Molla
  • Patent number: 10192979
    Abstract: A device having: a substrate having a dielectric surface; a gate electrode; a drain electrode; a source electrode having a conductive contact and a two-dimensional material edge; and a dielectric material between the source and the gate. The source is adjacent to the gate. The drain electrode is not laterally between the edge and the gate electrode, and the distance from the drain electrode to the edge is greater than the distance from the gate electrode to the edge. The edge does not contact any other component of the device. The gate, drain, and source are not in electrical contact with each other. There is a line of sight or electron path from the edge to the drain electrode.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: January 29, 2019
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Jonathan L. Shaw, John Bradley Boos, Kevin Jensen, James G. Champlain, Bradford B. Pate, Byoung-don Kong, Doewon Park, Joan E. Yater
  • Patent number: 10181457
    Abstract: Apparatuses and methods relating generally to a microelectronic package for wafer-level chip scale packaging with fan-out are disclosed. In an apparatus, there is a substrate having an upper surface and a lower surface opposite the upper surface. A microelectronic device is coupled to the upper surface with the microelectronic device in a face-up orientation. Wire bond wires are coupled to and extending away from the upper surface. Posts of the microelectronic device extend away from a front face thereof. Conductive pads are formed in the substrate associated with the wire bond wires for electrical conductivity.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: January 15, 2019
    Assignee: Invensas Corporation
    Inventors: Ashok S. Prabhu, Rajesh Katkar
  • Patent number: 10177084
    Abstract: An object of the invention is to manufacture a semiconductor module small. A metal wire (212) connecting a control electrode (101) and a control terminal (21) rises to form a first angle (?1) from the control electrode (101) toward a first conductive portion (202), gradually goes in substantially parallel to the first conductive portion (202) as the metal wire approaches the first conductive portion (202), and is connected to the control terminal (21) to form a second angle (?2) smaller than the first angle (?1).
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: January 8, 2019
    Assignee: HITACHI, LTD.
    Inventors: Nobutake Tsuyuno, Eiichi Ide
  • Patent number: 10147746
    Abstract: A flexible display device includes a flexible substrate, an adhesion layer disposed on a surface of the flexible substrate, and a plurality of pixel structures in respective pixels on the adhesion layer. Each of the pixel structures on the adhesion layer includes a light emitting diode including an inorganic light emitting layer, and a thin film transistor which is connected to the light emitting diode and switches a state of the light emitting diode.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: December 4, 2018
    Assignees: SAMSUNG DISPLAY CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Kihyun Kim, Taewoong Kim, Jong-hyun Ahn, Wonho Lee, Minwoo Choi
  • Patent number: 10081534
    Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity. The method for forming the cavity further includes forming at least one first vent hole of a first dimension which is sized to avoid or minimize material deposition on a beam structure during sealing processes. The method for forming the cavity further includes forming at least one second vent hole of a second dimension, larger than the first dimension.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: September 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey C. Maling, Anthony K. Stamper, Dana R. DeReus, Arthur S. Morris, III
  • Patent number: 10001418
    Abstract: Embodiments generally relate to device and methods for detecting force. A force sensor may include a sense die, a substrate, one or more sense elements supported by the sense die, one or more electrical contacts located on the sense die and electrically coupled to electrical traces on the substrate, and an actuation element configured to transmit a force to the sense die. The width of the actuation element may be less than the distance between the one or more electrical contacts. In some embodiments, the actuation element may include a thin wedge/plate configured to interact with the sense die at a contact point. The thin wedge/plate may allow use of a smaller sense die and/or may allow closer placement of the one or more sense elements to the contact point and/or may prevent accidental contact with the one or more electrical contacts which may lead to a short circuit.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: June 19, 2018
    Assignee: Honeywell International Inc.
    Inventors: James F. Machir, Jason Dennis Patch
  • Patent number: 9960192
    Abstract: A flexible display device includes a flexible substrate, an adhesion layer disposed on a surface of the flexible substrate, and a plurality of pixel structures in respective pixels on the adhesion layer. Each of the pixel structures on the adhesion layer includes a light emitting diode including an inorganic light emitting layer, and a thin film transistor which is connected to the light emitting diode and switches a state of the light emitting diode.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: May 1, 2018
    Assignees: SAMSUNG DISPLAY CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Kihyun Kim, Taewoong Kim, Jong-hyun Ahn, Wonho Lee, Minwoo Choi
  • Patent number: 9832878
    Abstract: A wiring board with a cavity for a built-in electronic component includes a conductor layer including a conductor circuit layer and a plane layer, and an insulating layer laminated on the conductor layer and having a cavity such that the cavity is forming an exposed portion of the plane layer and formed to mount a built-in electronic component on the exposed portion of the plane layer. The plane layer has a recess structure formed in an outer peripheral portion in the exposed portion of the plane layer.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: November 28, 2017
    Assignee: IBIDEN CO., LTD.
    Inventors: Keisuke Shimizu, Makoto Terui, Ryojiro Tominaga, Yuichi Nakamura
  • Patent number: 9781833
    Abstract: This invention relates to a method for producing an electrical system comprising a support (1) bearing on a first face at least one device; with the device comprising at least one electronic component (2) provided with at least one electrical connector (21, 22), with the method comprising: a step of setting in place of a cover (6) positioned above the component; said cover (6) comprising at least one passage (61, 62) according to a dimension in thickness of the cover (6) in such a way as to form an access space to the at least one electrical connector (21, 22), a step of forming a sealing seam (71) in such a way that the component is encapsulated in a sealed cavity (9) delimited by the first face of the support (1), the first face of the cover (6) and the sealing seam (7).
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: October 3, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Messaoud Bedjaoui, Raphael Salot
  • Patent number: 9773719
    Abstract: In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor chip having a first side and an opposite second side, and a chip contact pad disposed on the first side of the semiconductor chip. A dielectric liner is disposed over the semiconductor chip. The dielectric liner includes a plurality of openings over the chip contact pad. A interconnect contacts the semiconductor chip through the plurality of openings at the chip contact pad.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: September 26, 2017
    Assignee: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventors: Dirk Meinhold, Frank Daeche, Thorsten Scharf
  • Patent number: 9699885
    Abstract: Disclosed herein is a circuit board. According to an exemplary embodiment of the present disclosure, a circuit board has a structure in which at least a portion of a first heat transfer structure in which a metal layer and an insulating layer are alternately stacked is inserted into an insulating part.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: July 4, 2017
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Tae Hong Min, Myung Sam Kang, Young Gwan Ko, Min Jae Seong
  • Patent number: 9688532
    Abstract: A method of manufacturing an electronic device in which a second substrate (functional element) containing silicon and a third substrate (lid body) containing silicon are bonded to a first substrate containing alkali metal ions by anode bonding includes a first process of performing the anode bonding to bond the second substrate to a surface of the first substrate; a second process of removing at least a portion of the surface of the first substrate to which the third substrate is to be bonded by the anode bonding and exposing a bonding surface after the first process; and a third process of performing the anode bonding to bond the third substrate to the bonding surface of the first substrate.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: June 27, 2017
    Assignee: Seiko Epson Corporation
    Inventor: Atsuki Naruse
  • Patent number: 9521319
    Abstract: Systems and methods in accordance with embodiments of the invention implement array cameras and array camera modules that have spectral filters disposed outside of constituent image sensors. In one embodiment, an array camera module includes: a lens stack array including lens elements arranged to form a plurality of optical channels, each optical channel including a field-of-view that is shifted with respect to the fields-of-views of each other optical channel so that each shift includes a sub-pixel shifted view of the scene, a glass substrate located within an optical channel, and a spectral filter disposed within, or else proximate to, a glass substrate within the lens stack array; and an imager array including a plurality of focal planes, where each focal plane includes a plurality of rows of pixels that also form a plurality of columns of pixels, and where each focal plane does not include pixels from another focal plane.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: December 13, 2016
    Assignee: Pelican Imaging Corporation
    Inventors: Errol Mark Rodda, Jacques Duparré
  • Patent number: 9515034
    Abstract: A conductive structure is formed in a last metal layer of an integrated circuit. Passivation material is patterned over a portion of the conductive structure. A first trench is patterned around a selected portion of the passivation material. The selected portion represents a bond region of a wire bond to be formed above the passivation material. A portion of the passivation material completely covers a bottom of the trench. A layer of conductive material is conformally deposited over the passivation material. The conformal depositing resulting in a second trench forming in the conductive material over the first trench in the passivation material. The second trench is positioned to contain at least a portion of a splash of the conductive material when the wire bond is subsequently formed.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: December 6, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Sohrab Safai, David B. Clegg, Tu-Anh N. Tran
  • Patent number: 9511999
    Abstract: A method for sealing cavities in micro-electronic/-mechanical system (MEMS) devices to provide a controlled atmosphere within the sealed cavity includes providing a semiconductor substrate on which a template is provided on a localized area of the substrate. The template defines the interior shape of the cavity. Holes are made so as to enable venting of the cavity to provide a desired atmosphere to enter into the cavity through the hole. Finally, a sealing material is provided in the hole to seal the cavity. The sealing can be made by compression and/or melting of the sealing material.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: December 6, 2016
    Assignee: SILEX MICROSYSTEMS AB
    Inventors: Thorbjorn Ebefors, Niklas Svedin
  • Patent number: 9502380
    Abstract: A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer are provided. In some embodiments, the method is performed by placing an interposer with one or more through-substrate-vias (TSVs) on a first adhesive layer overlying a first carrier substrate. Connection structures are arranged along a first surface of the interposer facing the first adhesive layer. A first molding compound is formed over the first adhesive layer and surrounding the interposer. The first molding compound is arranged to expose the TSVs along a second surface of the interposer. A first redistribution structure is formed over the second surface of the interposer and the first molding compound, and conductive bump structures are formed over the first redistribution structure. A first packaged die is bonded to the conductive bump structures.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Cheng Lin, Shang-Yun Hou
  • Patent number: 9487391
    Abstract: Embodiments of mechanisms for forming a micro-electro mechanical system (MEMS) device are provided. The MEMS device includes a CMOS substrate, a cap substrate, and a MEMS substrate bonded between the CMOS substrate and the cap substrate. The MEMS substrate includes a first movable element and a second movable element. The MEMS device also includes a first closed chamber and a second closed chamber, which are between the MEMS substrate and the cap substrate. The first movable element is in the first closed chamber, and the second movable element is in the second closed chamber. A first pressure of the first closed chamber is higher than a second pressure of the second closed chamber.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: November 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Wen Cheng, Chia-Hua Chu
  • Patent number: 9478499
    Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The semiconductor package structure has a substrate and a die stack of n die(s), wherein n?1. The substrate has a first side, a second side and an opening extending from the first side to the second side. The die stack is disposed in the opening. The thickness of the substrate is substantially the same as the thickness of the die stack.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: October 25, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chien-Li Kuo
  • Patent number: 9418961
    Abstract: An apparatus including a bond head, a supplemental support, a reduction module, and a transducer is provided. The bond head holds a first substrate that contains a first set of metal pads. The supplemental support holds a second substrate that contains a second set of metal pads. The aligner forms an aligned set of metal pads by aligning the first substrate to the second substrate. The reduction module contains the aligned substrates and a reduction gas flows into the reduction module. The transducer provides repeated relative motion to the aligned set of metal pads.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: August 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu
  • Patent number: 9351084
    Abstract: A size of a port hole in a package for a micro-electro-mechanical (MEMS) microphone can be modified to improve performance of the MEMS microphone while protecting the MEMS microphone from environmental interference. As an example, the port hole diameter is increased along a thickness of a substrate coupled to the MEMS microphone to reduce air mass loading and air flow resistance and thus, increase the resonant frequency, resonant peak, signal-to-noise ratio (SNR) and/or a range for flat frequency response of the MEMS microphone. In one aspect, the port hole can be created by mechanical and/or laser drilling. In another aspect, the port hole can be created by forming a cavity in the substrate over a drilled port hole.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: May 24, 2016
    Assignee: INVENSENSE, INC.
    Inventor: Jia Gao
  • Patent number: 9351404
    Abstract: An electronic device comprising a laminate comprising pluralities of insulator layers each provided with conductor patterns, and an amplifier-constituting semiconductor device mounted to a mounting electrode formed on an upper surface of the laminate, a first ground electrode being formed on an insulator layer near an upper surface of the laminate; a second ground electrode being formed on an insulator layer near a lower surface of the laminate; the first ground electrode being connected to the mounting electrode through pluralities of via-holes; conductor patterns constituting the first circuit block being disposed in a region below the amplifier-constituting semiconductor device between the first ground electrode and the second ground electrode; and at least part of a conductor pattern for a line connecting the first circuit block to the amplifier-constituting semiconductor device being disposed on an insulator layer sandwiched by the mounting electrode and the first ground electrode.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: May 24, 2016
    Assignee: HITACHI METALS, LTD.
    Inventor: Hirotaka Satake
  • Patent number: 9318438
    Abstract: A method for selectively removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The method comprises oxidizing a semiconductor structure comprising a substrate and at least one copper feature and removing a portion of the substrate using an etchant comprising SF6 without forming copper sulfide on the at least one copper feature. Additional methods are also disclosed, as well as semiconductor structures produced from such methods.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: April 19, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Mark A. Bossler, Jaspreet S. Gandhi, Christopher J. Gambee, Randall S. Parker
  • Patent number: 9305885
    Abstract: A multi-chip package structure is provided, including a substrate having a grounding structure; two semiconductor elements disposed on and electrically connected to the substrate; an encapsulant formed on the substrate and encapsulating semiconductor elements, wherein the encapsulant has a plurality of round holes formed between the semiconductor elements; and an electromagnetic shielding structure formed in each of the round holes and connected to the grounding structure to achieve electromagnetic shielding effects. A method for forming the multi-chip package is also provided.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: April 5, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Tai-Tsung Hsu, Cheng-Yu Chiang, Miao-Wen Chen, Wen-Jung Chiang, Hsin-Hung Lee
  • Patent number: 9287140
    Abstract: Provided are semiconductor packages having through electrodes and methods of fabricating the same. The method may include may include forming a wafer-level package including first semiconductor chips stacked on a second semiconductor chip, forming a chip-level package including fourth semiconductor chips stacked on a third semiconductor chip stacking a plurality of the chip-level packages on a back surface of the second semiconductor substrate of the wafer-level package, polishing the first mold layer of the wafer-level package and the first semiconductor chips to expose a first through electrodes of the first semiconductor chip, and forming outer electrodes on the polished first semiconductor chips to be connected to the first through electrodes, respectively.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: March 15, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyunsoo Chung, Jongyeon Kim, In-Young Lee, Tae-Je Cho
  • Patent number: 9260296
    Abstract: A method embodiment includes providing a micro-electromechanical (MEMS) wafer including a polysilicon layer having a first and a second portion. A carrier wafer is bonded to a first surface of the MEMS wafer. Bonding the carrier wafer creates a first cavity. A first surface of the first portion of the polysilicon layer is exposed to a pressure level of the first cavity. A cap wafer is bonded to a second surface of the MEMS wafer opposite the first surface of the MEMS wafer. The bonding the cap wafer creates a second cavity comprising the second portion of the polysilicon layer and a third cavity. A second surface of the first portion of the polysilicon layer is exposed to a pressure level of the third cavity. The first cavity or the third cavity is exposed to an ambient environment.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hua Chu, Chun-Wen Cheng
  • Patent number: 9232657
    Abstract: A wiring substrate includes a core, first and second wiring layers formed on opposite sides of the core, an electronic component arranged in a cavity of the core, and a first insulating layer that fills the cavity and covers the one surface of the core. The electronic component is partially buried in the first insulating layer and partially projected from the cavity and exposed from the first insulating layer. A second insulating layer covers the first insulating layer. A third insulating layer covers the core and the projected and exposed portion of the electronic component. The thickness of the third insulating layer where the first wiring layer is located is equal to the total thickness of the first insulating layer and the second insulating layer where the second wiring layer is located.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: January 5, 2016
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Takayuki Kiwanami, Junji Sato, Katsuya Fukase
  • Patent number: 9209151
    Abstract: A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: December 8, 2015
    Assignee: General Electric Company
    Inventors: Shakti Singh Chauhan, Paul Alan McConnelee, Arun Virupaksha Gowda
  • Patent number: 9190355
    Abstract: A sub-assembly for a packaged integrated circuit (IC) device has a planar substrate. The substrate's top side has multiple sets electrically connected bond posts arranged in corresponding nested contour zones. Each contour zone includes a different bond post of each bond-post set. The bottom side has a different set of pad connectors electrically connected to the each top-side bond-post set. The sub-assembly can be used for different IC packages having IC dies of different sizes, with different contours of bond posts available for electrical connection depending on the size of the IC die.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: November 17, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Weng Hoong Chan, Ly Hoon Khoo, Boon Yew Low, Navas Khan Oratti Kalandar
  • Patent number: 9190459
    Abstract: A manufacturing method of an organic light emitting diode (OLED) display includes: supplying a circuit film on the pad area of the display panel and bonding a first end portion of the circuit film to the pad area; vertically standing and inserting the display panel in a bonding device; holding a portion of the circuit film including a second end portion to be horizontal by using a rotating device including a vacuum absorbing portion; supplying a flexible printed circuit (FPC) into a space under the second end portion of the circuit film, and attaching the flexible printed circuit to the second end portion of the circuit film; and operating the rotating device to move the second end portion to a vertical position, and separating the circuit film from the vacuum absorbing portion.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: November 17, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hae-Goo Jung, Do-Hyung Ryu
  • Patent number: 9156684
    Abstract: Methods for manufacturing multiple top port, surface mount microphones, each containing a micro-electro-mechanical system (MEMS) microphone die, are disclosed. Each surface mount microphone features a substrate with metal pads for surface mounting the package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The surface mount microphones are manufactured from a panel of unsingulated substrates, and each MEMS microphone die is substrate-mounted. Individual covers, each with an acoustic port, are joined to the panel of unsingulated substrates. Each individual substrate and cover pair cooperates to form an acoustic chamber for its respective MEMS microphone die, which is acoustically coupled to the acoustic port in the cover. The completed panel is singulated to form individual MEMS microphones.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: October 13, 2015
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 9161461
    Abstract: A multilayer electronic structure comprising a plurality of layers extending in an X-Y plane consisting of a dielectric material surrounding metal via posts that conduct in a Z direction perpendicular to the X-Y plane, wherein at least one multilayered hole crosses at least two layers of the plurality of layers and comprises at least two hole layers in adjacent layers of the multilayer composite electronic structure, wherein the at least two holes in adjacent layers have different dimensions in the X-Y plane, such that a perimeter of the multilayered hole is stepped and where at least one hole is an aperture to a surface of the multilayer electronic structure.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: October 13, 2015
    Assignee: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.
    Inventors: Dror Hurwitz, Simon Chan, Alex Huang
  • Patent number: 9161454
    Abstract: A method of packaging an electrical device including following steps is provided. A circuit board including a substrate and a first conductive pattern is provided. The electrical device having an electrode is disposed on the circuit board. A dielectric layer is formed on the circuit board to cover the electrical device, the electrode and the first conductive pattern, wherein a first caving pattern is formed in the dielectric layer by the first conductive pattern. The dielectric layer is patterned to form a through hole and a second caving pattern connecting with the through hole and exposing the electrode. A conductive material is filled in the through hole and the second caving pattern to form a conductive via in the through hole and a second conductive pattern in the second caving pattern. The substrate is removed. Moreover, the electrical device package structure is also provided.
    Type: Grant
    Filed: December 24, 2012
    Date of Patent: October 13, 2015
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Shu-Sheng Chiang, Tsung-Yuan Chen, Shih-Lian Cheng
  • Patent number: 9153551
    Abstract: A flip chip packaged component includes a die having a first surface and a dielectric barrier disposed on the first surface of the die. The dielectric barrier at least partially surrounds a designated location on the first surface of the die. A plurality of bumps is disposed on the first surface of the die on an opposite side of the dielectric barrier from the designated location. The flip chip packaged component further includes a substrate having a plurality of bonding pads on a second surface thereof. A cavity is defined by the first surface of the die, the dielectric barrier, and the substrate. A molding compound encapsulates the die and at least a portion of the substrate.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: October 6, 2015
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventor: Steve X. Liang
  • Patent number: 9150409
    Abstract: Methods for manufacturing multiple bottom port, surface mount microphones, each containing a micro-electro-mechanical system (MEMS) microphone die, are disclosed. Each surface mount microphone features a substrate with metal pads for surface mounting the package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The surface mount microphones are manufactured from a panel of unsingulated substrates, each substrate having an acoustic port, and each MEMS microphone die is substrate-mounted and acoustically coupled to its respective acoustic port. Individual covers are joined to the panel of unsingulated substrates, and each individual substrate and cover pair cooperates to form an acoustic chamber for its respective MEMS microphone die. The completed panel is singulated to form individual MEMS microphones.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: October 6, 2015
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 9148731
    Abstract: A top port, surface mount package for a micro-electro-mechanical system (MEMS) microphone die is disclosed. The surface mount package features a substrate with metal pads for surface mounting the package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The surface mount microphone package has a cover with an acoustic port, and the MEMS microphone die is substrate-mounted and acoustically coupled to the acoustic port. The substrate and the cover are joined together to form the MEMS microphone, and the substrate and cover cooperate to form an acoustic chamber for the substrate-mounted MEMS microphone die.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: September 29, 2015
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 9139421
    Abstract: A top port, surface mount package for a micro-electro-mechanical system (MEMS) microphone die is disclosed. The surface mount package features a substrate with metal pads for surface mounting the package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The surface mount microphone package has a cover with an acoustic port, and the MEMS microphone die is substrate-mounted and acoustically coupled to the acoustic port. The substrate and the cover are joined together to form the MEMS microphone, and the substrate and cover cooperate to form an acoustic chamber for the substrate-mounted MEMS microphone die.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: September 22, 2015
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 9139422
    Abstract: A bottom port, surface mount package for a micro-electro-mechanical system (MEMS) microphone die is disclosed. The surface mount package features a substrate with metal pads for surface mounting the package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The surface mount microphone package has a cover, and the MEMS microphone die is substrate-mounted and acoustically coupled to the acoustic port in the substrate. The substrate and the cover are joined together to form the MEMS microphone, and the substrate and cover cooperate to form an acoustic chamber for the substrate-mounted MEMS microphone die.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: September 22, 2015
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 9096423
    Abstract: Methods for manufacturing multiple top port, surface mount microphones, each containing a micro-electro-mechanical system (MEMS) microphone die, are disclosed. Each surface mount microphone features a substrate with metal pads for surface mounting the package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The surface mount microphones are manufactured from panels of substrates, sidewall spacers, and lids. Each MEMS microphone die is lid-mounted and acoustically coupled to the acoustic port disposed in the lid. The panels are joined together, and each individual substrate, sidewall spacer, and lid cooperate to form an acoustic chamber for its respective MEMS microphone die. The joined panels are then singulated to form individual MEMS microphones.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: August 4, 2015
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 9067780
    Abstract: Methods for manufacturing multiple top port, surface mount microphones, each containing a micro-electro-mechanical system (MEMS) microphone die, are disclosed. Each surface mount microphone features a substrate with metal pads for surface mounting the package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The surface mount microphones are manufactured from a panel of unsingulated substrates, and each MEMS microphone die is substrate-mounted. Individual covers, each with an acoustic port, are joined to the panel of unsingulated substrates, and each individual substrate and cover pair cooperates to form an acoustic chamber for its respective MEMS microphone die, which is acoustically coupled to the acoustic port in the cover. The completed panel is singulated to form individual MEMS microphones.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: June 30, 2015
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 9051171
    Abstract: A bottom port, surface mount package for a micro-electro-mechanical system (MEMS) microphone die is disclosed. The surface mount package features a substrate with metal pads for surface mounting the package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The surface mount microphone package has a cover, and the MEMS microphone die is substrate-mounted and acoustically coupled to the acoustic port in the substrate. The substrate and the cover are joined together to form the MEMS microphone, and the substrate and cover cooperate to form an acoustic chamber for the substrate-mounted MEMS microphone die.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: June 9, 2015
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 9048245
    Abstract: A method including providing a fixture comprising a trap ring, a base plate having a recess adapted to receive a laminate substrate, the base plate including an opening and an adjustable height center button disposed in the opening, the opening being located within the recess and located in a center of the laminate substrate, characterizing the laminate substrate for warpage characteristics by using one of room temperature techniques and elevated temperature techniques, determining a horizontal plane distortion based on the warpage characteristics, and placing the laminate substrate into the fixture with an adjustment to correct the horizontal plane distortion, the adjustment is provided by the adjustable height center button, wherein the adjustable height center button contacts the laminate substrate. The method further includes fluxing the laminate substrate, placing a chip onto the laminate substrate, and placing the fixture into a reflow furnace to join the chip and the laminate substrate.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: June 2, 2015
    Assignee: International Business Machines Corporation
    Inventors: Edmund Blackshear, Thomas E. Lombardi, Donald A. Merte, Steven P. Ostrander, Thomas Weiss, Jiantao Zheng
  • Publication number: 20150145131
    Abstract: A package substrate includes a core layer having a first surface and a second surface which are opposite to each other, a ball land pad disposed on the first surface of the core layer, an opening that penetrates the core layer to expose the ball land pad, and a dummy ball land disposed on the second surface of the core layer to surround the opening. The dummy ball land includes at least one sub-pattern and at least one vent hole. Related semiconductor packages and related methods are also provided.
    Type: Application
    Filed: April 25, 2014
    Publication date: May 28, 2015
    Applicant: SK hynix Inc.
    Inventors: Jong Woo YOO, Qwan Ho CHUNG
  • Patent number: 9040360
    Abstract: Methods for manufacturing multiple bottom port, surface mount microphones, each containing a micro-electro-mechanical system (MEMS) microphone die, are disclosed. Each surface mount microphone features a substrate with metal pads for surface mounting the package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The surface mount microphones are manufactured from panels of substrates, sidewall spacers, and lids. Each MEMS microphone die is substrate-mounted and acoustically coupled to the acoustic port disposed in the substrate. The panels are joined together, and each individual substrate, sidewall spacer, and lid cooperate to form an acoustic chamber for its respective MEMS microphone die. The joined panels are then singulated to form individual MEMS microphones.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: May 26, 2015
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 9041152
    Abstract: In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. A magnetic layer is positioned within the coil. In another embodiment, a coil is formed on a single substrate, wherein a magnetic layer is positioned within the coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Wei Luo, Hsiao-Tsung Yen, Chin-Wei Kuo, Min-Chie Jeng
  • Publication number: 20150137342
    Abstract: An integrated circuit package includes an integrated circuit and an interposer layer. The interposer layer is arranged above the integrated circuit and includes an inductor formed at least partially within the interposer layer. The inductor includes a first pair of conductive pillars including a first conductive pillar and a second conductive pillar formed within a first via and a second via, respectively. The first via and the second via are formed through the interposer layer. The inductor further includes a first conductive trace connected across first ends of the first conductive pillar and the second conductive pillar on a first surface of the interposer layer, and a first conductive interconnect structure connected between second ends of the first conductive pillar and the second conductive pillar and the integrated circuit.
    Type: Application
    Filed: November 19, 2014
    Publication date: May 21, 2015
    Inventor: Sehat Sutardja
  • Patent number: 9035450
    Abstract: A semiconductor substrate includes a semiconductor chip and an interconnect substrate. The interconnect substrate has an interconnect region between a first main surface formed with plural orderly arranged first and second signal electrodes connected to the semiconductor chip, and a second main surface. The interconnect region has a core substrate, interconnect layers formed on both surfaces thereof, plural first through holes and plural first vias that pass through the interconnect layer on the side of the first main surface for forming impedance matching capacitances. Each first through hole is connected to a first signal interconnect at a position spaced part from the first signal electrode by a first interconnect length and each first via is connected to the second signal interconnect at a position spaced apart from the second signal electrode by a second interconnect length that is substantially equal with the first interconnect length.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: May 19, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shuuichi Kariyazaki, Ryuichi Oikawa
  • Patent number: 9035473
    Abstract: Provided are a thin circuit device with show-through of thin metal wires prevented and a method of manufacturing the circuit device. A circuit device mainly includes: a substrate including a first substrate and second substrates; pads formed respectively on upper surfaces of the second substrates; a semiconductor element fixed on an upper surface of the first substrate; thin metal wires each connecting the semiconductor elements and a corresponding one of the pads; and a sealing resin with which the semiconductor element and the thin metal wires are covered, and which thereby seals the circuit device with the semiconductor element and the thin metal wires disposed therein. Furthermore, filler particles located in the uppermost portion of the sealing resin are covered with a resin material constituting the sealing resin.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: May 19, 2015
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Isao Nakazato, Shigeharu Yoshiba, Takashi Sekibata