Abstract: An insulated metal substrate (IMS) and a method for manufacturing the same are disclosed. The IMS includes an electrically conductive line pattern layer, an encapsulation layer, a first adhesive layer, a second adhesive layer, and a heat sink element. The encapsulation layer fills a gap between a plurality of electrically conductive lines of the electrically conductive line pattern layer. An upper surface of the encapsulation layer is flush with an upper surface of the electrically conductive line pattern layer. The first and second adhesive layer are disposed between the electrically conductive line pattern layer and the heat sink element. A bonding strength between the first adhesive layer and the second adhesive layer is greater than 80 kg/cm2.

Abstract: A method for manufacturing an electronic device includes the steps of providing a flexible substrate, forming an electric circuit layer on the flexible substrate at an elevated temperature, and enhancing a transmittance of the flexible substrate after forming the electric circuit layer.

Abstract: In an embodiment a lid includes a top section and a side section arranged below the top section. A vertical height of the top section is calculated by ITS*HB, ITS being a first multiple integer and HB being a basic height, and a vertical height of the side section is calculated by Iss* HB, Iss being a second multiple integer and HB being the basic height HB.

Abstract: A wireless circuit includes a housing having at least one opening, and sensor connected to the housing at the opening. The sensor includes a first layer having a first dimension and a second layer having a second dimension shorter than the first dimension. The second layer may be positioned entirely within the housing and a surface of said first layer may be exposed to an exterior of the housing.

Abstract: A package structure includes a first circuit board, a second circuit board, at least one electronic component, at least one conductive lead, and a molding compound. The first circuit board includes a first circuit layer and a second circuit layer. The second circuit board includes a third circuit layer and a fourth circuit layer. The electronic component is disposed between the first circuit board and the second circuit board. The conductive lead contacts at least one of the second circuit layer and the third circuit layer. The conductive lead has a vertical height, and the vertical height is greater than a vertical distance between the second circuit layer and the third circuit layer. The molding compound covers the first circuit board, the second circuit board, the electronic component, and the conductive lead. The molding compound exposes the first circuit layer and the fourth circuit layer, and the conductive lead extends outside the molding compound.

Abstract: A micro-LED display device and a manufacturing method thereof are disclosed. The method comprises: forming micro-LEDs (202) on a carrier substrate (201), wherein the carrier substrate (201) is transparent for a laser which is used in laser lifting-off; filling trenches between the micro-LEDs (202) on the carrier substrate (201) with a holding material (209); performing a laser lifting-off on selected ones of the micro-LEDs (202) to lift off them from the carrier substrate (201), wherein the selected micro-LEDs (202) are held on the carrier substrate (201) through the holding material (209); bonding the selected micro-LEDs (202) onto a receiving substrate (207) of the micro-LED display device; separating the selected micro-LEDs (202) from the carrier substrate (201) to transfer them to the receiving substrate (207).

Abstract: Embodiments disclosed herein include an electronics package. In an embodiment, the electronics package comprises a package substrate and a die on the package substrate. In an embodiment, a mold layer is positioned over the package substrate. In an embodiment, the electronics package further comprises through-mold interconnects through the mold layer, and a trench that extends at least partially into the mold layer.

Abstract: An array of through-silicon via (TSV) structures is formed through a silicon substrate, and package-side metal pads are formed on backside surfaces of the array of TSV structures. The silicon substrate is disposed over a carrier substrate, and an epoxy molding compound (EMC) interposer frame is formed around the silicon substrate. A die-side redistribution structure is formed over the silicon substrate and the EMC interposer frame, and at least one semiconductor die is attached to the die-side redistribution structure. The carrier substrate is removed from underneath the package-side metal pads. A package-side redistribution structure is formed on the package-side metal pads and on the EMC interposer frame. Overlay tolerance between the package-side redistribution wiring interconnects and the package-side metal pads increases due to increased areas of the package-side metal pads.

Abstract: A plastic material substrate has a die mounting location for a semiconductor die. Metallic traces are formed on selected areas of the plastic material substrate, wherein the metallic traces provide electrically-conductive paths for coupling to the semiconductor die. The semiconductor die is attached onto the die mounting location. The semiconductor die attached onto the die mounting location is electrically bonded to selected ones of the metallic traces formed on the plastic material substrate. A package material is molded onto the semiconductor die attached onto the die mounting location.

Abstract: Implementations of a silicon-in-insulator (SOI) semiconductor die may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be included through a silicon layer coupled to a insulative layer.

Abstract: Aspects of the disclosure provide a waterproof packaging technique for fabricating waterproof microphones in mobile devices. A device based on the waterproof packaging technique can include a microelectromechanical system (MEMS) device, a housing enclosing the MEMS device, and a liquid-resistant air inlet passive device (LRAPD) on the housing. The LRAPD can include at least one channel connecting an exterior of the housing with a chamber formed between the housing and the MEMS device. An inside surface of the channel can be coated with a liquid-repellant coating. In some examples, the liquid-repellant coating can be a self-assembled monolayer (SAM) coating.

Abstract: A semiconductor package is provided. The semiconductor package includes a connection structure, a semiconductor chip, and a connection metal. The connection structure includes a redistribution layer and a connection via layer. The semiconductor chip is disposed on the connection structure, and includes a connection pad. The connection metal is disposed on the connection structure and is electrically connected to the connection pad by the connection structure. The connection via layer includes a connection via having a major axis and a minor axis, and in a plan view, the minor axis of the connection via intersects with the connection metal.

Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

Abstract: The method manufactures a hermetic sealing lid member used for an electronic component housing package including an electronic component arrangement member on which an electronic component is arranged. The method includes forming a clad material in which a silver brazing layer that contains Ag and Cu and a first Fe layer arranged on the silver brazing layer and made of Fe or an Fe alloy are bonded to each other by roll-bonding a silver brazing plate that contains Ag and Cu and a first Fe plate made of Fe or an Fe alloy to each other and performing first heat treatment for diffusion annealing; softening the clad material by performing second heat treatment; and forming the hermetic sealing lid member in a box shape including a recess portion by bending the softened clad material.

Abstract: A semiconductor package includes a redistribution structure including a redistribution insulating layer and a redistribution pattern, a semiconductor chip provided on a first surface of the redistribution insulation layer and electrically connected to the redistribution pattern, and a lower electrode pad provided on a second surface opposite to the first surface of the redistribution insulating layer, the lower electrode pad including a first portion embedded in the redistribution insulating layer and a second portion protruding from the second surface of the redistribution insulating layer, wherein a thickness of the first portion of the lower electrode pad is greater than a thickness of the second portion of the lower electrode pad.

Abstract: A semiconductor package structure includes a first package, a second package over the first package, a plurality of connectors between the first package and the second package and a plurality of baffle structures between the first package and the second package. The second package includes a bonding region and a periphery region surrounding the bonding region. The connectors are disposed in the bonding region to provide electrical connections between the first package and the second package. The baffle structures are disposed in the periphery region and are separated from each other.

Abstract: A system and method for detecting dynamic electromagnetic emission of an integrated circuit (IC) chip is provided. One embodiment of the method, includes exciting nitro vacancy (NV) centers of a diamond slide located in close proximity to the IC chip via use of light, resulting in an NV fluorescence; providing an optical readout of the NV fluorescence, wherein the optical readout provides quantum states of the NV centers, thereby providing a spectra of electromagnetic fields of the IC chip. A determination is then made of at least one of the group comprising clock frequencies of the IC chip, referred to herein as determined clock frequencies, and data bandwidth of the IC chip, referred to herein as determined data bandwidth of the IC chip, from the spectra of electromagnetic fields of the IC chip.

Abstract: The present disclosure provides a semiconductor structure, including a sensing substrate, a capping substrate over the sensing substrate, the capping substrate having a first surface facing toward the sensing substrate and a second surface facing away from the sensing substrate, wherein the capping substrate comprises a through hole extending from the first surface to the second surface, a spacer between the sensing substrate and the capping substrate, the spacer, the sensing substrate, and the capping substrate forming a cavity connecting with the through hole, and a sealing structure at the second surface and aligning with the through hole, wherein the sealing structure comprises a metal layer and a dielectric layer.

Abstract: Embodiments of three-dimensional (3D) memory devices with 3D phase-change memory (PCM) and methods for forming and operating the 3D memory devices are disclosed. In an example, a 3D memory device includes a first semiconductor structure including a peripheral circuit, an array of 3D PCM cells, and a first bonding layer including a plurality of first bonding contacts. The 3D memory device also further includes a second semiconductor structure including an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts. The 3D memory device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

Abstract: Provided is a three-dimensional integrated circuit (3DIC) structure including a first die and a second die bonded together by a hybrid bonding structure. One of the first die and the second die has a pad and a cap layer disposed over the pad. The cap layer exposes a portion of a top surface of the pad, and the portion of the top surface of the pad has a probe mark. A bonding metal layer of the hybrid bonding structure penetrates the cap layer to electrically connect to the pad. A method of fabricating the first die or the second die of 3DIC structure is also provided.

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity. The method for forming the cavity further includes forming at least one first vent hole of a first dimension which is sized to avoid or minimize material deposition on a beam structure during sealing processes. The method for forming the cavity further includes forming at least one second vent hole of a second dimension, larger than the first dimension.

Abstract: A printed circuit board of an embodiment includes a board, a first ground plane provided on a first face of the board and having a first opening, a first wiring provided above the first ground plane, a second ground plane provided on a second face facing the first face of the board and having a second opening, a second wiring provided above the second ground plane, and a third wiring penetrating the board between the first opening and the second opening and connecting the first wiring and the second wiring. The third wiring is provided in the first opening and in the second opening when viewed from a direction perpendicular to the first face of the board.

Abstract: An electronic package is provided. An electronic component and a plurality of conductive pillars electrically connected with the electronic component are embedded in an encapsulating layer. Each of the conductive pillars has a circumferential surface and two end surfaces wider than the circumferential surface in width. The encapsulating layer encapsulates and protects the electronic component effectively, so as to improve the reliability of the electronic package. A method for fabricating the electronic package is also provided.

Abstract: In fabricating a radio frequency (RF) switch, a phase-change material (PCM) and a heating element, underlying an active segment of the PCM and extending outward and transverse to the PCM, are provided. Lower portions of PCM contacts for connection to passive segments of the PCM are formed, wherein the passive segments extend outward and are transverse to the heating element. Upper portions of the PCM contacts are formed from a lower interconnect metal. Heating element contacts are formed cross-wise to the PCM contacts. The heating element contacts can comprise a top interconnect metal directly connecting with terminal segments of the heating element. The heating element contacts can comprise a top interconnect metal and intermediate metal segments for connecting with the terminal segments of the heating element.

Abstract: A fan-out semiconductor package includes: a core member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the core member and the semiconductor chip; and a connection member disposed on the core member and an active surface of the semiconductor chip and including a redistribution layer connected to the connection pads. The core member includes a plurality of wiring layers disposed on different levels, a dielectric is disposed between the plurality of wiring layers of the core member, one of the plurality of wiring layers includes an antenna pattern, the other of the plurality of wiring layers includes a ground pattern, and the antenna pattern is connected to the connection pads through the redistribution layer in a signal manner.

Abstract: Reversible (relatively weak) anodic bonds permit glass and silicon components to be separated without damaging the components so that they can be reused. To this end, chamfered glass with high aluminum content can be used during the original anodic bonding. Anodic bonding is terminated after complete intimate contact is achieved and while the bond is reversible. The high aluminum content impedes further bond strengthening so that the bond does not become non-reversible via contact bonding. The chamfer provides access near the glass-silicon interface for prying the glass off the silicon to effect debonding without damaging the glass or the silicon. Accordingly, the glass, the silicon, or both may be rebounded (rather than being wastefully disposed).

Abstract: A light source module including a substrate, an LED package, an optical cover, and at least one packing layer is provided. The LED package is disposed on the substrate and includes an encapsulant. The optical cover is disposed above the LED package. The at least one packing layer is filled between the LED package and the optical cover.

Abstract: A solid state drive apparatus includes a housing having a first accommodation space and a second accommodation space; a substrate mounted in the first accommodation space, wherein at least one non-volatile memory chip is mounted on the substrate; and a heat dissipation member mounted in the second accommodation space and including an isolation barrier that defines a boundary between the second accommodation space and the first accommodation space and a plurality of fin portions that extend from the isolation barrier away from the first accommodation space, wherein a plurality of through air holes are provided in a side of the housing adjacent the second accommodation space.

Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a molded package body having an upper peripheral edge portion, an air cavity around which the upper peripheral edge portion extends, and a cover piece bonded to the upper peripheral edge portion to enclose the air cavity. The cover piece has a lower peripheral edge portion, which cooperates with the upper peripheral edge portion to define a cover-body interface. The cover-body interface includes an annular channel extending around the cover-body interface, as taken about the package centerline, and first and second hardstop features formed on the upper peripheral edge portion of the molded package body and on the lower peripheral edge portion of the cover piece, respectively. The hardstop features contact to determine a vertical height of the annular channel, as taken along the package centerline.

Abstract: A protective tape including an adhesive agent layer, a thermoplastic resin layer, and a matrix film layer in this order to a surface of a wafer on which a bump electrode is formed; grinding a surface of the wafer opposite to the surface on which the protective tape is pasted; pasting an adhesive tape to the ground surface of the wafer; peeling the protective tape so that the adhesive agent layer remains and other layers are removed; dicing the wafer to which the adhesive tape is pasted to obtain individual semiconductor chips; and curing the adhesive agent layer before dicing; the adhesive agent layer after curing has a shear storage modulus of 3.0E+08 Pa to 5.0E+09 Pa, and the ratio of the thickness of the adhesive agent layer of the protective tape before pasting to the height of the bump electrode is 1/30 to 1/6.

Abstract: A surface mount package for a micro-electro-mechanical system (MEMS) microphone die is disclosed. The surface mount package features a substrate with metal pads for surface mounting the package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The surface mount microphone package has a cover, and the MEMS microphone die is substrate-mounted and acoustically coupled to an acoustic port provided in the surface mount package. The substrate and the cover are joined together to form the MEMS microphone, and the substrate and cover cooperate to form an acoustic chamber for the substrate-mounted MEMS microphone die.

Abstract: A fan-out semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of the inactive surface, a first connection member disposed on the active surface and including a redistribution layer and a first via electrically connecting the connection pad to the redistribution layer, a passivation layer disposed on the first connection member, and an under-bump metal layer including an external connection pad disposed on the passivation layer and a second via connecting the external connection pad to the redistribution layer. In a vertical direction, the first and second vias are disposed within the external connection pad and do not overlap each other.

Abstract: The present invention provides a portable electronic device and an image-capturing module thereof, and an image-sensing assembly thereof. The image-sensing assembly includes an image-sensing chip, a spacer structure, and a filter element. The image-sensing chip has an image sensing area and a non-image sensing area surrounding the image sensing area. The spacer structure is disposed on the non-image sensing area. The filter element is disposed on the spacer structure so as to separate the filter element from the image-sensing chip by a predetermined distance. The image-sensing assembly can be applied to the image-capturing module, and the image-capturing module can be applied to the portable electronic device.

Abstract: A method of packaging an electrical device including following steps is provided. A circuit board including a substrate and a first conductive pattern is provided. The electrical device having an electrode is disposed on the circuit board. A dielectric layer is formed on the circuit board to cover the electrical device, the electrode and the first conductive pattern, wherein a first caving pattern is formed in the dielectric layer by the first conductive pattern. The dielectric layer is patterned to form a through hole and a second caving pattern connecting with the through hole and exposing the electrode. A conductive material is filled in the through hole and the second caving pattern to form a conductive via in the through hole and a second conductive pattern in the second caving pattern. The substrate is removed.

Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a molded package body having an upper peripheral edge portion, an air cavity around which the upper peripheral edge portion extends, and a cover piece bonded to the upper peripheral edge portion to enclose the air cavity. The cover piece has a lower peripheral edge portion, which cooperates with the upper peripheral edge portion to define a cover-body interface. The cover-body interface includes an annular channel extending around the cover-body interface, as taken about the package centerline, and first and second hardstop features formed on the upper peripheral edge portion of the molded package body and on the lower peripheral edge portion of the cover piece, respectively. The hardstop features contact to determine a vertical height of the annular channel, as taken along the package centerline.

Abstract: A device having: a substrate having a dielectric surface; a gate electrode; a drain electrode; a source electrode having a conductive contact and a two-dimensional material edge; and a dielectric material between the source and the gate. The source is adjacent to the gate. The drain electrode is not laterally between the edge and the gate electrode, and the distance from the drain electrode to the edge is greater than the distance from the gate electrode to the edge. The edge does not contact any other component of the device. The gate, drain, and source are not in electrical contact with each other. There is a line of sight or electron path from the edge to the drain electrode.

Abstract: Apparatuses and methods relating generally to a microelectronic package for wafer-level chip scale packaging with fan-out are disclosed. In an apparatus, there is a substrate having an upper surface and a lower surface opposite the upper surface. A microelectronic device is coupled to the upper surface with the microelectronic device in a face-up orientation. Wire bond wires are coupled to and extending away from the upper surface. Posts of the microelectronic device extend away from a front face thereof. Conductive pads are formed in the substrate associated with the wire bond wires for electrical conductivity.

Abstract: An object of the invention is to manufacture a semiconductor module small. A metal wire (212) connecting a control electrode (101) and a control terminal (21) rises to form a first angle (?1) from the control electrode (101) toward a first conductive portion (202), gradually goes in substantially parallel to the first conductive portion (202) as the metal wire approaches the first conductive portion (202), and is connected to the control terminal (21) to form a second angle (?2) smaller than the first angle (?1).

Abstract: A flexible display device includes a flexible substrate, an adhesion layer disposed on a surface of the flexible substrate, and a plurality of pixel structures in respective pixels on the adhesion layer. Each of the pixel structures on the adhesion layer includes a light emitting diode including an inorganic light emitting layer, and a thin film transistor which is connected to the light emitting diode and switches a state of the light emitting diode.

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity. The method for forming the cavity further includes forming at least one first vent hole of a first dimension which is sized to avoid or minimize material deposition on a beam structure during sealing processes. The method for forming the cavity further includes forming at least one second vent hole of a second dimension, larger than the first dimension.

Abstract: Embodiments generally relate to device and methods for detecting force. A force sensor may include a sense die, a substrate, one or more sense elements supported by the sense die, one or more electrical contacts located on the sense die and electrically coupled to electrical traces on the substrate, and an actuation element configured to transmit a force to the sense die. The width of the actuation element may be less than the distance between the one or more electrical contacts. In some embodiments, the actuation element may include a thin wedge/plate configured to interact with the sense die at a contact point. The thin wedge/plate may allow use of a smaller sense die and/or may allow closer placement of the one or more sense elements to the contact point and/or may prevent accidental contact with the one or more electrical contacts which may lead to a short circuit.

Abstract: A flexible display device includes a flexible substrate, an adhesion layer disposed on a surface of the flexible substrate, and a plurality of pixel structures in respective pixels on the adhesion layer. Each of the pixel structures on the adhesion layer includes a light emitting diode including an inorganic light emitting layer, and a thin film transistor which is connected to the light emitting diode and switches a state of the light emitting diode.

Abstract: A wiring board with a cavity for a built-in electronic component includes a conductor layer including a conductor circuit layer and a plane layer, and an insulating layer laminated on the conductor layer and having a cavity such that the cavity is forming an exposed portion of the plane layer and formed to mount a built-in electronic component on the exposed portion of the plane layer. The plane layer has a recess structure formed in an outer peripheral portion in the exposed portion of the plane layer.

Abstract: This invention relates to a method for producing an electrical system comprising a support (1) bearing on a first face at least one device; with the device comprising at least one electronic component (2) provided with at least one electrical connector (21, 22), with the method comprising: a step of setting in place of a cover (6) positioned above the component; said cover (6) comprising at least one passage (61, 62) according to a dimension in thickness of the cover (6) in such a way as to form an access space to the at least one electrical connector (21, 22), a step of forming a sealing seam (71) in such a way that the component is encapsulated in a sealed cavity (9) delimited by the first face of the support (1), the first face of the cover (6) and the sealing seam (7).

Abstract: In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor chip having a first side and an opposite second side, and a chip contact pad disposed on the first side of the semiconductor chip. A dielectric liner is disposed over the semiconductor chip. The dielectric liner includes a plurality of openings over the chip contact pad. A interconnect contacts the semiconductor chip through the plurality of openings at the chip contact pad.

Abstract: Disclosed herein is a circuit board. According to an exemplary embodiment of the present disclosure, a circuit board has a structure in which at least a portion of a first heat transfer structure in which a metal layer and an insulating layer are alternately stacked is inserted into an insulating part.

Abstract: A method of manufacturing an electronic device in which a second substrate (functional element) containing silicon and a third substrate (lid body) containing silicon are bonded to a first substrate containing alkali metal ions by anode bonding includes a first process of performing the anode bonding to bond the second substrate to a surface of the first substrate; a second process of removing at least a portion of the surface of the first substrate to which the third substrate is to be bonded by the anode bonding and exposing a bonding surface after the first process; and a third process of performing the anode bonding to bond the third substrate to the bonding surface of the first substrate.

Abstract: Systems and methods in accordance with embodiments of the invention implement array cameras and array camera modules that have spectral filters disposed outside of constituent image sensors. In one embodiment, an array camera module includes: a lens stack array including lens elements arranged to form a plurality of optical channels, each optical channel including a field-of-view that is shifted with respect to the fields-of-views of each other optical channel so that each shift includes a sub-pixel shifted view of the scene, a glass substrate located within an optical channel, and a spectral filter disposed within, or else proximate to, a glass substrate within the lens stack array; and an imager array including a plurality of focal planes, where each focal plane includes a plurality of rows of pixels that also form a plurality of columns of pixels, and where each focal plane does not include pixels from another focal plane.

Abstract: A conductive structure is formed in a last metal layer of an integrated circuit. Passivation material is patterned over a portion of the conductive structure. A first trench is patterned around a selected portion of the passivation material. The selected portion represents a bond region of a wire bond to be formed above the passivation material. A portion of the passivation material completely covers a bottom of the trench. A layer of conductive material is conformally deposited over the passivation material. The conformal depositing resulting in a second trench forming in the conductive material over the first trench in the passivation material. The second trench is positioned to contain at least a portion of a splash of the conductive material when the wire bond is subsequently formed.

Abstract: A method for sealing cavities in micro-electronic/-mechanical system (MEMS) devices to provide a controlled atmosphere within the sealed cavity includes providing a semiconductor substrate on which a template is provided on a localized area of the substrate. The template defines the interior shape of the cavity. Holes are made so as to enable venting of the cavity to provide a desired atmosphere to enter into the cavity through the hole. Finally, a sealing material is provided in the hole to seal the cavity. The sealing can be made by compression and/or melting of the sealing material.