Insulative Housing Or Support Patents (Class 438/125)
  • Patent number: 11178786
    Abstract: The method manufactures a hermetic sealing lid member used for an electronic component housing package including an electronic component arrangement member on which an electronic component is arranged. The method includes forming a clad material in which a silver brazing layer that contains Ag and Cu and a first Fe layer arranged on the silver brazing layer and made of Fe or an Fe alloy are bonded to each other by roll-bonding a silver brazing plate that contains Ag and Cu and a first Fe plate made of Fe or an Fe alloy to each other and performing first heat treatment for diffusion annealing; softening the clad material by performing second heat treatment; and forming the hermetic sealing lid member in a box shape including a recess portion by bending the softened clad material.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: November 16, 2021
    Assignee: HITACHI METALS, LTD.
    Inventors: Masayuki Yokota, Masaharu Yamamoto
  • Patent number: 11145611
    Abstract: A semiconductor package includes a redistribution structure including a redistribution insulating layer and a redistribution pattern, a semiconductor chip provided on a first surface of the redistribution insulation layer and electrically connected to the redistribution pattern, and a lower electrode pad provided on a second surface opposite to the first surface of the redistribution insulating layer, the lower electrode pad including a first portion embedded in the redistribution insulating layer and a second portion protruding from the second surface of the redistribution insulating layer, wherein a thickness of the first portion of the lower electrode pad is greater than a thickness of the second portion of the lower electrode pad.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: October 12, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongyoun Kim, Jungho Park, Seokhyun Lee, Yeonho Jang, Jaegwon Jang
  • Patent number: 11139282
    Abstract: A semiconductor package structure includes a first package, a second package over the first package, a plurality of connectors between the first package and the second package and a plurality of baffle structures between the first package and the second package. The second package includes a bonding region and a periphery region surrounding the bonding region. The connectors are disposed in the bonding region to provide electrical connections between the first package and the second package. The baffle structures are disposed in the periphery region and are separated from each other.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kuo-Chiang Ting, Tu-Hao Yu, Ting-Yu Yeh, Chia-Hao Hsu, Weiming Chris Chen, Wan-Yu Lee, Yu-Jie Su
  • Patent number: 11041809
    Abstract: A system and method for detecting dynamic electromagnetic emission of an integrated circuit (IC) chip is provided. One embodiment of the method, includes exciting nitro vacancy (NV) centers of a diamond slide located in close proximity to the IC chip via use of light, resulting in an NV fluorescence; providing an optical readout of the NV fluorescence, wherein the optical readout provides quantum states of the NV centers, thereby providing a spectra of electromagnetic fields of the IC chip. A determination is then made of at least one of the group comprising clock frequencies of the IC chip, referred to herein as determined clock frequencies, and data bandwidth of the IC chip, referred to herein as determined data bandwidth of the IC chip, from the spectra of electromagnetic fields of the IC chip.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: June 22, 2021
    Assignee: PRESIDENT AND FELLOWS OF HARVARD COLLEGE
    Inventors: Linbo Shao, Marko Loncar
  • Patent number: 10961114
    Abstract: The present disclosure provides a semiconductor structure, including a sensing substrate, a capping substrate over the sensing substrate, the capping substrate having a first surface facing toward the sensing substrate and a second surface facing away from the sensing substrate, wherein the capping substrate comprises a through hole extending from the first surface to the second surface, a spacer between the sensing substrate and the capping substrate, the spacer, the sensing substrate, and the capping substrate forming a cavity connecting with the through hole, and a sealing structure at the second surface and aligning with the through hole, wherein the sealing structure comprises a metal layer and a dielectric layer.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ching-Kai Shen, Yi-Chuan Teng, Wei-Chu Lin, Hung-Wei Liang, Jung-Kuo Tu
  • Patent number: 10937766
    Abstract: Embodiments of three-dimensional (3D) memory devices with 3D phase-change memory (PCM) and methods for forming and operating the 3D memory devices are disclosed. In an example, a 3D memory device includes a first semiconductor structure including a peripheral circuit, an array of 3D PCM cells, and a first bonding layer including a plurality of first bonding contacts. The 3D memory device also further includes a second semiconductor structure including an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts. The 3D memory device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: March 2, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Jun Liu
  • Patent number: 10886245
    Abstract: Provided is a three-dimensional integrated circuit (3DIC) structure including a first die and a second die bonded together by a hybrid bonding structure. One of the first die and the second die has a pad and a cap layer disposed over the pad. The cap layer exposes a portion of a top surface of the pad, and the portion of the top surface of the pad has a probe mark. A bonding metal layer of the hybrid bonding structure penetrates the cap layer to electrically connect to the pad. A method of fabricating the first die or the second die of 3DIC structure is also provided.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: January 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Sung-Feng Yeh
  • Patent number: 10882736
    Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity. The method for forming the cavity further includes forming at least one first vent hole of a first dimension which is sized to avoid or minimize material deposition on a beam structure during sealing processes. The method for forming the cavity further includes forming at least one second vent hole of a second dimension, larger than the first dimension.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: January 5, 2021
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, WISPRY, INC
    Inventors: Jeffrey C. Maling, Anthony K. Stamper, Dana R. DeReus, Arthur S. Morris, III
  • Patent number: 10827614
    Abstract: A printed circuit board of an embodiment includes a board, a first ground plane provided on a first face of the board and having a first opening, a first wiring provided above the first ground plane, a second ground plane provided on a second face facing the first face of the board and having a second opening, a second wiring provided above the second ground plane, and a third wiring penetrating the board between the first opening and the second opening and connecting the first wiring and the second wiring. The third wiring is provided in the first opening and in the second opening when viewed from a direction perpendicular to the first face of the board.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: November 3, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hitoshi Imi, Motochika Okano, Toshihiro Tsujimura
  • Patent number: 10811378
    Abstract: An electronic package is provided. An electronic component and a plurality of conductive pillars electrically connected with the electronic component are embedded in an encapsulating layer. Each of the conductive pillars has a circumferential surface and two end surfaces wider than the circumferential surface in width. The encapsulating layer encapsulates and protects the electronic component effectively, so as to improve the reliability of the electronic package. A method for fabricating the electronic package is also provided.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: October 20, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventor: Chih-Hsien Chiu
  • Patent number: 10707125
    Abstract: In fabricating a radio frequency (RF) switch, a phase-change material (PCM) and a heating element, underlying an active segment of the PCM and extending outward and transverse to the PCM, are provided. Lower portions of PCM contacts for connection to passive segments of the PCM are formed, wherein the passive segments extend outward and are transverse to the heating element. Upper portions of the PCM contacts are formed from a lower interconnect metal. Heating element contacts are formed cross-wise to the PCM contacts. The heating element contacts can comprise a top interconnect metal directly connecting with terminal segments of the heating element. The heating element contacts can comprise a top interconnect metal and intermediate metal segments for connecting with the terminal segments of the heating element.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: July 7, 2020
    Assignee: Newport Fab, LLC
    Inventors: Jefferson E. Rose, Gregory P. Slovin, David J. Howard, Michael J. DeBar, Nabil El-Hinnawy
  • Patent number: 10700024
    Abstract: A fan-out semiconductor package includes: a core member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the core member and the semiconductor chip; and a connection member disposed on the core member and an active surface of the semiconductor chip and including a redistribution layer connected to the connection pads. The core member includes a plurality of wiring layers disposed on different levels, a dielectric is disposed between the plurality of wiring layers of the core member, one of the plurality of wiring layers includes an antenna pattern, the other of the plurality of wiring layers includes a ground pattern, and the antenna pattern is connected to the connection pads through the redistribution layer in a signal manner.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: June 30, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Won Wook So, Yong Ho Baek, Doo Il Kim, Young Sik Hur
  • Patent number: 10676350
    Abstract: Reversible (relatively weak) anodic bonds permit glass and silicon components to be separated without damaging the components so that they can be reused. To this end, chamfered glass with high aluminum content can be used during the original anodic bonding. Anodic bonding is terminated after complete intimate contact is achieved and while the bond is reversible. The high aluminum content impedes further bond strengthening so that the bond does not become non-reversible via contact bonding. The chamfer provides access near the glass-silicon interface for prying the glass off the silicon to effect debonding without damaging the glass or the silicon. Accordingly, the glass, the silicon, or both may be rebounded (rather than being wastefully disposed).
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: June 9, 2020
    Assignee: ColdQuanta, Inc.
    Inventor: Steven Michael Hughes
  • Patent number: 10580948
    Abstract: A light source module including a substrate, an LED package, an optical cover, and at least one packing layer is provided. The LED package is disposed on the substrate and includes an encapsulant. The optical cover is disposed above the LED package. The at least one packing layer is filled between the LED package and the optical cover.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: March 3, 2020
    Assignee: Lite-On Technology Corporation
    Inventors: Yao-Chi Peng, Tsan-Li Chiu, Po-Chang Li, Ming-Hung Chien
  • Patent number: 10551885
    Abstract: A solid state drive apparatus includes a housing having a first accommodation space and a second accommodation space; a substrate mounted in the first accommodation space, wherein at least one non-volatile memory chip is mounted on the substrate; and a heat dissipation member mounted in the second accommodation space and including an isolation barrier that defines a boundary between the second accommodation space and the first accommodation space and a plurality of fin portions that extend from the isolation barrier away from the first accommodation space, wherein a plurality of through air holes are provided in a side of the housing adjacent the second accommodation space.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: February 4, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jung-Hoon Kim
  • Patent number: 10529638
    Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a molded package body having an upper peripheral edge portion, an air cavity around which the upper peripheral edge portion extends, and a cover piece bonded to the upper peripheral edge portion to enclose the air cavity. The cover piece has a lower peripheral edge portion, which cooperates with the upper peripheral edge portion to define a cover-body interface. The cover-body interface includes an annular channel extending around the cover-body interface, as taken about the package centerline, and first and second hardstop features formed on the upper peripheral edge portion of the molded package body and on the lower peripheral edge portion of the cover piece, respectively. The hardstop features contact to determine a vertical height of the annular channel, as taken along the package centerline.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: January 7, 2020
    Assignee: NXP USA, Inc.
    Inventors: Audel Sanchez, Lakshminarayan Viswanathan, Fernando A. Santos, Jaynal A. Molla
  • Patent number: 10483148
    Abstract: A protective tape including an adhesive agent layer, a thermoplastic resin layer, and a matrix film layer in this order to a surface of a wafer on which a bump electrode is formed; grinding a surface of the wafer opposite to the surface on which the protective tape is pasted; pasting an adhesive tape to the ground surface of the wafer; peeling the protective tape so that the adhesive agent layer remains and other layers are removed; dicing the wafer to which the adhesive tape is pasted to obtain individual semiconductor chips; and curing the adhesive agent layer before dicing; the adhesive agent layer after curing has a shear storage modulus of 3.0E+08 Pa to 5.0E+09 Pa, and the ratio of the thickness of the adhesive agent layer of the protective tape before pasting to the height of the bump electrode is 1/30 to 1/6.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: November 19, 2019
    Assignee: DEXERIALS CORPORATION
    Inventor: Hironobu Moriyama
  • Patent number: 10477301
    Abstract: A surface mount package for a micro-electro-mechanical system (MEMS) microphone die is disclosed. The surface mount package features a substrate with metal pads for surface mounting the package to a device's printed circuit board and for making electrical connections between the microphone package and the device's circuit board. The surface mount microphone package has a cover, and the MEMS microphone die is substrate-mounted and acoustically coupled to an acoustic port provided in the surface mount package. The substrate and the cover are joined together to form the MEMS microphone, and the substrate and cover cooperate to form an acoustic chamber for the substrate-mounted MEMS microphone die.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: November 12, 2019
    Assignee: Knowles Electronics, LLC
    Inventor: Anthony D. Minervini
  • Patent number: 10403588
    Abstract: A fan-out semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of the inactive surface, a first connection member disposed on the active surface and including a redistribution layer and a first via electrically connecting the connection pad to the redistribution layer, a passivation layer disposed on the first connection member, and an under-bump metal layer including an external connection pad disposed on the passivation layer and a second via connecting the external connection pad to the redistribution layer. In a vertical direction, the first and second vias are disposed within the external connection pad and do not overlap each other.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Han Kim, Kyung Moon Jung, Seok Hwan Kim, Kyung Ho Lee, Kang Heon Hur
  • Patent number: 10388685
    Abstract: The present invention provides a portable electronic device and an image-capturing module thereof, and an image-sensing assembly thereof. The image-sensing assembly includes an image-sensing chip, a spacer structure, and a filter element. The image-sensing chip has an image sensing area and a non-image sensing area surrounding the image sensing area. The spacer structure is disposed on the non-image sensing area. The filter element is disposed on the spacer structure so as to separate the filter element from the image-sensing chip by a predetermined distance. The image-sensing assembly can be applied to the image-capturing module, and the image-capturing module can be applied to the portable electronic device.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: August 20, 2019
    Assignee: AZUREWAVE TECHNOLOGIES, INC.
    Inventors: Tseng-Chieh Lee, Kung-An Lin
  • Patent number: 10271433
    Abstract: A method of packaging an electrical device including following steps is provided. A circuit board including a substrate and a first conductive pattern is provided. The electrical device having an electrode is disposed on the circuit board. A dielectric layer is formed on the circuit board to cover the electrical device, the electrode and the first conductive pattern, wherein a first caving pattern is formed in the dielectric layer by the first conductive pattern. The dielectric layer is patterned to form a through hole and a second caving pattern connecting with the through hole and exposing the electrode. A conductive material is filled in the through hole and the second caving pattern to form a conductive via in the through hole and a second conductive pattern in the second caving pattern. The substrate is removed.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: April 23, 2019
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Shu-Sheng Chiang, Tsung-Yuan Chen, Shih-Lian Cheng
  • Patent number: 10199303
    Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a molded package body having an upper peripheral edge portion, an air cavity around which the upper peripheral edge portion extends, and a cover piece bonded to the upper peripheral edge portion to enclose the air cavity. The cover piece has a lower peripheral edge portion, which cooperates with the upper peripheral edge portion to define a cover-body interface. The cover-body interface includes an annular channel extending around the cover-body interface, as taken about the package centerline, and first and second hardstop features formed on the upper peripheral edge portion of the molded package body and on the lower peripheral edge portion of the cover piece, respectively. The hardstop features contact to determine a vertical height of the annular channel, as taken along the package centerline.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: February 5, 2019
    Assignee: NXP USA, INC.
    Inventors: Audel Sanchez, Lakshminarayan Viswanathan, Fernando A. Santos, Jaynal A. Molla
  • Patent number: 10192979
    Abstract: A device having: a substrate having a dielectric surface; a gate electrode; a drain electrode; a source electrode having a conductive contact and a two-dimensional material edge; and a dielectric material between the source and the gate. The source is adjacent to the gate. The drain electrode is not laterally between the edge and the gate electrode, and the distance from the drain electrode to the edge is greater than the distance from the gate electrode to the edge. The edge does not contact any other component of the device. The gate, drain, and source are not in electrical contact with each other. There is a line of sight or electron path from the edge to the drain electrode.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: January 29, 2019
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Jonathan L. Shaw, John Bradley Boos, Kevin Jensen, James G. Champlain, Bradford B. Pate, Byoung-don Kong, Doewon Park, Joan E. Yater
  • Patent number: 10181457
    Abstract: Apparatuses and methods relating generally to a microelectronic package for wafer-level chip scale packaging with fan-out are disclosed. In an apparatus, there is a substrate having an upper surface and a lower surface opposite the upper surface. A microelectronic device is coupled to the upper surface with the microelectronic device in a face-up orientation. Wire bond wires are coupled to and extending away from the upper surface. Posts of the microelectronic device extend away from a front face thereof. Conductive pads are formed in the substrate associated with the wire bond wires for electrical conductivity.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: January 15, 2019
    Assignee: Invensas Corporation
    Inventors: Ashok S. Prabhu, Rajesh Katkar
  • Patent number: 10177084
    Abstract: An object of the invention is to manufacture a semiconductor module small. A metal wire (212) connecting a control electrode (101) and a control terminal (21) rises to form a first angle (?1) from the control electrode (101) toward a first conductive portion (202), gradually goes in substantially parallel to the first conductive portion (202) as the metal wire approaches the first conductive portion (202), and is connected to the control terminal (21) to form a second angle (?2) smaller than the first angle (?1).
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: January 8, 2019
    Assignee: HITACHI, LTD.
    Inventors: Nobutake Tsuyuno, Eiichi Ide
  • Patent number: 10147746
    Abstract: A flexible display device includes a flexible substrate, an adhesion layer disposed on a surface of the flexible substrate, and a plurality of pixel structures in respective pixels on the adhesion layer. Each of the pixel structures on the adhesion layer includes a light emitting diode including an inorganic light emitting layer, and a thin film transistor which is connected to the light emitting diode and switches a state of the light emitting diode.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: December 4, 2018
    Assignees: SAMSUNG DISPLAY CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Kihyun Kim, Taewoong Kim, Jong-hyun Ahn, Wonho Lee, Minwoo Choi
  • Patent number: 10081534
    Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity. The method for forming the cavity further includes forming at least one first vent hole of a first dimension which is sized to avoid or minimize material deposition on a beam structure during sealing processes. The method for forming the cavity further includes forming at least one second vent hole of a second dimension, larger than the first dimension.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: September 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey C. Maling, Anthony K. Stamper, Dana R. DeReus, Arthur S. Morris, III
  • Patent number: 10001418
    Abstract: Embodiments generally relate to device and methods for detecting force. A force sensor may include a sense die, a substrate, one or more sense elements supported by the sense die, one or more electrical contacts located on the sense die and electrically coupled to electrical traces on the substrate, and an actuation element configured to transmit a force to the sense die. The width of the actuation element may be less than the distance between the one or more electrical contacts. In some embodiments, the actuation element may include a thin wedge/plate configured to interact with the sense die at a contact point. The thin wedge/plate may allow use of a smaller sense die and/or may allow closer placement of the one or more sense elements to the contact point and/or may prevent accidental contact with the one or more electrical contacts which may lead to a short circuit.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: June 19, 2018
    Assignee: Honeywell International Inc.
    Inventors: James F. Machir, Jason Dennis Patch
  • Patent number: 9960192
    Abstract: A flexible display device includes a flexible substrate, an adhesion layer disposed on a surface of the flexible substrate, and a plurality of pixel structures in respective pixels on the adhesion layer. Each of the pixel structures on the adhesion layer includes a light emitting diode including an inorganic light emitting layer, and a thin film transistor which is connected to the light emitting diode and switches a state of the light emitting diode.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: May 1, 2018
    Assignees: SAMSUNG DISPLAY CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Kihyun Kim, Taewoong Kim, Jong-hyun Ahn, Wonho Lee, Minwoo Choi
  • Patent number: 9832878
    Abstract: A wiring board with a cavity for a built-in electronic component includes a conductor layer including a conductor circuit layer and a plane layer, and an insulating layer laminated on the conductor layer and having a cavity such that the cavity is forming an exposed portion of the plane layer and formed to mount a built-in electronic component on the exposed portion of the plane layer. The plane layer has a recess structure formed in an outer peripheral portion in the exposed portion of the plane layer.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: November 28, 2017
    Assignee: IBIDEN CO., LTD.
    Inventors: Keisuke Shimizu, Makoto Terui, Ryojiro Tominaga, Yuichi Nakamura
  • Patent number: 9781833
    Abstract: This invention relates to a method for producing an electrical system comprising a support (1) bearing on a first face at least one device; with the device comprising at least one electronic component (2) provided with at least one electrical connector (21, 22), with the method comprising: a step of setting in place of a cover (6) positioned above the component; said cover (6) comprising at least one passage (61, 62) according to a dimension in thickness of the cover (6) in such a way as to form an access space to the at least one electrical connector (21, 22), a step of forming a sealing seam (71) in such a way that the component is encapsulated in a sealed cavity (9) delimited by the first face of the support (1), the first face of the cover (6) and the sealing seam (7).
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: October 3, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Messaoud Bedjaoui, Raphael Salot
  • Patent number: 9773719
    Abstract: In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor chip having a first side and an opposite second side, and a chip contact pad disposed on the first side of the semiconductor chip. A dielectric liner is disposed over the semiconductor chip. The dielectric liner includes a plurality of openings over the chip contact pad. A interconnect contacts the semiconductor chip through the plurality of openings at the chip contact pad.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: September 26, 2017
    Assignee: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventors: Dirk Meinhold, Frank Daeche, Thorsten Scharf
  • Patent number: 9699885
    Abstract: Disclosed herein is a circuit board. According to an exemplary embodiment of the present disclosure, a circuit board has a structure in which at least a portion of a first heat transfer structure in which a metal layer and an insulating layer are alternately stacked is inserted into an insulating part.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: July 4, 2017
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Tae Hong Min, Myung Sam Kang, Young Gwan Ko, Min Jae Seong
  • Patent number: 9688532
    Abstract: A method of manufacturing an electronic device in which a second substrate (functional element) containing silicon and a third substrate (lid body) containing silicon are bonded to a first substrate containing alkali metal ions by anode bonding includes a first process of performing the anode bonding to bond the second substrate to a surface of the first substrate; a second process of removing at least a portion of the surface of the first substrate to which the third substrate is to be bonded by the anode bonding and exposing a bonding surface after the first process; and a third process of performing the anode bonding to bond the third substrate to the bonding surface of the first substrate.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: June 27, 2017
    Assignee: Seiko Epson Corporation
    Inventor: Atsuki Naruse
  • Patent number: 9521319
    Abstract: Systems and methods in accordance with embodiments of the invention implement array cameras and array camera modules that have spectral filters disposed outside of constituent image sensors. In one embodiment, an array camera module includes: a lens stack array including lens elements arranged to form a plurality of optical channels, each optical channel including a field-of-view that is shifted with respect to the fields-of-views of each other optical channel so that each shift includes a sub-pixel shifted view of the scene, a glass substrate located within an optical channel, and a spectral filter disposed within, or else proximate to, a glass substrate within the lens stack array; and an imager array including a plurality of focal planes, where each focal plane includes a plurality of rows of pixels that also form a plurality of columns of pixels, and where each focal plane does not include pixels from another focal plane.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: December 13, 2016
    Assignee: Pelican Imaging Corporation
    Inventors: Errol Mark Rodda, Jacques Duparré
  • Patent number: 9511999
    Abstract: A method for sealing cavities in micro-electronic/-mechanical system (MEMS) devices to provide a controlled atmosphere within the sealed cavity includes providing a semiconductor substrate on which a template is provided on a localized area of the substrate. The template defines the interior shape of the cavity. Holes are made so as to enable venting of the cavity to provide a desired atmosphere to enter into the cavity through the hole. Finally, a sealing material is provided in the hole to seal the cavity. The sealing can be made by compression and/or melting of the sealing material.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: December 6, 2016
    Assignee: SILEX MICROSYSTEMS AB
    Inventors: Thorbjorn Ebefors, Niklas Svedin
  • Patent number: 9515034
    Abstract: A conductive structure is formed in a last metal layer of an integrated circuit. Passivation material is patterned over a portion of the conductive structure. A first trench is patterned around a selected portion of the passivation material. The selected portion represents a bond region of a wire bond to be formed above the passivation material. A portion of the passivation material completely covers a bottom of the trench. A layer of conductive material is conformally deposited over the passivation material. The conformal depositing resulting in a second trench forming in the conductive material over the first trench in the passivation material. The second trench is positioned to contain at least a portion of a splash of the conductive material when the wire bond is subsequently formed.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: December 6, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Sohrab Safai, David B. Clegg, Tu-Anh N. Tran
  • Patent number: 9502380
    Abstract: A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer are provided. In some embodiments, the method is performed by placing an interposer with one or more through-substrate-vias (TSVs) on a first adhesive layer overlying a first carrier substrate. Connection structures are arranged along a first surface of the interposer facing the first adhesive layer. A first molding compound is formed over the first adhesive layer and surrounding the interposer. The first molding compound is arranged to expose the TSVs along a second surface of the interposer. A first redistribution structure is formed over the second surface of the interposer and the first molding compound, and conductive bump structures are formed over the first redistribution structure. A first packaged die is bonded to the conductive bump structures.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Cheng Lin, Shang-Yun Hou
  • Patent number: 9487391
    Abstract: Embodiments of mechanisms for forming a micro-electro mechanical system (MEMS) device are provided. The MEMS device includes a CMOS substrate, a cap substrate, and a MEMS substrate bonded between the CMOS substrate and the cap substrate. The MEMS substrate includes a first movable element and a second movable element. The MEMS device also includes a first closed chamber and a second closed chamber, which are between the MEMS substrate and the cap substrate. The first movable element is in the first closed chamber, and the second movable element is in the second closed chamber. A first pressure of the first closed chamber is higher than a second pressure of the second closed chamber.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: November 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Wen Cheng, Chia-Hua Chu
  • Patent number: 9478499
    Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The semiconductor package structure has a substrate and a die stack of n die(s), wherein n?1. The substrate has a first side, a second side and an opening extending from the first side to the second side. The die stack is disposed in the opening. The thickness of the substrate is substantially the same as the thickness of the die stack.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: October 25, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chien-Li Kuo
  • Patent number: 9418961
    Abstract: An apparatus including a bond head, a supplemental support, a reduction module, and a transducer is provided. The bond head holds a first substrate that contains a first set of metal pads. The supplemental support holds a second substrate that contains a second set of metal pads. The aligner forms an aligned set of metal pads by aligning the first substrate to the second substrate. The reduction module contains the aligned substrates and a reduction gas flows into the reduction module. The transducer provides repeated relative motion to the aligned set of metal pads.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: August 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu
  • Patent number: 9351084
    Abstract: A size of a port hole in a package for a micro-electro-mechanical (MEMS) microphone can be modified to improve performance of the MEMS microphone while protecting the MEMS microphone from environmental interference. As an example, the port hole diameter is increased along a thickness of a substrate coupled to the MEMS microphone to reduce air mass loading and air flow resistance and thus, increase the resonant frequency, resonant peak, signal-to-noise ratio (SNR) and/or a range for flat frequency response of the MEMS microphone. In one aspect, the port hole can be created by mechanical and/or laser drilling. In another aspect, the port hole can be created by forming a cavity in the substrate over a drilled port hole.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: May 24, 2016
    Assignee: INVENSENSE, INC.
    Inventor: Jia Gao
  • Patent number: 9351404
    Abstract: An electronic device comprising a laminate comprising pluralities of insulator layers each provided with conductor patterns, and an amplifier-constituting semiconductor device mounted to a mounting electrode formed on an upper surface of the laminate, a first ground electrode being formed on an insulator layer near an upper surface of the laminate; a second ground electrode being formed on an insulator layer near a lower surface of the laminate; the first ground electrode being connected to the mounting electrode through pluralities of via-holes; conductor patterns constituting the first circuit block being disposed in a region below the amplifier-constituting semiconductor device between the first ground electrode and the second ground electrode; and at least part of a conductor pattern for a line connecting the first circuit block to the amplifier-constituting semiconductor device being disposed on an insulator layer sandwiched by the mounting electrode and the first ground electrode.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: May 24, 2016
    Assignee: HITACHI METALS, LTD.
    Inventor: Hirotaka Satake
  • Patent number: 9318438
    Abstract: A method for selectively removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The method comprises oxidizing a semiconductor structure comprising a substrate and at least one copper feature and removing a portion of the substrate using an etchant comprising SF6 without forming copper sulfide on the at least one copper feature. Additional methods are also disclosed, as well as semiconductor structures produced from such methods.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: April 19, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Mark A. Bossler, Jaspreet S. Gandhi, Christopher J. Gambee, Randall S. Parker
  • Patent number: 9305885
    Abstract: A multi-chip package structure is provided, including a substrate having a grounding structure; two semiconductor elements disposed on and electrically connected to the substrate; an encapsulant formed on the substrate and encapsulating semiconductor elements, wherein the encapsulant has a plurality of round holes formed between the semiconductor elements; and an electromagnetic shielding structure formed in each of the round holes and connected to the grounding structure to achieve electromagnetic shielding effects. A method for forming the multi-chip package is also provided.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: April 5, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Tai-Tsung Hsu, Cheng-Yu Chiang, Miao-Wen Chen, Wen-Jung Chiang, Hsin-Hung Lee
  • Patent number: 9287140
    Abstract: Provided are semiconductor packages having through electrodes and methods of fabricating the same. The method may include may include forming a wafer-level package including first semiconductor chips stacked on a second semiconductor chip, forming a chip-level package including fourth semiconductor chips stacked on a third semiconductor chip stacking a plurality of the chip-level packages on a back surface of the second semiconductor substrate of the wafer-level package, polishing the first mold layer of the wafer-level package and the first semiconductor chips to expose a first through electrodes of the first semiconductor chip, and forming outer electrodes on the polished first semiconductor chips to be connected to the first through electrodes, respectively.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: March 15, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyunsoo Chung, Jongyeon Kim, In-Young Lee, Tae-Je Cho
  • Patent number: 9260296
    Abstract: A method embodiment includes providing a micro-electromechanical (MEMS) wafer including a polysilicon layer having a first and a second portion. A carrier wafer is bonded to a first surface of the MEMS wafer. Bonding the carrier wafer creates a first cavity. A first surface of the first portion of the polysilicon layer is exposed to a pressure level of the first cavity. A cap wafer is bonded to a second surface of the MEMS wafer opposite the first surface of the MEMS wafer. The bonding the cap wafer creates a second cavity comprising the second portion of the polysilicon layer and a third cavity. A second surface of the first portion of the polysilicon layer is exposed to a pressure level of the third cavity. The first cavity or the third cavity is exposed to an ambient environment.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hua Chu, Chun-Wen Cheng
  • Patent number: 9232657
    Abstract: A wiring substrate includes a core, first and second wiring layers formed on opposite sides of the core, an electronic component arranged in a cavity of the core, and a first insulating layer that fills the cavity and covers the one surface of the core. The electronic component is partially buried in the first insulating layer and partially projected from the cavity and exposed from the first insulating layer. A second insulating layer covers the first insulating layer. A third insulating layer covers the core and the projected and exposed portion of the electronic component. The thickness of the third insulating layer where the first wiring layer is located is equal to the total thickness of the first insulating layer and the second insulating layer where the second wiring layer is located.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: January 5, 2016
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Takayuki Kiwanami, Junji Sato, Katsuya Fukase
  • Patent number: 9209151
    Abstract: A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: December 8, 2015
    Assignee: General Electric Company
    Inventors: Shakti Singh Chauhan, Paul Alan McConnelee, Arun Virupaksha Gowda
  • Patent number: 9190355
    Abstract: A sub-assembly for a packaged integrated circuit (IC) device has a planar substrate. The substrate's top side has multiple sets electrically connected bond posts arranged in corresponding nested contour zones. Each contour zone includes a different bond post of each bond-post set. The bottom side has a different set of pad connectors electrically connected to the each top-side bond-post set. The sub-assembly can be used for different IC packages having IC dies of different sizes, with different contours of bond posts available for electrical connection depending on the size of the IC die.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: November 17, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Weng Hoong Chan, Ly Hoon Khoo, Boon Yew Low, Navas Khan Oratti Kalandar