Abstract: A semiconductor module is manufactured by bonding a resin case having a first opening through which surfaces of main circuit terminals and control terminals are exposed, onto a metal heat-dissipating substrate onto which is bonded, a conductive-patterned insulating substrate onto which are bonded, semiconductor chips, the main circuit terminals, and the control terminals; inserting into and attaching to a second opening formed on a side wall constituting a resin case, a resin body having a nut embedded therein to fix the main circuit terminals and the control terminals; and filling the resin case with a resin material. A side wall of the first opening is tapered toward the surface thereof; a tapered contact portion contacting the tapered side wall is disposed on the control terminal; and the resin body having the embedded nut fixes the control terminal having a one-footing structure that is an independent terminal.

Abstract: A semiconductor light emitting element includes a semiconductor stack part that includes a light emitting layer, a diffractive face that light emitted from the light emitting layer is incident to, convex portions or concave portions formed in a period which is longer than an optical wavelength of the light and is shorter than a coherent length of the light, wherein the diffractive face reflects incident light in multimode according to Bragg's condition of diffraction and transmits the incident light in multimode according to the Bragg's condition of diffraction, and a reflective face which reflects multimode light diffracted at the diffractive face and let the multimode light be incident to the diffractive face again. The semiconductor stack part is formed on the diffractive face.

Abstract: Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a microelectronic device includes attaching a microelectronic die to a support member by forming an attachment feature on at least one of a back side of the microelectronic die and the support member. The attachment feature includes a volume of solder material. The method also includes contacting the attachment feature with the other of the microelectronic die and the support member, and reflowing the solder material to join the back side of the die and the support member via the attachment feature. In several embodiments, the attachment feature is not electrically connected to internal active structures of the die.

Abstract: A semiconductor device, includes: a connection member including a first pad formed on a principal surface thereof; a semiconductor chip including a circuit-formed surface on which a second pad is formed, the chip mounted on the connection member so that the circuit-formed surface faces the principal surface; and a solder bump that connects the first and second pads and is made of metal containing Bi and Sn, wherein the bump includes a first interface-layer formed adjacent to the second pad, a second interface-layer formed adjacent to the first pad, a first intermediate region formed adjacent to either one of the interface-layers, and a second intermediate region formed adjacent to the other one of the interface-layers and formed adjacent to the first intermediate region; Bi-concentration in the first intermediate region is higher than a Sn-concentration; and a Sn-concentration in the second intermediate region is higher than a Bi-concentration.

Abstract: The formation of the conductive wire of a chip package consists of a plurality of steps. Coat a first dielectric layer on the pad-mounting surface and a slot is formed on each bonding pad correspondingly. Then coat a second dielectric layer and produce a wiring slot corresponding to each bonding pad and the slot thereof. Next each wiring slot is filled with electrically conductive metal so as to form a conductive wire. Later Coat a third dielectric layer and a corresponding slot is formed on one end of each conductive wire while this slot is filled with electrically conductive metal to form a solder point. The above steps can further be repeated so as to form an upper-layer and a lower-layer conductive wire. Thereby precision of the chip package, use efficiency of the wafer and yield rate of manufacturing processes are all improved.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a trench; mounting an integrated circuit device on the leadframe; forming a top encapsulation on the leadframe and the trench; forming a lead having a lead protrusion and a peripheral groove, the lead protrusion and the peripheral groove formed from etching the trench at a leadframe bottom side; and forming a bottom encapsulation surrounding a lead bottom side of the lead.

Abstract: A compound carrier board structure of Flip-Chip Chip-Scale Package and manufacturing method thereof provides a baseplate having a flip region with a through-opening and bonding to a Non-conductive Film to bond to a carrier board in order to form a compound carrier board structure. Therefore, when a die is planted in the film region of the carrier board structure, the carrier board is able to susceptible to different stresses during a package process. The baseplate uses the low Thermal Expansion Coefficient material to avoid warpage problems caused by the thermal expansion of the carrier board resulting from the thermal stresses. The carrier board is able to disperse conduction of thermal stresses by the baseplate in order to strengthen cooling effect of the compound carrier board structure. Thus, the present invention achieves miniaturization and heat strengthening and enhances the mechanical strength.

Abstract: A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.

Abstract: An integrated circuit package includes a packaging substrate, which has an electrically conductive grid formed on a dielectric layer, and an integrated circuit die electrically coupled to the electrically conductive grid at one or more locations. In this embodiment, the electrically conductive grid includes a plurality of electrically conductive portions, wherein each portion is electrically coupled to at least one other portion, and a plurality of void regions that are electrically non-contiguous and substantially free of electrically conductive material. One advantage of the integrated circuit package is that a packaging substrate that is reduced in thickness, and therefore rigidity, can still maintain planarity during operation.

Abstract: Electronic assemblies including substrates and their manufacture are described. One assembly includes a die embedded in a dielectric layer in a multilayer substrate, and a dielectric region embedded in the dielectric layer in the multilayer substrate. The multilayer substrate includes a die side and a land side, with the first dielectric region and the dielectric layer extending to the die side. A plurality of vias are positioned within the first dielectric region, the vias extending to pads on the die side. Other embodiments are described and claimed.

Abstract: A semiconductor device has a substrate with a die attach area. A conductive layer is formed over a surface of the substrate and extending below the surface. An insulating layer is formed over the surface of the substrate outside the die attach area. A portion of the conductive layer is removed within the die attach area to expose sidewalls of the substrate. The remaining portion of the conductive layer is recessed below the surface of the substrate within the die attach area. A semiconductor die has bumps formed over its active surface. The semiconductor die is mounted to the substrate by bonding the bumps to the remaining portion of the first conductive layer recessed below the first surface of the substrate. The sidewalls of the substrate retain the bumps during bonding to the remaining portion of the conductive layer. An encapsulant is deposited between the semiconductor die and substrate.

Abstract: A semiconductor device has an insulation substrate formed with a conductive pattern; an independent terminal, which is an externally leading terminal, soldered to the conductive pattern of the insulation substrate; a case disposed over the insulation substrate such that a top surface of the independent terminal is exposed; an opening provided on a side surface of the case; a nut glove inserted from the opening so as to be below the independent terminal, and fix the independent terminal; and a first projection part formed on a side surface of the nut glove, and having tapers in a frontward direction and a rearward direction of insertion of the nut glove, respectively. The rearward taper of the first projection part is pressure contacting with a sidewall surface of the opening.

Abstract: A method of making an electronic device includes forming an electrically conductive pattern on a substrate, forming a cover layer on the substrate and the electrically conductive pattern, and forming openings in the cover layer and being aligned with the electrically conductive pattern. The method also includes positioning an IC on the cover layer so that bond pads of the IC are aligned with the openings, and heating under pressure the cover layer to both mechanically secure and electrically interconnect the IC.

Abstract: A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad. A method of forming a surface mounting component or a chip scale package assembly wherein the component or assembly has at least two different types of solder bumps.

Abstract: A connector for connection to terminals of an integrated circuit. The connector consists of a dielectric substrate having a first side and a second side. The connector has wire bond terminals which are attached to the first side of the substrate and configured to receive wire bonds connected to a first set of the terminals of the integrated circuit. The connector also has solder bump terminals, attached to the second side of the substrate so as to be insulated from the wire bond terminals, the solder bump terminals being configured to be coupled via solder balls with a second set of the terminals of the integrated circuit.

Abstract: A method of packaging includes placing a package component over a release film, wherein solder balls on a surface of the package component are in physical contact with the release film. Next, A molding compound filled between the release film and the package component is cured, wherein during the step of curing, the solder balls remain in physical contact with the release film.

Abstract: A MEMS device (40) includes a base structure (42) and a microstructure (44) suspended above the structure (42). The base structure (42) includes an oxide layer (50) formed on a substrate (48), a structural layer (54) formed on the oxide layer (50), and an insulating layer (56) formed over the structural layer (54). A sacrificial layer (112) is formed overlying the base structure (42), and the microstructure (44) is formed in another structural layer (116) over the sacrificial layer (112). Methodology (90) entails removing the sacrificial layer (112) and a portion of the oxide layer (50) to release the microstructure (44) and to expose a top surface (52) of the substrate (48). Following removal, a width (86) of a gap (80) produced between the microstructure (44) and the top surface (52) is greater than a width (88) of a gap (84) produced between the microstructure (44) and the structural layer (54).

Abstract: Various semiconductor chip package substrates with reinforcement and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a package substrate that has a first side and a second side opposite to the first side. The first side has a central area adapted to receive a semiconductor chip. A solder reinforcement structure is formed on the first side of the package substrate outside of the central area to resist bending of the package substrate.

Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a dielectric core having an embedded pad; a top solder resist layer on the dielectric core, a pad top surface of the embedded pad below the top solder resist layer; a device interconnect attached to the embedded pad; and an integrated circuit device having an interconnect pillar, the interconnect pillar attached to the device interconnect for mounting the integrated circuit device to the dielectric core.

Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.

Abstract: Methods of forming conductive materials on contact pads for semiconductor devices and packages. Substrate is provided with contact pads formed thereon. Conductive material is formed over the contact pads by a depositing process followed by a heating process to alter the chemical properties of the conductive material. Optionally, a dispersing process may be incorporated. An interconnect structure can be mounted over the conductive material where the interconnect structure is attached to the conductive material without any active treatment to the conductive material after formation.

Abstract: A power module substrate includes: a ceramics substrate having a surface; and a metal plate connected to the surface of the ceramics substrate, composed of aluminum, and including Cu at a joint interface between the ceramics substrate and the metal plate, wherein a Cu concentration at the joint interface is in the range of 0.05 to 5 wt %.

Abstract: An integrated circuit (IC) package is disclosed comprising a substrate including a plurality of substrate contacts; a semiconductor die including a plurality of die contacts; and a plurality of conductors for providing direct connections between substrate contacts and die contacts, respectively. By having the conductors directly route the connections between the die contacts and substrate contacts, many improvements may be realized including, but not limited to, improved package routing capabilities, reduced die and/or package size, improved package reliability, improved current handling capacity, improved speed, improved thermal performance, and lower costs.

Abstract: First electrode pads formed on one semiconductor package surface include a first reinforcing electrode pad having a surface area larger than that of other first electrode pads. Second electrode pads formed on a printed wiring board on which the semiconductor package is mounted include at least one second reinforcing electrode pad. The second reinforcing electrode pad opposes the first reinforcing electrode pad, and has a surface area greater than that of the other second electrode pads. The first and second electrode pads are connected by solder connection parts. A cylindrical enclosing member encloses an outer perimeter of a solder connection part connecting the first and second reinforcing electrode pads. Increases in the amount of warping of semiconductor devices such as the package substrate and the printed wiring board are suppressed, and the development of solder bridges with respect to adjacent solder connecting parts or adjacent components is reduced.

Abstract: A method comprises forming semiconductor flip chip interconnects having electrical connecting pads and electrically conductive posts terminating in distal ends operatively associated with the pads. We solder bump the distal ends by injection molding, mask the posts on the pads with a mask having a plurality of through hole reservoirs and align the reservoirs in the mask to be substantially concentric with the distal ends. Injecting liquid solder into the reservoirs and allowing it to cool provides solidified solder on the distal ends, which after mask removal produces a solder bumped substrate which we position on a wafer to leave a gap between the wafer and the substrate. The wafer has electrically conductive sites on the surface for soldering to the posts. Abutting the sites and the solder bumped posts followed by heating joins the wafer and substrate. The gap is optionally filled with a material comprising an underfill.

Abstract: A semiconductor module is produced by providing a circuit carrier having a metallization, an electrically conductive wire and a bonding device. With the aid of the bonding device, a bonding connection is produced between the metallization and a first section of the wire. A separating location and a second section of the wire, the second section being spaced apart from the separating location, are defined on the wire. The wire is reshaped in the second section. Before or after reshaping, the wire is severed at the separating location, such that a terminal conductor of the semiconductor module is formed from a part of the wire. The terminal conductor is bonded to the metallization and having a free end at the separating location.

Abstract: An electronic device includes: a vibrator disposed within a cavity on a substrate and electrically driven; an enclosure wall which has electric conductivity and sections the cavity from an insulation layer surrounding the circumference of the cavity; a first wiring and a second wiring which connect with the vibrator and penetrate the enclosure wall; and a liquid flow preventing portion disposed at the position where the first wiring and the second wiring penetrate the enclosure wall to prevent flow of etchant dissolving the insulation layer from the cavity toward the insulation layer and insulate the first wiring and the second wiring from the enclosure wall.

Abstract: A method and structure for stabilizing an array of micro devices is disclosed. The array of micro devices is formed on an array of stabilization posts formed from a thermoset material. Each micro device includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface.

Abstract: When a conductive post is bonded to a bonding target member such as a semiconductor chip or an insulating substrate with conductive patterns by using metal nanoparticles, a strong bonding layer can be obtained by forming a bottom surface of the distal end of the conductive post in a concave shape.

Abstract: A method of attaching a chip to the substrate with an outer layer comprising via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method comprising the steps of: (o) optionally removing organic varnish, (p) positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and (q) applying heat to melt the solder bumps and to wet the ends of the vias with solder.

Abstract: A semiconductor package includes a baseplate having a die attach region and a peripheral region, a transistor die having a first terminal attached to the die attach region, and a second terminal and a third terminal facing away from the baseplate, and a frame including an electrically insulative member having a first side attached to the peripheral region of the baseplate, a second side facing away from the baseplate, a first metallization at the first side of the insulative member and a second metallization at the second side of the insulative member. The insulative member extends outward beyond a lateral sidewall of the baseplate. The first metallization is attached to the part of the first side which extends outward beyond the lateral sidewall of the baseplate. The first and second metallizations are electrically connected at a region of the insulative member spaced apart from the lateral sidewall of the baseplate.

Abstract: A structure includes a thermal interface material, and a Perforated Foil Sheet (PFS) including through-openings therein, with a first portion of the PFS embedded in the thermal interface material. An upper layer of the thermal interface material is overlying the PFS, and a lower layer of thermal interface material is underlying the PFS. The thermal interface material fills through-openings in the PFS.

Abstract: A method for making an electronic package structure is provided which comprises: providing a substrate; providing an inductor module; assembling the inductor module and the substrate so that they define a space; injecting package glue into the space defined by the inductor module and the substrate so as to form a package layer.

Abstract: In accordance with one or more embodiments, a semiconductor device comprises a semiconductor die having a heat region disposed on at least one portion of the semiconductor die, and a diamond substrate disposed proximate to the semiconductor die, wherein the diamond substrate is capable of dissipating heat from the diamond substrate via at least one or more bumps coupling the diamond substrate to the heat region of the semiconductor die.

Abstract: Methods and devices for packaging integrated circuits. A packaged device may include an integrated circuit, a first packaging component including a patterned surface, and a second packaging component. The patterned surface of the first packaging component may be adhesively coupled to a surface of the second packaging component or a surface of the integrated circuit. The integrated circuit may be at least partially enclosed between the first and second packaging components. A packaging method may include patterning a surface of a packaging component of an integrated circuit package. The surface of the packaging component may be for adhesively coupling to a second component to at least partially enclose an integrated circuit in the integrated circuit package.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands.

Abstract: A microelectronic package is provided. The microelectronic package includes a substrate having a plurality of solder bumps disposed on a top side of the substrate and a die disposed adjacent to the top side of the substrate. The die includes a plurality of glassy metal bumps disposed on a bottom side of the die wherein the plurality of glassy metal bumps are to melt the plurality of solder bumps to form a liquid solder layer. The liquid solder layer is to attach the die with the substrate.

Abstract: A multi-chip electronic package and methods of manufacture are provided. The method includes contacting pistons of a lid with respective ones of chips on a chip carrier. The method further includes separating the lid and the chip carrier and placing at least one seal shim on one of the lid and chip carrier. The at least one seal shim has a thickness that results in a gap between the pistons with the respective ones of the chips on the chip carrier. The method further includes dispensing thermal interface material within the gap and in contact with the chips. The method further includes sealing the lid to the chip carrier with the at least one seal shim between the lid and the chip carrier.

Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.

Abstract: A chip package includes a substrate, a pad positioned on the substrate, a base board, at least one adhesive layer and at least one chip. The base board is positioned on the pad. At least one mounting hole is defined through the base board. The at least one adhesive layer is received in the at least one mounting hole. The at least one chip is received in the at least one mounting hole and adhere to the pad via the at least one adhesive layer.

Abstract: A radio frequency switch includes a first transmission line, a second transmission line, a first electrode electrically coupled to the first transmission line, a second electrode electrically coupled to the second transmission line, and a phase change material, the first transmission line coupled to a first area of the phase change material and the second transmission line coupled to a second area of the phase change material. When a direct current is sent from the first electrode to the second electrode through the phase change material, the phase change material changes state from a high resistance state to a low resistance state allowing transmission from the first transmission line to the second transmission line. The radio frequency switch is integrated on a substrate.

Abstract: A semiconductor package includes a substrate, an RF semiconductor die attached to a first side of the substrate, a capacitor attached to the first side of the substrate, and a first terminal on the first side of the substrate. The semiconductor package further includes copper or aluminum bonding wires or ribbons connecting the first terminal to an output of the RF semiconductor die, and gold bonding wires or ribbons connecting the capacitor to the output of the RF semiconductor die. The gold bonding wires or ribbons are designed to accommodate greater RF Joule heating during operation of the RF semiconductor die than the copper or aluminum bonding wires or ribbons. Corresponding methods of manufacturing are also described.

Abstract: A semiconductor chip (1) is flip-chip mounted on a circuit board (4) with an underfill resin (6) interposed between the semiconductor chip (1) and the circuit board (4) and a container covering the semiconductor chip (1) is bonded on the circuit board (4). At this point, the semiconductor chip (1) positioned with the underfill resin (6) interposed between the circuit board (4) and the semiconductor chip (1) is pressed and heated by a pressure-bonding tool (8); meanwhile, the surface of the underfill resin (6) protruding around the semiconductor chip (1) is pressed by the pressure-bonding tool (8) through a film (13) on which a surface unevenness is formed in a periodically repeating pattern, so that a surface unevenness (16a) is formed. The inner surface of the container covering the semiconductor chip (1) is bonded to the surface unevenness (16a) on the surface of the underfill resin.

Abstract: Disclosed is a method for fabricating a semiconductor package, including providing a package unit having an insulating layer and at least a semiconductor element embedded into the insulating layer, wherein the semiconductor element is exposed from the insulting layer and a plurality of recessed portions formed in the insulating layer; and electrically connecting a redistribution structure to the semiconductor element. The formation of the recessed portions release the stress of the insulating layer and prevent warpage of the insulating layer from taking place.

Abstract: An electronic component includes: a substrate formed of ceramic and including one or more pads on an upper surface thereof; a component flip-chip mounted on the upper surface of the substrate with one or more bumps bonded to the one or more pads; and an additional film located on a lower surface of the substrate and overlapping with at least a part of a smaller one of the pad and the bump in each of one or more pad/bump pairs, the one or more pad/bump pairs being composed of the one or more pads and the one or more bumps bonded to each other.

Abstract: An integrated circuit package includes an interposer and an integrated circuit die. The interposer is formed from a layer of semiconductor material that is separated from a bulk portion of a semiconductor substrate, and the integrated circuit die is coupled to the interposer. Vias in the interposer can be formed in the thin layer of semiconductor material removed from the semiconductor substrate, and therefore can be scaled down significantly in size. Such reduced-size, through-interposer vias can be etched and filled much more cost-effectively and result in greatly reduced parasitic capacitance in the integrated circuit package.

Abstract: An integrated circuit package includes an integrated circuit package comprising an interposer and an integrated circuit die. The interposer is formed from a silicon-on-insulator semiconductor substrate and includes a plurality of through-silicon vias, and the integrated circuit die is electrically coupled to a first through-silicon via included in the plurality of through-silicon vias. Through-silicon vias in the integrated circuit package can be formed in the thin silicon surface layer of the silicon-on-insulator substrate, and therefore can be scaled down significantly in size. Such reduced-size through-silicon vias can be etched and filled much more cost-effectively and result in greatly reduced parasitic capacitance in the integrated circuit package.

Abstract: An integrated circuit package includes an electronic sensor protected by a lid structure. The electronic sensor includes a transducer placed on a backside surface of a lead frame assembly. The lid structure is placed over the transducer and is attached to the lead frame assembly on the backside surface. The lid can define an air cavity around the transducer, such that mold compound, gel, or other protective chemical material is not placed in contact with the transducer. The transducer is therefore protected without a chemical protectant, lowering the cost of the integrated circuit package and maintaining the sensitivity and performance of the transducer.

Abstract: A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform.

Abstract: A chip package including a chip having an upper surface, a lower surface and a sidewall is provided. The chip includes a signal pad region adjacent to the upper surface. A first recess extends from the upper surface toward the lower surface along the sidewall. At least one second recess extends from a first bottom of the first recess toward the lower surface. The first and second recesses further laterally extend along a side of the upper surface, and a length of the first recess extending along the side is greater than that of the second recess extending along the side. A redistribution layer is electrically connected to the signal pad region and extends into the second recess. A method for forming the chip package is also provided.