Abstract: A package structure is provided. The package structure includes a semiconductor die over a redistribution structure, bonding elements below the redistribution structure, and an underfill layer surrounding the bonding elements and the redistribution structure. The semiconductor die has a rectangular profile in a plan view. A pitch of the bonding elements is defined as the sum of a diameter of the bonding elements and a spacing between neighboring two of the bonding elements. A first circular area of the redistribution structure is entirely covered and in direct contact with the underfill layer. The center of the first circular area is aligned with a first corner of the rectangular profile of the semiconductor die. A diameter of the first circular area is greater than twice the pitch of the bonding elements.

Abstract: A semiconductor module includes a power electronics carrier including a structured metallization layer disposed on an electrically insulating substrate, a power semiconductor die mounted on the power electronics carrier, a housing that surrounds an interior volume over the power electronics carrier, a reinforcing structure contained within the interior volume and including a textured surface that is accessible by fluid, a volume of curable encapsulant disposed within the interior volume and encapsulating the power semiconductor die, wherein the reinforcing structure is embedded within the volume of curable encapsulant such that the textured surface adheres to the encapsulant, and wherein the reinforcing structure has a tensile strength that is greater than a tensile strength of the curable encapsulant.

Abstract: A substrate treating method includes moving a first component of a substrate treatment device to a preset position in response to a treating process of the substrate treatment device, detecting, by a plurality of position detection sensors, a position of the first component, vision-testing, by a vision sensor, a positional state of the first component, and determining an operational state of an error in the detection of the plurality of position detection sensors or a malfunction of the substrate treatment device based on a detection result obtained by the plurality of position detection sensor and a test result obtained by the vision sensor.

Abstract: A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.

Abstract: An integrated circuit package includes a package structure including a plurality of first dies, a second redistribution structure, a second die and a second encapsulant. The package structure includes the first dies, a first encapsulant encapsulating the first dies, a first redistribution structure over the first encapsulant and a plurality of conductive pillars over the first redistribution structure. The second redistribution structure is disposed over the package structure, and electrically connected to the package structure through the conductive pillars. The second die is disposed between the conductive pillars and electrically connected to the second redistribution structure, wherein a first surface of the second die is substantially flush with a surface of the first redistribution structure and a second surface opposite to the first surface of the second die is substantially flush with a surface of the second redistribution structure.

Abstract: By interposing a hard mask between a dielectric and photo-sensitive material it is possible to form fine via in the dielectric by dry etching without damaging the remaining surface of the dielectric.

Abstract: A semiconductor package includes a lower redistribution layer having a plurality of lower ball pads forming a plurality of lower ball pad groups, a semiconductor chip on the lower redistribution layer, an expanded layer surrounding the semiconductor chip on the lower redistribution layer, and an upper redistribution layer on the semiconductor chip and the expanded layer and having a plurality of upper ball pads forming a plurality of upper ball pad groups. The number of the plurality of upper ball pad groups may be the same as the number of the of the plurality lower ball pad groups. Each of the upper ball pads in one of the plurality of upper ball pad groups, from among the plurality of upper ball pads, may be a dummy ball pad.

Abstract: A base substrate, high-k substrate layers on the base substrate with discrete decoupling capacitors embedded, high density substrate layers on the high-k substrate layers supporting wiring and wiring spacing of less than 2 up to about 10 micron width, pitch connectivity between the upper surface of the base substrate and a lower surface of the set of high density substrate layers supports less than 50 up to about 300 micron pitch, the pitch connectivity on an upper surface of the set of high density substrate layers supports less than about 150 micron pitch. A method including attaching a set of metal posts at each contact on a lower surface of a set of high density substrate layers, attaching to a handler, attaching an interconnect layer to a base substrate, and attaching the set of high density substrate layers to the base substrate while aligning each metal post with a contact.

Abstract: A semiconductor apparatus includes a semiconductor element unit comprising one or more semiconductor elements, a packaging substrate, and a motherboard. The packaging substrate, connected to the semiconductor elements, includes a core layer and an upper layer disposed on the core layer. The core layer includes a glass substrate, a core via, and a core distribution layer. The glass substrate having a first surface and a second surface facing each other. A part of the core distribution layer connects electrically conductive layers of the first surface and an electrically conductive layer of the second surface through the core via penetrating through the glass substrate. A thickness of a thinner one among electrically conductive layers of the core distribution layer is the same as or greater than a width of a thinner one among the electrically conductive layers of the upper layer.

Abstract: A method for forming a protective film on an electronic module includes: placing the electronic module and a protective material placed on the electronic module in a chamber; performing a first heating procedure on the protective material in the chamber, and performing a first pressure boosting procedure, wherein a pressure in the first pressure boosting procedure is greater than 1 atmosphere; after softening the protective material, maintaining the first heating procedure, and performing an oscillating decompression procedure on the chamber, wherein the oscillating decompression procedure includes alternately changing pressures in the chamber between multiple low pressures less than 1 atmosphere; maintaining the first heating procedure, and performing a second pressure boosting procedure on the chamber, wherein a pressure in the second boosting procedure is less than that of the first boosting procedure and greater than 1 atmosphere; and performing a second heating procedure on the protective material in the

Abstract: Apparatus and method for tool mark free stich bonding. In some embodiments, a method for wire bonding can include feeding a wire through a capillary tip and attaching a first end of the wire to a first location, thereby forming a ball bond. The method can further include moving the capillary tip towards a second location while the wire feeds out of the capillary tip. The method can further include attaching a second end of the wire to the second location while preventing contact between the capillary tip and the second location, thereby forming a stitch bond without a tool mark at the second location.

Abstract: Disclosed is a semiconductor package comprising an interposer substrate having first and second surfaces opposite each other and including a wiring layer adjacent to the first surface, a semiconductor chip on the first surface of the interposer substrate, a passivation layer on the first surface of the interposer substrate and covering the semiconductor chip, and redistribution patterns in the passivation layer and connected to the semiconductor chip. The semiconductor chip has third and fourth surfaces opposite to each other. The third surface of the semiconductor chip faces the first surface of the interposer substrate. The redistribution patterns are connected to the fourth surface of the semiconductor chip. The semiconductor chip includes chip pads adjacent to the third surface and chip through electrodes connected to the chip pads. Each of the chip pads is directly bonded to a corresponding one of wiring patterns in the wiring layer.

Abstract: A passivation layer and conductive via are provided, wherein the transmittance of an imaging energy is increased within the material of the passivation layer. The increase in transmittance allows for a greater cross-linking that helps to increase control over the contours of openings formed within the passivation layer. Once the openings are formed, the conductive vias can be formed within the openings.

Abstract: A chip package structure is provided. The chip package structure includes a substrate. The chip package structure also includes a first chip structure and a second chip structure over the substrate. The chip package structure further includes an anti-warpage bar between the first chip structure and the second chip structure. In addition, the chip package structure includes an underfill layer between the first chip structure and the second chip structure and between the anti-warpage bar and the substrate. A topmost surface of the underfill layer is lower than a top surface of the anti-warpage bar.

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

Abstract: A semiconductor package includes a substrate having a top planar surface and a semiconductor die mounted on the top planar surface of the substrate. Bond wires electrically connect the semiconductor die to the substrate. Flow control dams are integrally formed with the top planar surface of the substrate and each flow control dam protrudes from the top planar surface of the substrate at a location proximate to the bond wires. The flow control dams reduce the occurrence of wire sweep in the bond wires electrically connected to the substrate and semiconductor die.

Abstract: Multiple (multi-) die integrated circuit (IC) packages for supporting higher connection density, and related fabrication methods. The multi-die IC package includes split dies that provided in respective die packages that are stacked on top of each other to conserve package area. To support signal routing, including through-package signal routing that extends through the die package, each die package includes vertical interconnects disposed adjacent to their respective dies and coupled to a respective package substrate (and interposer substrate if provided) in the package substrate. In this manner, as an example, through-silicon-vias (TSVs) are not required to be fabricated in the multi-die IC package that extend through the dies themselves to provide signal routing between the respective die packages. In another example, space created between adjacent interposer substrates of stacked die packages, as stood off from each other through the interconnect bumps, provides an area for heat dissipation.

Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.

Abstract: An electronic device structure and a method for making an electronic device. As non-limiting examples, various aspects of this disclosure provide a method of manufacturing an electronic device that comprises the utilization of a carrier assisted substrate, and an electronic device manufactured thereby.

Abstract: A semiconductor package includes a substrate, a first semiconductor device disposed over the substrate in an offset position toward an edge of the substrate, and a ring structure disposed over the substrate and surrounding the first semiconductor device. The ring structure includes an overhang portion cantilevered over the edge of the substrate.

Abstract: An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.

Abstract: A semiconductor device package and a method for manufacturing the semiconductor device package are provided. The semiconductor device package includes a first substrate, a second substrate disposed over the first substrate and having a first surface facing away from the first substrate and a second surface facing the first substrate, a first component disposed on the first surface of the second substrate, a second component disposed on the second surface of the second substrate; and a support member covering the first component.

Abstract: A sensor module includes: a substrate including a first terminal and a second terminal; a first conductive bonding member having a first melting point and a first Young's modulus; a lead bonded to the first terminal by the first conductive bonding member; a second conductive bonding member having a second melting point lower than the first melting point and a second Young's modulus higher than the first Young's modulus; and an inertial sensor bonded to the second terminal by the second conductive bonding member.

Abstract: An embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die, a second package bonded to the first package with a first set of conductive connectors, the second package comprising a second die, and an underfill between the first package and the second package and surrounding the first set of conductive connectors, the underfill having a first portion extending up along a sidewall of the second package, the first portion having a first sidewall, the first sidewall having a curved portion and a planar portion.

Abstract: A method of manufacturing a semiconductor device includes: providing a silicon carbide substrate that includes device regions and a grid-shaped kerf region laterally separating the device regions; forming a mold structure on a backside surface of the grid-shaped kerf region; forming backside metal structures on a backside surface of the device regions; and separating the device regions, wherein parts of the mold structure form frame structures laterally surrounding the backside metal structures.

Abstract: A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.

Abstract: A method includes coating a release film over a carrier. The carrier includes a first material having a first Coefficient of Thermal Expansion (CTE), and a second material having a second CTE different from the first CTE. The method further includes placing a device die over the release film, encapsulating the device die in an encapsulant, and planarizing the encapsulant until the device die is revealed.

Abstract: A semiconductor package is disclosed. The semiconductor package includes a back-side wiring substrate and a front-side redistribution layer which are in parallel, and a connector, a semiconductor chip and an encapsulator which are between the back-side wiring substrate and the front-side redistribution layer. The encapsulator surrounds surfaces of the connector and the semiconductor chip. The back-side wiring substrate includes a core layer, a back-side via plug extending through the core layer, and a back-side redistribution layer on the back-side via plug.

Abstract: A resin applying machine includes a processing chamber, a temperature measuring unit, and a controller. The processing chamber houses therein a holder for holding the wafer, a table that faces the holder, a resin supply unit for supplying a liquid resin to the table, a moving unit for relatively moving the holder and the table closely to each other, and a hardening unit for hardening the liquid resin that has coated the wafer. The temperature measuring unit measures a temperature in the processing chamber. The controller includes a correlation data storage unit for recording therein correlation data with respect to the temperature in the processing chamber and a moved distance by which the holder and the table are relatively moved by the moving unit at the temperature.

Abstract: In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.

Abstract: A frame member for an electron beam lithography device of the present disclosure includes a frame body comprising sapphire or aluminum oxide-based ceramics having an open porosity of 0.2% or less and a conductive film disposed at least on a main surface of an electron gun side of the frame body.

Abstract: Disclosed are apparatuses and methods for fabricating the apparatuses. In one aspect, an apparatus includes a high-power die mounted on a backside of a package substrate. A heat transfer layer is disposed on the backside of the high-power die. A plurality of heat sink interconnects is coupled to the heat transfer layer, where each of the plurality of heat sink interconnects is directly coupled to the heat transfer layer in a vertical orientation.

Abstract: Device, package structure and method of forming the same are disclosed. The device includes a die encapsulated by an encapsulant, a conductive structure aside the die, and a dielectric layer overlying the conductive structure. The conductive structure includes a through via in the encapsulant, a redistribution line layer overlying the through via, and a seed layer overlying the redistribution line layer. The dielectric layer includes an opening, wherein the opening exposes a surface of the conductive structure, the opening has a scallop sidewall, and an included angle between a bottom surface of the dielectric layer and a sidewall of the opening is larger than about 60 degrees.

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.

Abstract: A method for forming a redistribution structure in a semiconductor package and a semiconductor package including the redistribution structure are disclosed. In an embodiment, the method may include encapsulating an integrated circuit die and a through via in a molding compound, the integrated circuit die having a die connector; depositing a first dielectric layer over the molding compound; patterning a first opening through the first dielectric layer exposing the die connector of the integrated circuit die; planarizing the first dielectric layer; depositing a first seed layer over the first dielectric layer and in the first opening; and plating a first conductive via extending through the first dielectric layer on the first seed layer.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.

Abstract: Trenches are opened from a top surface of a production wafer that extend down through scribe areas to a depth that is only partially through a semiconductor substrate. Prior to performing a bumping process, a first handle is attached to the top surface of the production wafer. A back surface of the semiconductor substrate is then thinned to reach the trenches and form a wafer level chip scale package at each integrated circuit location delimited by the trenches. A second handle is then attached to a bottom surface of the thinned semiconductor substrate, and the first handle is removed to expose underbump metallization pads at the top surface. The bumping process is then performed to form a solder ball at each of the exposed underbump metallization pads.

Abstract: The present invention provides a SiP structure and method for a light emitting diode (LED) chip. The packaging structure includes: a heat sink structure, a first chip, a first packaging layer, a second packaging layer, a rewiring layer, an LED chip, a printed circuit board (PCB), and a third packaging layer. In the present invention, chips with a plurality of functions, including the first chip, the LED chip, and the like, are integrated into one packaging structure through fan-out system-level packaging, to meet a plurality of different system functional requirements and improve the performance of the packaging system. By the rewiring layer, a metal connecting pillar, a metal lead wire, and the like, the first chip, the LED chip, and the PCB are electrically connected, to achieve a three-dimensional vertically stacked package thereby effectively reducing the area of a SiP and improving the integration of the packaging system.

Abstract: A package structure includes a first dielectric layer, a first semiconductor device over the first dielectric layer, a first redistribution line in the first dielectric layer, a second dielectric layer over the first semiconductor device, a second semiconductor device over the second dielectric layer, a second redistribution line in the second dielectric layer, a conductive through-via over the first dielectric layer and electrically connected to the first redistribution line, a conductive ball over the conductive through-via and electrically connected to the second redistribution line, and a molding material. The molding material surrounds the first semiconductor device, the conductive through-via, and the conductive ball, wherein a top of the conductive ball is higher than a top of the molding material.

Abstract: A USB memory according to a present embodiment is the USB memory capable of data transfer by being connected with a receptacle, and includes a wiring board, a semiconductor chip, a connector, and an adhesive film. The wiring board includes wiring. The semiconductor chip is electrically connected with the wiring. The connector includes a first connection, a second connection, and a holder. The first connection is electrically connected with the semiconductor chip via the wiring. The second connection is electrically connected with the first connection and is connectable with the receptacle. The holder holds the first connection and the second connection. The adhesive film is provided at least between the wiring board and the holder.

Abstract: A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.

Abstract: A package that includes a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer and a plurality of interconnects comprising a first via interconnect and a first trace interconnect, wherein the first via interconnect is directly coupled to the first trace interconnect. The first via interconnect is coupled to the first trace interconnect without an intervening pad interconnect between the first via interconnect and the first trace interconnect.

Abstract: In one example, a semiconductor device comprises a main substrate having a top side and a bottom side, a first electronic component on the top side of the main substrate, a second electronic component on the bottom side of the main substrate, a substrate structure on the bottom side of the main substrate adjacent to the second electronic component, and an encapsulant structure comprising an encapsulant top portion on the top side of the main substrate and contacting a side of the first electronic component, and an encapsulant bottom portion on the bottom side of the main substrate and contacting a side of the second electronic component and a side of the substrate structure. Other examples and related methods are also disclosed herein.

Abstract: An integrated circuit (IC) chip can include a die with an interconnect conductively coupled to a leadframe, wherein the leadframe forms a portion of a given surface of the IC chip. The IC chip can also include an encapsulating material molded over the die and the leadframe. The encapsulating material can form another surface of the IC chip. The other surface of the IC chip opposes the given surface of the IC chip. The IC chip can further include a vertical wire extending through the encapsulating material in a direction that is substantially perpendicular to the given surface of the IC chip and the vertical wire protruding through the other surface of the IC chip to form a vertical connector for the IC chip. The vertical connector can be coupled to the interconnect on the die.

Abstract: A bonding head for a die bonding apparatus and a die bonding apparatus including the bonding head, the bonding head including a head body; a thermal pressurizer mounted on a lower surface of the head body, the thermal pressurizer being configured to hold and heat at least one die and including a heater having a first heating surface that faces a held surface of the die; and a thermal compensator at an outer region of the die, the thermal compensator extending downwardly from the lower surface of the head body and including at least one thermal compensating block having a second heating surface that emits heat from a heating source therein and that faces a side surface of the die held on the thermal pressurizer.

Abstract: A semiconductor package includes a molding compound, a chip and a conductive pad, wherein the chip is electrically connected to the conductive pad and both are encapsulated in the molding compound. An anchor flange is formed around a top surface of the conductive pad by over plating. When the conductive pad is embedded in the molding compound, the anchor flange engages the molding compound to prevent the conductive pad from separation. Bottoms of a chip and the conductive pad are exposed from the molding compound for electrically soldering to a circuit board.

Abstract: A semiconductor package includes a substrate, a composite seed-barrier layer, a routing via, and a semiconductor die. The substrate has a through hole formed therethrough. The composite seed-barrier layer extends on sidewalls of the through hole and includes a first barrier layer, a seed layer, and a second barrier layer sequentially stacked on the sidewalls of the through hole. The routing via fills the through hole and is separated from the substrate by the composite seed-barrier layer. The semiconductor die is electrically connected to the routing via. Along the sidewalls of the through holes, at a level height corresponding to half of a total thickness of the substrate, the seed layer is present as inclusions of seed material surrounded by barrier material of the first barrier layer and the second barrier layer.

Abstract: An injection mould and an injection moulding method are provided. The injection mould includes a base plate used to place a packaged chip to be injection moulded including a substrate and at least one of the chips fixed on the front substrate by a flip chip process. The substrate has a gas hole. Two or more gas ducts that extend in at least two intersected directions and connect with one another are formed in the base plate. Two ends of each one of gas ducts are open, and at least one of the gas ducts is buried into the base plate. Each one of gas ducts is provided with a gas outlet. When the packaged chip is placed on the base plate, the gas outlet connects with the gas hole of the substrate.

Abstract: A package includes a die and a redistribution structure. The die has an active surface and is wrapped around by an encapsulant. The redistribution structure disposed on the active surface of the die and located above the encapsulant, wherein the redistribution structure comprises a conductive via connected with the die, a routing pattern located above and connected with the conductive via, and a seal ring structure, the seal ring structure includes a first seal ring element and a second seal ring element located above and connected with the first seal ring element, wherein the second seal ring element includes a seed layer sandwiched between the first seal ring element and the second seal ring element, and a top surface of the first seal ring element is substantially coplanar with a top surface of the conductive via.

Abstract: The semiconductor device according to the present invention comprises; a semiconductor element having one surface with a plurality of electrode pads; an electrode structure including a plurality of metal terminals and a sealing resin. The plurality of metal terminals being disposed in a region along a circumference of the one surface. The sealing resin holding the plurality of metal terminals and being disposed on the one surface of the semiconductor element. The electrode structure includes a first surface opposed to the one surface of the semiconductor element, a second surface positioned in an opposite side of the first surface, and a third surface positioned between the first surface and the second surface. Each of the plurality of metal terminals is exposed from the sealing resin in at least a part of the second surface and at least a part of the third surface.