And Encapsulating Patents (Class 438/126)
  • Patent number: 10361394
    Abstract: An OLED device encapsulating structure used to encapsulate an OLED is disclosed. The OLED device encapsulating structure includes a substrate, a barrier layer formed on the substrate, a surface active layer disposed on the barrier layer, and a buffer layer stacked on the surface active layer. An orthogonal projection of the buffer layer onto the barrier layer may coincide with that of the surface active layer onto the barrier layer. A composite layer may further be stacked on the buffer layer. An OLED device and a display screen are also disclosed.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: July 23, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Hui Huang
  • Patent number: 10163862
    Abstract: A device comprises a bottom package comprising an interconnect structure, a molding compound layer over the interconnect structure, a semiconductor die in the molding compound layer and a solder layer embedded in the molding compound layer, wherein a top surface of the solder layer is lower than a top surface of the molding compound layer and a top package bonded on the bottom package through a joint structure formed by the solder layer and a bump of the top package.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Kuo-Chuan Liu
  • Patent number: 10115774
    Abstract: A base body including a plurality of first regions and a second region having a shape surrounding each of the first regions is prepared. A resin layer is formed in the plurality of first regions while avoiding the second region. A buried layer having a moisture-proof property higher than the resin layer is formed in the second region. A functional layer including a self-emitting element layer emitting light whose luminance is controlled for each of a plurality of unit pixels constituting an image is formed on the resin layer and the buried layer. The buried layer and the functional layer are cut along a line passing through the second region, so as to separate the resin layer into a plurality of portions respectively corresponding to the plurality of first regions.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: October 30, 2018
    Assignee: Japan Display Inc.
    Inventors: Takeshi Kuriyagawa, Kazufumi Watabe
  • Patent number: 10032826
    Abstract: Provided is a light extraction substrate capable of achieving both light extraction efficiency and preservability. Before forming a cap layer, a step of reducing in-membrane water content such that the in-membrane water content of a layer formed between a gas barrier layer and the cap layer is less than 1.0×1015/mg is performed. The in-membrane water content of less than 1.0×1015/mg is maintained until at least a step of forming the cap layer after the step of reducing the in-membrane water content, and the cap layer is then formed through a dry process.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: July 24, 2018
    Assignee: KONICA MINOLTA, INC.
    Inventors: Takaaki Kuroki, Yasunobu Kobayashi
  • Patent number: 9698118
    Abstract: Methods and apparatus are disclosed for attaching the integrated circuit (IC) packages to printed circuit boards (PCBs) to form smooth solder joints. A polymer flux may be provided in the process to mount an IC package to a PCB. The polymer flux may be provided on connectors of the IC package, or provided on PCB contact pad and/or pre-solder of the PCB. When the IC package is mounted onto the PCB, the polymer flux may cover a part of the connector, and may extend to cover a surface of the molding compound on the IC package. The polymer flux may completely cover the connector as well. The polymer flux delivers a fluxing component that facilitates smooth solder joint formation as well as a polymer component that offers added device protection by encapsulating individual connectors. The polymer component may be an epoxy.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 9666599
    Abstract: According to one embodiment, a display device includes an underlying insulation layer formed on a surface of a resin layer, and a thin-film transistor formed above the surface of the resin layer via the underlying insulation layer. The underlying insulation layer includes a three-layer multilayer structure of a first silicon oxide film, a silicon nitride film formed above the first silicon oxide film, and a second silicon oxide film formed above the silicon nitride film.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: May 30, 2017
    Assignee: Japan Display Inc.
    Inventors: Masato Hiramatsu, Yasushi Kawata, Arichika Ishida
  • Patent number: 9664955
    Abstract: The described embodiments relate generally to liquid crystal displays (LCDs), and more particularly to methods for extending a glass portion of a display to an edge of a display housing. In one embodiment, a thin cover glass layer is provided between a color filter glass layer and an upper polarizer. The thin cover glass layer is supported along an edge of the display by a filler material that can include a foam dam and a glass spacer or adhesive filler. The filler material allows the cover glass layer to be supported without damaging any drivers or circuits located on an underlying thin film transistor glass layer. In another embodiment, a glass spacer circuit with integrated drivers and circuitry on its lower surface can support the cover glass along the edge of the display.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: May 30, 2017
    Assignee: Apple Inc.
    Inventors: Eric Lee Benson, Bryan W. Posner, Jun Qi, Victor Hao-En Yin, Christiaan A. Ligtenberg, Dinesh C. Mathew, Adam T. Garelli
  • Patent number: 9647231
    Abstract: Disclosed is a method for the production of an organic light emitting device of the OLED type, the method including the following sequences of steps: a step of forming a stack of layers on a substrate; the stack including, successively and in the following order, a first electrode, an organic layer and a second electrode; a step of positioning a cover; a step of forming a connection pad. The method also includes: a step of fixing a first end of at least one elongated electrical connection member to an area of the connection pad covering a portion of the second face of the cover and a step of forming a layer of resist, the layer of resist being so configured as to preserve an electrical access to a second end of the elongated electrical connection member above the layer of resist.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: May 9, 2017
    Assignee: ASTRON FIAMM SAFETY
    Inventors: Mohamed Khalifa, Bruno Dussert-Vidalet, Vincent Michalcik
  • Patent number: 9634285
    Abstract: The invention relates to an electrical device comprising an electrical unit (2) like an organic light emitting diode, a protection element (3) like a thin film encapsulation, which at least partly covers the electrical unit, for protecting the electrical unit against water and/or oxygen, and a detection layer (4) arranged between the protection element and the electrical unit or within the protection element, wherein the detection layer comprises organic material and is adapted such that a property of the detection layer is changed, if the detection layer is in contact with a contact gas usable for detecting a permeability of the protection element. This allows easily integrating a fast detection test for detecting a permeability of the protection element into a production process for producing the electrical device, i.e. a time consuming external permeability test may not be required.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: April 25, 2017
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Jens Meyer, Soren Hartmann
  • Patent number: 9177848
    Abstract: A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. The metal vias are surrounded by organic material. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. The RDL and through-hole vias (THV) provide expanded interconnect flexibility to adjacent die. Repassivation layers are formed between the RDL on the second surface of the die for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The RDL provide electrical interconnect to the adjacent die. Bond wires and solder bumps also provide electrical connection to the semiconductor die.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: November 3, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Tai Do, Heap Hoe Kuan, Linda Pei Ee Chua
  • Patent number: 9087930
    Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: July 21, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Hin Hwa Goh, Yu Gu, Il Kwon Shim, Rui Huang, Seng Guan Chow, Jianmin Fang, Xia Feng
  • Patent number: 9082780
    Abstract: A semiconductor device has a semiconductor die. An encapsulant is deposited around the semiconductor die. An interconnect structure having a conductive bump is formed over the encapsulant and semiconductor die. A mechanical support layer is formed over the interconnect structure and around the conductive bump. The mechanical support layer is formed over a corner of the semiconductor die and over a corner of the interconnect structure. An opening is formed through the encapsulant that extends to the interconnect structure. A conductive material is deposited within the opening to form a conductive through encapsulant via (TEV) that is electrically connected to the interconnect structure. A semiconductor device is mounted to the TEV and over the semiconductor die to form a package-on-package (PoP) device. A warpage balance layer is formed over the encapsulant opposite the interconnect structure.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: July 14, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Kang Chen, Yu Gu
  • Patent number: 9076737
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base strip having a base top side; forming a terminal body with a substantially spherical shape partially in the base strip; attaching a device adjacent the terminal body and over the base top side, a device mount side of the device below a top portion of the terminal body; attaching a device connector to the device and the top portion of the terminal body; applying an encapsulant over the device connector, the device, and the top portion of the terminal body; and removing the base strip providing the terminal body partially exposed from the encapsulant.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: July 7, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Jose Alvin Caparas, Lionel Chien Hui Tay
  • Publication number: 20150145115
    Abstract: A semiconductor device includes a carrier, a die including a first surface and a second surface, a plurality of first conductive bumps disposed between the second surface of the carrier and the die, wherein the die is flip bonded on the carrier, and a molding disposed over the carrier and surrounding the die, wherein the molding includes a recessed portion disposed on the first surface of the die thereby leaving a portion of the first surface is uncovered by the molding. Further, a method of manufacturing a semiconductor device includes providing a carrier, flip bonding a die on the carrier, disposing a rubber material on a first surface of the die and within the first surface of the die, and forming a molding surrounding the rubber material and covering the carrier.
    Type: Application
    Filed: November 22, 2013
    Publication date: May 28, 2015
    Applicant: TAIWAN SEMICOMDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: YU-CHIH LIU, CHUN-CHENG LIN, WEI-TING LIN, KUAN-LIN HO, CHIN-LIANG CHEN, SHIH-YEN LIN
  • Publication number: 20150145137
    Abstract: An electronic device is formed by depositing polyimide on a glass substrate. A conductive material is deposited on the polyimide and patterned to form electrodes and signal traces. Remaining portions of the electronic device are formed on the polyimide. A second polyimide layer is then formed on the first polyimide layer. The glass substrate is then removed, exposing the electrodes and the top surface of the electronic device.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Applicant: STMicroelectronics Pte. Ltd
    Inventors: Calvin Leung, Olivier Le Neel
  • Publication number: 20150145123
    Abstract: Disclosed herein are a power semiconductor module and a method of manufacturing the same. The power semiconductor module includes: a substrate on which a semiconductor device is mounted; a pin positioned on the substrate and having one side electrically connected to the substrate; and a molding part formed to cover a portion of the pin and the substrate and the semiconductor device, wherein the molding part has a pin insertion opening.
    Type: Application
    Filed: June 25, 2014
    Publication date: May 28, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Job Ha
  • Publication number: 20150145145
    Abstract: Disclosed herein is an IC embedded substrate that includes a core substrate having an opening, an IC chip provided in the opening, a lower insulating layer, and upper insulating layer. The IC chip and the core substrate is sandwiched between the lower insulating layer and the upper insulating layer. The upper insulating layer is formed in such a way as to fill a gap between a side surface of the IC chip and an inner peripheral surface of the opening of the core substrate. A first distance from the upper surface of the IC chip to an upper surface of the upper insulating layer is shorter than a second distance from the upper surface of the core substrate to the upper surface of the upper insulating layer.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 28, 2015
    Applicant: TDK Corporation
    Inventors: Kazutoshi TSUYUTANI, Masashi KATSUMATA
  • Publication number: 20150147851
    Abstract: A preassembly semiconductor device comprises chip soldering structures on a semiconductor chip and substrate soldering structures on a substrate corresponding to the chip soldering structures. The substrate soldering structures extend toward the chip soldering structures for forming solder connections with the chip soldering structures. The chip and the substrate are in preassembly positions relative to one another. The height of the substrate soldering structures is greater than the height of the chip soldering structures. A pre-applied underfill is contiguous with the substrate and is sufficiently thick so as to extend substantially no further than the full height of the substrate soldering structures.
    Type: Application
    Filed: October 28, 2014
    Publication date: May 28, 2015
    Applicant: International Business Machines Corporation
    Inventors: Claudius Feger, Michael A. Gaynes, Jae-Woong Nah, Da-Yuan Shih
  • Patent number: 9040361
    Abstract: A CSP includes: a hard board having a first wiring layer with conductive pads; a plurality of conductive elements disposed on at least a portion of the conductive pads; an electronic component having opposite active and inactive surfaces and being mounted on the hard board via the inactive surface; an encapsulating layer disposed on the hard board for encapsulating the conductive elements and electronic component, the active surface of the electronic component and the surfaces of the conductive elements being exposed through the encapsulating layer; a first dielectric layer and a third wiring layer disposed on the encapsulating layer, the third wiring layer being electrically connected to the conductive elements and the electronic component and further electrically connected to the first wiring layer through the conductive elements, thereby obtaining a stacked connection structure without the need of PTHs and using the hard board as a main structure to avoid warpage.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: May 26, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chiang-Cheng Chang, Chien-Ping Huang, Chun-Chi Ke, Hsin-Yi Liao, Hsi-Chang Hsu
  • Patent number: 9040349
    Abstract: Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of semiconductor die comprising electronic devices to an interposer wafer, and applying an underfill material between the die and the interposer wafer. A mold material may be applied to encapsulate the die. The interposer wafer may be thinned to expose through-silicon-vias (TSVs) and metal contacts may be applied to the exposed TSVs. The interposer wafer may be singulated to generate assemblies comprising the semiconductor die and an interposer die. The die may be placed on the interposer wafer utilizing an adhesive film. The interposer wafer may be singulated utilizing one or more of: a laser cutting process, reactive ion etching, a sawing technique, and a plasma etching process. The die may be bonded to the interposer wafer utilizing a mass reflow or a thermal compression process.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: May 26, 2015
    Assignee: Amkor Technology, Inc.
    Inventors: Michael G. Kelly, Ronald Patrick Huemoeller, Won Chul Do, David Jon Hiner
  • Patent number: 9040388
    Abstract: A patterned adhesive layer including holes is employed to attach a coreless substrate layer to a stiffener. The patterned adhesive layer is confined to kerf regions, which are subsequently removed during singulation. Each hole in the patterned adhesive layer has an area that is greater than the area of a bottomside interconnect footprint of the coreless substrate. The patterned adhesive layer may include a permanent adhesive that is thermally curable or ultraviolet-curable. The composition of the stiffener can be tailored so that the thermal coefficient of expansion of the stiffener provides tensile stress to the coreless substrate layer at room temperature and at the bonding temperature. The tensile stress applied to the coreless substrate layer prevents or reduces warpage of the coreless substrate layer during bonding. Upon dicing, bonded stacks of a semiconductor chip and a coreless substrate can be provided without adhesive thereupon.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: May 26, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Edmund Blackshear
  • Publication number: 20150140737
    Abstract: A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die.
    Type: Application
    Filed: December 19, 2014
    Publication date: May 21, 2015
    Inventor: John Richard Hunt
  • Publication number: 20150137391
    Abstract: The invention relates to an electronic component (1) having a corrosion-protected bonding connection and a method for producing said component. For this purpose the electronic component (1) has at least one semiconductor chip (3) on a substrate (4). Moreover, a bonding connection at risk of corrosion is provided on the semiconductor chip (3). For encapsulation of the at least one semiconductor chip (3) and the at least one bonding connection at risk of corrosion, said semiconductor chip and bonding connection are surrounded by a hermetically sealing housing (5). The hermetically sealed bonding connection is a bonding wire connection (2) which is fully enclosed in the housing (5), in which the substrate (4) is at least partially enclosed. The substrate (4) has at least one surface-mounted hydrolysis-sensitive component (6) in the housing (5).
    Type: Application
    Filed: November 29, 2012
    Publication date: May 21, 2015
    Applicant: Robert Bosch GMBH
    Inventors: Fabian Bez, Johannes Duerr, Rolf Becker, Sven Lamers, Lutz Mueller, Michael Schlecht
  • Publication number: 20150130048
    Abstract: A semiconductor package includes a mold body having a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces, a first semiconductor module including a plurality of first semiconductor chips and a first encapsulation layer disposed above the first semiconductor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of second semiconductor channels and a second encapsulation layer disposed above the second semiconductor channels. The semiconductor package further includes a plurality of external connectors extending through one or more of the side faces of the mold body.
    Type: Application
    Filed: November 12, 2013
    Publication date: May 14, 2015
    Inventors: Olaf Hohlfeld, Juergen Hoegerl, Gottfried Beer, Magdalena Hoier
  • Patent number: 9029205
    Abstract: A method for manufacture of an integrated circuit packaging system includes: mounting an integrated circuit, having a planar interconnect, over a carrier with the planar interconnect at a non-active side of the integrated circuit and an active side of the integrated circuit facing the carrier; connecting the integrated circuit and the carrier; connecting the planar interconnect and the carrier; and forming an encapsulation over the integrated circuit, the carrier, and the planar interconnect.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: May 12, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Reza Argenty Pagaila, Byung Tai Do, Heap Hoe Kuan
  • Patent number: 9027238
    Abstract: A multilayered printed circuit board or a substrate for mounting a semiconductor device includes a semiconductor device, a first resin insulating layer accommodating the semiconductor device, a second resin insulating layer provided on the first resin insulating layer, a conductor circuit provided on the second resin insulating layer, and via holes for electrically connecting the semiconductor device to the conductor circuit, wherein the semiconductor device is accommodated in a recess provided in the first resin insulating layer, and a metal layer for placing the semiconductor device is provided on the bottom face of the recess. A multilayered printed circuit board in which the installed semiconductor device establishes electrical connection through the via holes is provided.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: May 12, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Sotaro Ito, Michimasa Takahashi, Yukinobu Mikado
  • Publication number: 20150123272
    Abstract: A method of forming a package on a package structure includes applying a no-reflow underfill (NUF) layer over a substrate, wherein the substrate has at least one first bump and a plurality of second bumps surrounding the at least one first bump. The method further includes bonding a semiconductor die to the at least one first bump. The method further includes bonding an interposer frame to the plurality of second bumps, wherein the interposer frame surrounds the semiconductor die, wherein the semiconductor die is disposed in an opening of the interposer frame.
    Type: Application
    Filed: January 9, 2015
    Publication date: May 7, 2015
    Inventor: Jiun Yi WU
  • Patent number: 9023690
    Abstract: Embodiments of the present invention are directed to leadframe area array packaging technology for fabricating an area array of I/O contacts. A manufactured package includes a polymer material substrate, an interconnect layer positioned on top of the polymer material substrate, a die coupled to the interconnect layer via wire bonds or conductive pillars, and a molding compound encapsulating the die, the interconnect layer and the wire bonds or conductive pillars. The polymer material is typically formed on a carrier before assembly and is not removed to act as the substrate of the manufactured package. The polymer material substrate has a plurality of through holes that exposes the interconnect layer at predetermined locations and enables solder ball mounting or solder printing directly to the interconnect layer. In some embodiments, the semiconductor package includes a relief channel in the polymer material substrate to improve the reliability performance of the manufactured package.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: May 5, 2015
    Assignee: United Test and Assembly Center
    Inventors: Antonio Bambalan Dimaano, Jr., Nathapong Suthiwongsunthorn, Yong Bo Yang
  • Patent number: 9024426
    Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device includes an interposer and a first semiconductor package comprising a first substrate, and a first semiconductor chip mounted on the first substrate. The device also includes at least two second semiconductor packages electrically connected to a top surface of the interposer, the second semiconductor packages spaced apart from each other in a direction parallel to the top surface of the interposer. Each of the second semiconductor packages comprises a second substrate, a second semiconductor chip mounted on the second substrate and a mold part disposed on the second substrate to protect the second semiconductor chip.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: May 5, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kundae Yeom
  • Patent number: 9024353
    Abstract: An encapsulating sheet-covered semiconductor element includes a semiconductor element having one surface in contact with a board and the other surface disposed at the other side of the one surface and an encapsulating sheet covering at least the other surface of the semiconductor element. The encapsulating sheet includes an exposed surface that is, when projected from one side toward the other side, not included in the one surface of the semiconductor element and exposed from the one surface and the exposed surface has the other side portion that is positioned toward the other side with respect to the one surface of the semiconductor element.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: May 5, 2015
    Assignee: Nitto Denko Corporation
    Inventors: Hiroyuki Katayama, Takashi Kondo, Yuki Ebe, Munehisa Mitani
  • Patent number: 9023691
    Abstract: A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. An encapsulation separates respective pairs of coupled first and second connectors from one another and may encapsulate the microelectronic element and fill spaces between the support elements. The first connectors, the second connectors or both may be partially encapsulated prior to electrically coupling respective pairs of first and second connectors in columns.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: May 5, 2015
    Assignee: Invensas Corporation
    Inventors: Ilyas Mohammed, Belgacem Haba
  • Publication number: 20150115439
    Abstract: The present disclosure relates to a chip package and a method for forming the same. The chip package comprises a carrier pad, a chip, and a plurality of second conductive bumps, and a molding compound. The carrier pad has a first surface with a plurality of first conductive bumps formed thereon. The chip has an active surface. One end of each of the plurality of second conductive bumps is electrically coupled to the active surface, and the other end of each of the plurality of second conductive bumps is electrically coupled to the first conductive bumps. The molding compound encapsulates the chip and completely fills space between the carrier pad and the chip.
    Type: Application
    Filed: October 31, 2014
    Publication date: April 30, 2015
    Inventor: Xiaochun Tan
  • Publication number: 20150115465
    Abstract: A semiconductor device has a substrate. A conductive via is formed through the substrate. A plurality of first contact pads is formed over a first surface of the substrate. A plurality of second contact pads is formed over a second surface of the substrate. A dummy pattern is formed over the second surface of the substrate. An indentation is formed in a sidewall of the substrate. An opening is formed through the substrate. An encapsulant is deposited in the opening. An insulating layer is formed over second surface of the substrate. A dummy opening is formed in the insulating layer. A semiconductor die is disposed adjacent to the substrate. An encapsulant is deposited over the semiconductor die and substrate. The first surface of the substrate includes a width that is greater than a width of the second surface of the substrate.
    Type: Application
    Filed: July 11, 2014
    Publication date: April 30, 2015
    Inventors: Yaojian Lin, Kang Chen, Hin Hwa Goh, Il Kwon Shim
  • Publication number: 20150118801
    Abstract: To provide a semiconductor device characterized in that lands for mounting thereon solder balls placed in an inner area of a chip mounting area have an NSMD structure. This means that lands for mounting thereon solder balls placed in an area of the back surface of a through-hole wiring board overlapping with a chip mounting area in a plan view have an NSMD structure. According to the invention, a semiconductor device to be mounted on a mounting substrate with balls has improved reliability.
    Type: Application
    Filed: January 6, 2015
    Publication date: April 30, 2015
    Inventors: Kozo HARADA, Shinji BABA, Masaki WATANABE, Satoshi YAMADA
  • Patent number: 9018749
    Abstract: Described herein is a stacked package using laser direct structuring. The stacked package includes a die attached to a substrate. The die is encapsulated with a laser direct structuring mold material. The laser direct structuring mold material is laser activated to form circuit traces on the top and side surfaces of the laser direct structuring mold material. The circuit traces then undergo metallization. A package is then attached to the metalized circuit traces and is electrically connected to the substrate via the metalized circuit traces.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: April 28, 2015
    Assignee: Flextronics AP, LLC
    Inventors: Samuel Tam, Bryan Lee Sik Pong, Dick Pang
  • Patent number: 9018045
    Abstract: Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method comprises encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body. The outer molded body has a portion, which circumscribes the core redistribution layer. One or more topside redistribution layers are produced over the core redistribution layer. A contact array is formed over the topside redistribution layer and electrically coupled to the first semiconductor die encapsulated in the outer molded body through the topside redistribution layers and the core redistribution layers.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: April 28, 2015
    Assignee: Freescale Semiconductor Inc.
    Inventors: Weng Foong Yap, Douglas G. Mitchell
  • Patent number: 9018742
    Abstract: An electronic device includes a semiconductor chip. A contact element, an electrical connector, and a dielectric layer are disposed on a first surface of a conductive layer facing the semiconductor chip. A first conductive member is disposed in a first recess of the dielectric layer. The first conductive member electrically connects the contact element of the semiconductor chip with the conductive layer. A second conductive member is disposed in a second recess of the dielectric layer. The second conductive member electrically connects the conductive layer with the electrical connector.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: April 28, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ivan Nikitin, Joachim Mahler
  • Publication number: 20150108627
    Abstract: An electronic component comprises: a resin frame; a semicionductor substrate housed in the resin frame; a plate shape metal member having at least one end fixed in the resin frame at a position spaced apart from the semiconductor substrate; an electrical connection region portion formed on the surface on the side of the plate shape metal member of the semiconductor substrate with an electrically conductive material; and a solder layer formed on the surface on the side of the plate shape metal member of the electrical connection region portion, wherein the plate shape metal member supports the semiconductor substrate without contact through the solder layer and the electrical connection region portion, and is electrically connected to the electrical connection region portion.
    Type: Application
    Filed: October 21, 2014
    Publication date: April 23, 2015
    Inventors: Yasuo SHIMANUKI, Masakazu FUKUOKA
  • Publication number: 20150108643
    Abstract: A semiconductor device having an embedded semiconductor die and substrate-to-substrate interconnects is disclosed and may include a substrate with a top surface and a bottom surface, a semiconductor die bonded to the top surface of the substrate, a first mold material encapsulating the semiconductor die and at least a portion of the top surface of the substrate, and a first conductive bump that is on the top surface of the substrate and is at least partially encapsulated by the first mold material. An extended substrate may be coupled to the substrate utilizing the first conductive bump. A second conductive bump may be formed on the bottom surface of the substrate, and a second mold material may encapsulate at least a portion of the second conductive bump and at least a portion of the bottom surface of the substrate. A third mold material may be formed between the first mold material and the extended substrate.
    Type: Application
    Filed: October 23, 2014
    Publication date: April 23, 2015
    Inventors: Jin Seong Kim, Ye Sul Ahn, Cha Gyu Song
  • Patent number: 9006030
    Abstract: An integrated circuit includes a stacked conductive layer interposer and a first die at least partially encapsulated in a mold material. The first die is mechanically and electrically attached to a top surface of the stacked conductive layer interposer using solder bumps. The integrated circuit further includes a first warpage correction layer.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: April 14, 2015
    Assignee: Xilinx, Inc.
    Inventors: Woon-Seong Kwon, Suresh Ramalingam, Paul Y. Wu, Manoj Nachnani
  • Publication number: 20150099331
    Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.
    Type: Application
    Filed: December 12, 2014
    Publication date: April 9, 2015
    Inventors: Eiji HAYASHI, Kyo GO, Kozo HARADA, Shinji BABA
  • Publication number: 20150097282
    Abstract: A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.
    Type: Application
    Filed: December 15, 2014
    Publication date: April 9, 2015
    Inventors: Michael Bauer, Alfred Haimerl, Angela Kessler, Wolfgang Schober
  • Patent number: 8999764
    Abstract: Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Ian D. Melville, Kevin S. Petrarca, Kenneth P. Rodbell
  • Patent number: 8999763
    Abstract: Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having an interposer including at least one topological feature, such as a depression in a surface of the interposer, a die coupled to the surface of the interposer, and an encapsulant material formed over the die and the interposer, and disposed in the at least one depression to resist movement of the encapsulant material relative to the interposer. Other embodiments may be described and claimed.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: April 7, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Steven Eskildsen, Aravind Ramamoorthy
  • Patent number: 8999762
    Abstract: A process for encapsulating a micro-device in a cavity formed between a first and a second substrate is provided, including producing the micro-device in or on the first substrate; attaching and securing the second substrate to the first substrate, thereby forming the cavity in which the micro-device is placed; producing at least one hole through one of the two substrates, leading into the cavity opposite a portion of the other of the two substrates; depositing at least one getter material portion through the hole on said portion of the other of the two substrates; and hermetically sealing the cavity by closing the hole.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: April 7, 2015
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Xavier Baillin, Jean-Louis Pornin
  • Patent number: 8999813
    Abstract: A method of forming a focal plane array by: forming a first wafer having sensing material provided on a surface, which is covered by a sacrificial layer, the sensing material being a thermistor material defining at least one pixel; providing supporting legs for the pixel within the sacrificial layer, covering them with a further sacrificial layer and forming first conductive portions in the surface of the sacrificial layer that are in contact with the supporting legs; forming a second wafer having read-out integrated circuit (ROIC), the second wafer being covered by another sacrificial layer, into which is formed second conductive portions in contact with the ROIC; bringing the sacrificial oxide layers of the first wafer and second wafer together such that the first and second conductive portions are aligned and bonding them together such that the sensing material is transferred from the first wafer to the second wafer when a sacrificial bulk layer of the first wafer is removed; and removing the sacrificial l
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: April 7, 2015
    Assignee: SensoNor AS
    Inventors: Adriana Lapadatu, Gjermund Kittilsland
  • Publication number: 20150091182
    Abstract: A die assembly formed on a thin dielectric sheet is described. In one example, a first and a second die have interconnect areas. A dielectric sheet, such as glass, silicon, or oxidized metal is applied over the interconnect areas of dies. Conductive vias are formed in the dielectric sheet to connect with pads of the interconnect areas. A build-up layer includes routing to connect pads of the first die interconnect area to pads of the second die interconnect area through the conductive vias and a cover is applied over the dies, the dielectric sheet, and the build-up layer.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 2, 2015
    Inventors: Chia-Pin Chiu, Qing Ma, Robert L. Sankman, Paul B. Fischer, Patrick Morrow, William J. Lambert, Charles A. Gealer, Tyler Osborn
  • Publication number: 20150091167
    Abstract: Stress buffer layers for integrated microelectromechanical systems (MEMS) are described. For example, a semiconductor package includes a substrate having first and second surfaces, the second surface having an array of external conductive contacts. A microelectromechanical system (MEMS) component is disposed above the first surface of the substrate. A buffer layer is disposed above the MEMS component, the buffer layer having a first Young's modulus. A mold compound is disposed above the buffer layer, the mold compound having a second Young's modulus higher than the first Young's modulus.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventors: Christian Geissler, Thorsten Meyer, Gerald Ofner, Reinhard Mahnkopf, Andreas Augustin, Christian Mueller
  • Publication number: 20150091157
    Abstract: A semiconductor device has a semiconductor die. The semiconductor die is disposed over a conductive substrate. An encapsulant is deposited over the semiconductor die. A first interconnect structure is formed over the encapsulant. An opening is formed through the substrate to isolate a portion of the substrate electrically connected to the first interconnect structure. A bump is formed over the first interconnect structure. Conductive vias are formed through the encapsulant and electrically connected to the portion of the substrate. A plurality of bumps is formed over the semiconductor die. A first conductive layer is formed over the encapsulant. A first insulating layer is formed over the first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. Protrusions extend above the substrate.
    Type: Application
    Filed: June 14, 2013
    Publication date: April 2, 2015
    Inventors: HeeJo Chi, HanGil Shin, NamJu Cho
  • Publication number: 20150091145
    Abstract: A semiconductor device has a semiconductor die mounted over the carrier. An encapsulant is deposited over the carrier and semiconductor die. The carrier is removed. A first interconnect structure is formed over the encapsulant and a first surface of the die. A second interconnect structure is formed over the encapsulant and a second surface of the die. A first protective layer is formed over the first interconnect structure and second protective layer is formed over the second interconnect structure prior to forming the vias. A plurality of vias is formed through the second interconnect structure, encapsulant, and first interconnect structure. A first conductive layer is formed in the vias to electrically connect the first interconnect structure and second interconnect structure. An insulating layer is formed over the first interconnect structure and second interconnect structure and into the vias. A discrete semiconductor component can be mounted to the first interconnect structure.
    Type: Application
    Filed: December 11, 2014
    Publication date: April 2, 2015
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Yaojian Lin, Pandi C. Marimuthu