Abstract: A semiconductor chip package includes a substrate unit, a chip, metal members, a molding compound and a shielding layer. The chip is assembled on and electrically connected with the substrate unit. The substrate unit includes conductive seat portions surrounding the chip, and defines through holes respectively coated by conducting films to ground the corresponding seat portions. The metal members are assembled on the seat portions, surround the chip, and are grounded through the conducting films. The molding compound encapsulates the chip and the metal members, with part of each metal member exposed out of the molding compound. The shielding layer covers the molding compound and the parts of each metal member exposed out of the molding compound to shield the chip from electromagnetic radiation.

Abstract: An embedded package that may be realized by surrounding a semiconductor chip (or a semiconductor die) in a package substrate. A semiconductor chip of an embedded package may be electrically connected to external connection terminals through interconnection wires instead of bumps, and the interconnection wires may be formed using a wire bonding process. A high reliability embedded package results.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an interposer having an interposer bottom side and an interposer top side; attaching a base integrated circuit to the interposer bottom side; attaching a lead to the interposer bottom side, the lead adjacent the base integrated circuit and entirely below the interposer; and forming an encapsulation partially covering the lead and exposing the interposer top side.

Abstract: Electronic modules are formed by encapsulating microelectronic dies within cavities in a substrate.

Abstract: A semiconductor device includes (i) a tape base material, (ii) a wiring pattern, (iii) a semiconductor element which is electrically connected with the wiring pattern, (iv) a top-side insulating protective film which covers a top surface of the tape base material and has an top-side opening section provided in a region where the top-side insulating protective film faces the semiconductor element, and (v) a reverse-side insulating protective film which covers a reverse surface of the tape base material and has a reverse-side opening section provided on a reverse side below the top-side opening section. The top-side insulating protective film has a protruding opening section extending outwardly from the region. An opening of the reverse-side opening section is 1.00 time to 8.50 times larger in an area than the region.

Abstract: The yield of semiconductor devices is improved. In an upper die of a resin molding die including a pair of the upper die and a lower die, by lengthening the radius of the cross section of an inner peripheral surface of a second corner part facing an injection gate of a cavity more than that of the other corner part, a void contained in a resin in resin injection can be pushed out into an air vent without allowing the void to remain in the second corner part of the cavity. Consequently, the occurrence of the void in the cavity can be prevented and then the occurrence of the appearance defect of the semiconductor device can be prevented.

Abstract: A microelectronic package including a dielectric layer having top and bottom surfaces, the dielectric layer having terminals exposed at the bottom surface; a metallic wall bonded to the dielectric layer and projecting upwardly from the top surface of the dielectric layer and surrounding a region of the top surface; a metallic lid bonded to the wall and extending over the region of the top surface so that the lid, the wall and the dielectric layer cooperatively define an enclosed space; and a microelectronic element disposed within the space and electrically connected to the terminals.

Abstract: A semiconductor device includes an interposer having a base member including a first surface and a second surface opposite to the first surface, a first interconnect formed on the first surface of the base member, a first insulating film formed on the first surface of the base member, a first external terminal and a second external terminal neighboring the first external terminal formed on the second surface of the base member, a second interconnect formed on the second surface of the base member and passing between the first external terminal and the second external terminal, and a second insulating film formed on the second surface of the base member, a semiconductor chip mounted on the first insulating film, a sealing resin formed on the first insulating film and sealing the semiconductor chip. The second insulating film has an opening so that the second interconnect is exposed in an area.

Abstract: Methods of fabricating a circuit structure are provided. The fabrication method includes: forming a chip layer, which includes obtaining at least one chip and disposing a structural material around and physically contacting the side surface(s) of each chip in the chip layer. The structural material has an upper surface substantially coplanar with or parallel to an upper surface of each chip and defines at least a portion of a front surface of the chip layer, and has a lower surface substantially coplanar with or parallel to a lower surface of each chip, which defines at least portion of a back surface of the chip layer. The method further includes forming at least one strengthening structure over the back surface of the chip layer. The strengthening structure is formed to strengthen an interface between the chip(s) and the structural material.

Abstract: A method for protecting an electronic device comprising an organic device body. The method involves the use of a hybrid layer deposited by chemical vapor deposition. The hybrid layer comprises a mixture of a polymeric material and a non-polymeric material, wherein the weight ratio of polymeric to non-polymeric material is in the range of 95:5 to 5:95, and wherein the polymeric material and the non-polymeric material are created from the same source of precursor material. Also disclosed are techniques for impeding the lateral diffusion of environmental contaminants.

Abstract: A packaged electronic device includes a flexible circuit structure and a die. The flexible circuit structure includes a first structural layer and electrical conductors. The die is bonded to the flexible circuit structure by a flexible attachment layer. The die includes interconnects in electrical contact with die circuitry and extending through the die, through the flexible attachment layer, and into electrical contact with respective electrical conductors at first ends. A flexible second structural layer is disposed on the die and exposed portions of the electrical conductors, wherein the die and the electrical conductors are encapsulated by the first structural layer and the second structural layer. The first structural layer and/or the second structural layer include a plurality of openings defining respective exposed areas on the electrical conductors at second ends.

Abstract: An integrated chip package structure and method of manufacturing the same is by adhering dies on a ceramic substrate and forming a thin-film circuit layer on top of the dies and the ceramic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

Abstract: A semiconductor device package includes a semiconductor device having connection pads formed thereon, with the connection pads being formed on first and second surfaces of the semiconductor device with edges of the semiconductor device extending therebetween. A first passivation layer is applied on the semiconductor device and a base dielectric laminate is affixed to the first surface of the semiconductor device that has a thickness greater than that of the first passivation layer. A second passivation layer having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover the second surface and the edges of the semiconductor device, and metal interconnects are coupled to the connection pads, with the metal interconnects extending through vias formed through the first and second passivation layers and the base dielectric laminate sheet to form a connection with the connection pads.

Abstract: Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces are disclosed. In one embodiment, a microelectronic assembly comprises a support member having a first side and a projection extending away from the first side. The assembly also includes a plurality of conductive traces at the first side of the support member. Some of the conductive traces include bond sites carried by the projection and having an outer surface at a first distance from the first side of the support member. The assembly further includes a protective coating deposited over the first side of the support member and at least a portion of the conductive traces. The protective coating has a major outer surface at a second distance from the first side of the support member. The second distance is approximately the same as the first distance such that the outer surface of the protective coating is generally co-planar with the outer surface of the bond sites carried by the projection.

Abstract: A method includes providing a carrier with an adhesive layer disposed thereon; and providing a die including a first surface, a second surface opposite the first surface. The die further includes a plurality of bond pads adjacent the second surface; and a dielectric layer over the plurality of bond pads. The method further includes placing the die on the adhesive layer with the first surface facing toward the adhesive layer and dielectric layer facing away from the adhesive layer; forming a molding compound to cover the die, wherein the molding compound surrounds the die; removing a portion of the molding compound directly over the die to expose the dielectric layer; and forming a redistribution line above the molding compound and electrically coupled to one of the plurality of bond pads through the dielectric layer.

Abstract: An improved semiconductor device package is manufactured by attaching semiconductor chips (130) on an insulating substrate (101) having contact pads (103). A mold is provided, which has a top portion (210) with metal protrusions (202) at locations matching the pad locations. The protrusions are shaped as truncated cones. The substrate and the chips are loaded onto the bottom mold portion (310); the mold is closed by clamping the top portion onto the bottom portion so that the protrusions approach the contact pads. Encapsulation compound is introduced into the cavity and the protrusions create apertures through the encapsulation compound towards the pad locations.

Abstract: Occurrence of a void is suppressed when mounting semiconductor chips over a wiring substrate via a paste-like adhesive material. A die bonding step is provided which mounts semiconductor chips over a chip-mounting region of the wiring substrate via the adhesive material. The wiring substrate includes a plurality of wirings (first wirings) and dummy wirings (second wirings) formed on an upper surface of a core layer. The chip-mounting region is provided over the first wirings and the second wirings. In addition, the die bonding step includes a step of applying the adhesive material over an adhesive material application region over the chip-mounting region. Each of the second wirings is extended along a direction in which the adhesive material spreads in the die bonding step.

Abstract: A semiconductor device having a semiconductor chip having an active surface with flip-chip contacts and a passive surface is disclosed. The flip-chip contacts are surrounded by an electrically insulating layer as underfill material, the layer having a UV B-stageable material. The UV B-stageable material is applied on the active surface of the semiconductor wafer.

Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit over a package carrier; mounting a rounded interconnect on the package carrier; mounting a conductive shield over the package carrier, the conductive shield having an elevated portion and a hole adjacent to the elevated portion with the elevated portion over the integrated circuit and the rounded interconnect exposed from the hole; and forming an encapsulation between the conductive shield and the package carrier with the rounded interconnect exposed.

Abstract: A method for disclosing an integrated circuit embedded in a resin is disclosed. In one embodiment, stabilizing vias can be formed within the resin and can couple to corresponding pads in the integrated circuit. The stabilizing vias can be used in areas prone to failure when the combined resin/integrated circuit is stressed or undergoes some amount of displacement. In one embodiment, the stabilizing vias can be non-functional vias that do not carry electrical signals or power to or from the integrated circuit.

Abstract: A method for producing a component and device including a component is disclosed. A basic substrate having paper as substrate material is provided, at least one integrated circuit is applied to the basic substrate, the at least one integrated circuit applied on the basic substrate is enveloped with an encapsulant, and at least parts of the basic substrate are removed from the at least one enveloped integrated circuit.

Abstract: Embodiments of the present invention relate to an improved package for a bi-directional and reverse blocking battery switch. According to one embodiment, two switches are oriented side-by-side, rather than end-to-end, in a die package. This configuration reduces the total switch resistance for a given die area, often reducing the resistance enough to avoid the use of backmetal in order to meet resistance specifications. Elimination of backmetal reduces the overall cost of the die package and removes the potential failure modes associated with the manufacture of backmetal. Embodiments of the present invention may also allow for more pin connections and an increased pin pitch. This results in redundant connections for higher current connections, thereby reducing electrical and thermal resistance and minimizing the costs of manufacture or implementation of the die package.

Abstract: A package for a microelectronic element 48, such as a semiconductor chip, has a dielectric mass 86 overlying the package substrate 56 and microelectronic element 48 and has top terminals 38 exposed at the top surface 94 of the dielectric mass 86. Traces 36a, 36b extending along edge surfaces 96, 108 of the dielectric mass 86 desirably connect the top terminals 38 to bottom terminals 64 on the package substrate 56. The dielectric mass 86 can be formed, for example, by molding or by application of a conformal layer 505.

Abstract: Package structures for integrating thermoelectric components with stacking chips are presented. The package structures include a chip with a pair of conductive through vias. Conductive elements are disposed one side of the chip contacting the pair of conductive through vias. Thermoelectric components are disposed on the other side of the chip, wherein the thermoelectric component includes a first type conductive thermoelectric element and a second type conductive thermoelectric element respectively corresponding to and electrically connecting to the pair of conductive through vias. A substrate is disposed on the thermoelectric component, wherein the thermoelectric component, the pair of conductive through vias and the conductive element form a thermoelectric current path. Therefore, heat generated from the chip is transferred outward through a thermoelectric path formed from the thermoelectric components, the conductive through vias and the conductive elements.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base carrier; forming a conductive post on the base carrier, the conductive post having a top protrusion with a protrusion top side; mounting a base integrated circuit over the base carrier; and forming a base encapsulation over the base integrated circuit, the base encapsulation having an encapsulation top side and an encapsulation recess with the conductive post partially exposed within the encapsulation recess, the encapsulation top side above the protrusion top side.

Abstract: A process for fabricating a reconstituted wafer that includes chips having connection pads on a front side of the chip, this process including positioning of the chips on an adhesive support, front side down on the support; deposition of a resin on the support in order to encapsulate the chips; and curing of the resin. Before deposition of the resin, the process includes bonding, onto the chips, a support wafer for positioning the chips, this support wafer having parts placed on one side of the chips.

Abstract: Provided is a highly reliable LED package with significantly improved heat radiating properties, manufacturing method of the LED package, and an LED chip assembly used in the LED package. The LED package is characterized in that the LED chip assembly (10) is bonded to a circuit board (11) created by forming metal circuitry (3) on a metal substrate (5) with an insulation layer (4) therebetween, whereas an LED chip (1) of the LED chip assembly and the metal circuitry (3) of the circuit board are connected via an electrical connection member (9), and at least the LED chip assembly and the electrical connection member are encapsulated with resin encapsulant (8) including fluorescent material.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a one-layer substrate with a symmetrical structure, the one-layer substrate having a redistribution pad and an insulation, the redistribution pad only at an insulation top side of the insulation; mounting an integrated circuit over the one-layer substrate; and forming an encapsulation over the integrated circuit.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a single-layer support structure having a structure non-horizontal surface; forming a single-layer contact coplanar with the single-layer support structure, the single-layer contact having a contact non-horizontal surface; forming a single-layer insulation coplanar with the single-layer contact and horizontally between the structure non-horizontal surface and the contact non-horizontal surface; forming an upper support pad over the single-layer insulation and directly on the single-layer support structure; and mounting an integrated circuit over the upper support pad.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a circuit substrate having an active side opposite to an inactive portion; attaching a nonconductive cover to the active side; forming a separation-gap partially cutting into the nonconductive cover and the circuit substrate to a kerf depth; attaching a back-grinding tape to the nonconductive cover; removing a portion of the inactive portion; and exposing the nonconductive cover by removing the back-grinding tape.

Abstract: The present invention provides a ceramic heat sink material for a pressure contact structure configured by providing a resin layer on a ceramic substrate, wherein the resin layer has durometer (Shore) hardness (A-type) of 70 or less, and an average value of gaps existing in an interface between the ceramic substrate and the resin layer is 3 ?m or less. Further, it is preferable that the resin layer is formed by solidifying a thermosetting resin which is fluidized at a temperature of 60° C. Due to above structure, there can be obtained a ceramic heat sink and a semiconductor module using the heat sink having a good close-contacting property with respect to the pressing member.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a conductive post on the substrate, the conductive post includes a vertical side; attaching an integrated circuit to the substrate; and forming an encapsulant including a molded cavity, the vertical side circumscribed by and exposed within the molded cavity from the encapsulant.

Abstract: An integrated circuit leadframe and a fabrication method for fabricating the integrated circuit leadframe include forming a leadframe having leads around a die pad that has a peripheral die pad rim. A discrete, alternately staggered surface configuration is formed in the die pad rim. The discrete, alternately staggered surface configuration creates space in the die pad for connecting and separating ground bond wire-bonds and down bond wire-bonds, and provides for locking encapsulant firmly to the die pad.

Abstract: A semiconductor device includes a cooling device, an insulating substrate, a semiconductor element, an external connection terminal, and a resin portion. The insulating substrate is brazed to an outer surface of the cooling device. The semiconductor element is brazed to the insulating substrate. The external connection terminal includes a first end, which is electrically connected to the semiconductor element, and an opposite second end. The resin portion is molded to the insulating substrate, the semiconductor element, the first end of the external connection terminal, and at least part of the cooling device.

Abstract: A package structure having an embedded semiconductor component, includes: a chip having an active surface with electrode pads and an inactive surface opposite to the active surface; a first insulating protection layer having a chip mounting area for the chip to be mounted thereon via the active surface thereof; a plurality of connection columns disposed in the first insulating protection layer at positions corresponding to the electrode pads and electrically connected to the electrode pads via solder bumps; an encapsulant formed on one surface of the first insulating protection layer having the chip mounted thereon for encapsulating the chip; and a built-up structure formed on the other surface of the first insulating protection layer and the connection columns. Due to the bending resistance of the encapsulant, the warpage of the built-up structure is prevented.

Abstract: A transition layer 38 is provided on a die pad 22 of an IC chip 20 and integrated into a multilayer printed circuit board 10. Due to this, it is possible to electrically connect the IC chip 20 to the multilayer printed circuit board 10 without using lead members and a sealing resin. Also, by providing the transition layer 38 made of copper on an aluminum pad 24, it is possible to prevent a resin residue on the pad 24 and to improve connection characteristics between the die pad 24 and a via hole 60 and reliability.

Abstract: A blank and a semiconductor device include a composite panel with semiconductor chips embedded in a plastic package molding compound. The blank includes a composite panel with semiconductor chips arranged in rows and columns in a plastic package molding compound with active upper sides of the semiconductor chips forming a coplanar surface area with the upper side of the composite panel. The blank further includes an orientation indicator impressed into the plastic package molding compound when the semiconductor chips are embedded within the molding compound.

Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).

Abstract: A microelectronic assembly includes a substrate having a first and second opposed surfaces. A microelectronic element overlies the first surface and first electrically conductive elements can be exposed at at least one of the first surface or second surfaces. Some of the first conductive elements are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the substrate and the bases, each wire bond defining an edge surface extending between the base and the end surface. An encapsulation layer can extend from the first surface and fill spaces between the wire bonds, such that the wire bonds can be separated by the encapsulation layer. Unencapsulated portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation layer.

Abstract: A method for fabricating a multi-chip stacked structure includes joining multiple wafers with interconnect structures interposed between each set of adjacent wafers. As each wafer is added to the stack, the new wafer is thinned to expose a through silicon via and back side metallization is performed. After the last wafer has been so joined, the wafer stack is diced and then joined to a substrate with a final interconnect structure interposed between the final wafer and the substrate.

Abstract: An electronic device includes a carrier, a plurality of pins, and an electronic circuit that includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is attached to the carrier and the second semiconductor chip is attached to one of the plurality of pins.

Abstract: A packaged semiconductor includes inner bond fingers, at least first and second semiconductor dies, and an interposer. The packaged semiconductor further includes wiring between the first and second semiconductor dies and the inner bond fingers, wiring between the interposer and the inner bond fingers, and wiring between the interposer and the first and second semiconductor dies. The wiring between the interposer and the first and second semiconductor dies thereby reduces the count of inner bond fingers needed for the wiring between the first and second semiconductor dies and the inner bond fingers. The interposer further provides indirect access to the inner bond fingers when the inner bond fingers are inaccessible by the first and second semiconductor dies.

Abstract: A method comprises attaching a first side of an interposer on a carrier wafer. The first side of the interposer comprises a plurality of bumps. The carrier wafer comprises a plurality of cavities formed in the carrier wafer. Each bump on the first side of the interposer can fit into its corresponding cavity on the carrier wafer. Subsequently, the method comprises attaching a semiconductor die on the second side of the interposer to form a wafer stack, detaching the wafer stack from the carrier wafer and attaching the wafer stack to a substrate.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package base having an inward base side and an outward base side; mounting a device over the inward base side and connected to the outward base side; connecting a silicon interposer having a through silicon via to the device and having an external side facing away from the device; and applying an encapsulant around the device, over the package base, and over the silicon interposer with the external side substantially exposed, the encapsulant having a protrusion over the outward base side.

Abstract: A semiconductor packaging method includes providing a substrate having a plurality of connection pads; mounting a chip on the substrate, wherein the chip comprises a plurality of copper-containing bumps directly coupled to the connection pads, and each of the copper-containing bumps comprises a ring surface; forming an anti-dissociation gel between the substrate and the chip, wherein the anti-dissociation gel comprises a plurality of anti-dissociation substances, and the ring surfaces of the copper-containing bumps are covered by the anti-dissociation substances.

Abstract: A component includes a substrate, a chip and a frame. The frame is bonded to the substrate and the chip rests on the frame. A sealing layer on parts of the frame and the chip is designed to hermetically seal a volume enclosed by the substrate, the chip and the metal frame.

Abstract: A method for forming a semiconductor structure. A semiconductor substrate including a plurality of dies mounted thereon is provided. The substrate includes a first portion proximate to the dies and a second portion distal to the dies. In some embodiments, the first portion may include front side metallization. The second portion of the substrate is thinned and a plurality of conductive through substrate vias (TSVs) is formed in the second portion of the substrate after the thinning operation. Prior to thinning, the second portion may not contain metallization. In one embodiment, the substrate may be a silicon interposer. Further back side metallization may be formed to electrically connect the TSVs to other packaging substrates or printed circuit boards.

Abstract: A semiconductor substrate having a first lateral dimension is combined with a flexible film piece having a second lateral dimension by arranging the semiconductor substrate in a recess of the film piece. The semiconductor substrate has circuit structures produced using lithography process steps. After the semiconductor substrate has been arranged in the recess of the film piece, a patterned layer of an electrically conductive material is produced above the semiconductor substrate and the film piece using lithography process steps. The patterned layer extends from the semiconductor substrate up to the flexible film piece and forms a number of electrically conductive contact tracks between the semiconductor substrate and the film piece.

Abstract: Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die.

Abstract: A semiconductor package includes a substrate having an insulation layer. The insulation layer has a first region having a first surface roughness and a second region having a second surface roughness. A semiconductor chip is mounted in the first region, and an underfill resin solution is filled into the space between the semiconductor chip and the insulation layer. The roughness of the second region prevents the underfill resin from flowing out from the semiconductor chip to thereby reduce a size of the semiconductor package.