And Encapsulating Patents (Class 438/126)
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Patent number: 8716068Abstract: In fabricating a semiconductor device first layers are formed of sintered bondable and solderable metal on a carrier strip. The first layers are patterned into first pads and second pads. A set of first pads is surrounding each second pad. The first pads are spaced from the second pad by gaps. The patterned layers are formed of agglomerate metal vertically on the first layers of sintered bondable and solderable metal of the first pads and of the second pad. The second layers are formed of sintered bondable and solderable metal vertically on the layers of agglomerate metal of the first pads.Type: GrantFiled: September 27, 2013Date of Patent: May 6, 2014Assignee: Texas Instruments IncorporatedInventors: Darvin R. Edwards, Siva P. Gurrum, Masood Murtuza, Matthew D. Romig, Kazunori Hayata
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Patent number: 8716767Abstract: A compliant bipolar micro device transfer head array and method of forming a compliant bipolar micro device transfer array from an SOI substrate are described. In an embodiment, a compliant bipolar micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include first and second silicon interconnects, and first and second arrays of silicon electrodes electrically connected with the first and second silicon interconnects and deflectable into one or more cavities between the base substrate and the silicon electrodes.Type: GrantFiled: October 25, 2013Date of Patent: May 6, 2014Assignee: LuxVue Technology CorporationInventors: Dariusz Golda, Andreas Bibl
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Publication number: 20140117555Abstract: An integrated circuit includes a substrate having at least one depression on a top surface. At least one solder bump is disposed over the substrate. A die is disposed over the at least one solder bump and electrically connected with the substrate through the at least one solder bump. An underfill surrounds the at least one solder bump and is formed between the substrate and the die. The at least one depression is disposed around the underfill to keep any spillover from the underfill in the at least one depression.Type: ApplicationFiled: December 21, 2012Publication date: May 1, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Wei Liang, Chun-Lin Lu, Kai-Chiang Wu, Ching-Feng Yang, Ming-Kai Liu, Chia-Chun Miao, Yen-Ping Wang
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Publication number: 20140117098Abstract: A method for manufacturing a portable data carrier includes the steps of: providing a carrier band having an upper side and a lower side disposed opposite the upper side including a contact field formed with at least one contact area; arranging a semiconductor circuit on the lower side of the carrier band and electroconductively connected with the corresponding contact area; and carrying out an injection molding process on the lower side a potting compound formed around the semiconductor circuit and having outer dimensions according to a portable data carrier standard specification. An injection channel for injecting the potting compound is arranged on a side of the potting compound mold parallel to the lower side, and after the injection of the potting compound a depression remains in the finished data carrier due to the injection channel. A portable data carrier includes the features and is used as a subscriber identity module.Type: ApplicationFiled: June 14, 2012Publication date: May 1, 2014Inventors: Bernhard Büttner, Thomas Tarantino, Robert Griesmeier
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Patent number: 8709865Abstract: A packaging substrate having a through-holed interposer embedded therein and a fabrication method of the packaging substrate are provided, where the packaging substrate includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer.Type: GrantFiled: August 17, 2012Date of Patent: April 29, 2014Assignee: Unimicron Technology CorporationInventors: Yu-Shan Hu, Dyi-Chung Hu, Tzyy-Jang Tseng
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Publication number: 20140110836Abstract: Packaging devices, methods of manufacture thereof, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging device includes a substrate including an integrated circuit die mounting region. An underfill material flow prevention feature is disposed around the integrated circuit die mounting region.Type: ApplicationFiled: October 19, 2012Publication date: April 24, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
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Patent number: 8703599Abstract: Microelectronic devices having intermediate contacts, and associated methods of packaging microelectronic devices with intermediate contacts, are disclosed herein. A packaged microelectronic device configured in accordance with one embodiment of the invention includes a microelectronic die attached to an interconnecting substrate. The microelectronic die includes an integrated circuit electrically coupled to a plurality of terminals. Each of the terminals is electrically coupled to a corresponding first contact on the die with an individual wire-bond. Each of the first contacts on the die is electrically coupled to a corresponding second contact on the interconnecting substrate by a conductive coupler such as a solder ball.Type: GrantFiled: November 27, 2012Date of Patent: April 22, 2014Assignee: Micron Technology, Inc.Inventor: Setho Sing Fee
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Patent number: 8704214Abstract: An organic light emitting diode (OLED) display a includes: a substrate; an organic light emitting element on the substrate and including a first electrode, a light emission layer, and a second electrode; and an encapsulation layer on the substrate while covering the organic light emitting element. The encapsulation layer includes an organic layer and an inorganic layer. A mixed area, where organic materials forming the organic layer and inorganic materials forming the inorganic layer co-exist along a plane direction of the encapsulation layer, is formed at the boundary between the organic layer and the inorganic layer.Type: GrantFiled: November 16, 2011Date of Patent: April 22, 2014Assignee: Samsung Display Co., Ltd.Inventors: So-Young Lee, Yoon-Hyeung Cho, Min-Ho Oh, Byoung-Duk Lee, Sang-Hwan Cho, Yong-Tak Kim, Yun-Ah Chung, Seung-Yong Song, Jong-Hyuk Lee
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Publication number: 20140103521Abstract: An electronic device may include a bottom interconnect layer and an integrated circuit (IC) carried by the bottom interconnect layer. The electronic device may further include an encapsulation material on the bottom interconnect layer and laterally surrounding the IC. The electronic device may further include electrically conductive pillars on the bottom interconnect layer extending through the encapsulation material. At least one electrically conductive pillar and adjacent portions of encapsulation material may have a reduced height with respect to adjacent portions of the IC and the encapsulation material and may define at least one contact recess. The at least one contact recess may be spaced inwardly from a periphery of the encapsulation material.Type: ApplicationFiled: October 16, 2012Publication date: April 17, 2014Applicant: STMicroelectronics Pte. LtdInventors: Yonggang Jin, How Yuan HWANG
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Publication number: 20140106511Abstract: Embodiments of the present disclosure flip-chip packaging techniques and configurations. An apparatus may include a package substrate having a plurality of pads formed on the package substrate, the plurality of pads being configured to receive a corresponding plurality of interconnect structures formed on a die and a fluxing underfill material disposed on the package substrate, the fluxing underfill material comprising a fluxing agent configured to facilitate formation of solder bonds between individual interconnect structures of the plurality of interconnect structures and individual pads of the plurality of pads and an epoxy material configured to harden during formation of the solder bonds to mechanically strengthen the solder bonds. Other embodiments may also be described and/or claimed.Type: ApplicationFiled: December 16, 2013Publication date: April 17, 2014Applicant: TriQuint Semiconductor, Inc.Inventors: Frank J. Juskey, Robert C. Hartmann, Paul D. Bantz
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Patent number: 8698288Abstract: A semiconductor device includes first and second flexible substrates each with first and second peripheral edges. First and second dies are attached on respective surfaces of the flexible substrates and are each respectively electrically connected to first and second metal traces. A first crimping structure electrically connects the first metal traces to the second metal traces and crimps together the first peripheral edges of the first and second substrates. A second crimping structure electrically connects the first metal traces to the second metal traces and crimps together the second peripheral edges of the first and second substrates.Type: GrantFiled: May 23, 2013Date of Patent: April 15, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Boon Yew Low, Navas Khan Oratti Kalandar, Sharon Huey Lin Tay
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Patent number: 8692265Abstract: A lighting device is provided. The lighting device comprises a first substrate and a plurality of second substrates. The plurality of second substrates are separately and electrically connected to the first substrate and comprise a light emitting device.Type: GrantFiled: July 10, 2012Date of Patent: April 8, 2014Assignee: LG Innotek Co., Ltd.Inventor: Jun Seok Park
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Patent number: 8680585Abstract: There is provided a light emitting diode package and a method of manufacturing the same. A light emitting diode package according to an aspect of the invention may include: an LED chip; a body part having the LED chip mounted thereon; a pair of reflective parts extending from the body part to face each other while interposing the LED chip therebetween, and reflecting light emitted from the LED chip; and a molding part provided between the pair of reflective parts to encapsulate the LED chip and having a top surface whose central region is curved inwards.Type: GrantFiled: November 11, 2010Date of Patent: March 25, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Young Sam Park, Hun Joo Hahm
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Patent number: 8680665Abstract: A method and encapsulation of a sensitive mechanical component structure in one embodiment includes a semiconductor substrate, and a film covering a component structure on the substrate, said film including at least one polymer layer, and at least one cavity formed between the component structure and the film, wherein at least one through contact penetrates through the film.Type: GrantFiled: July 15, 2009Date of Patent: March 25, 2014Assignee: Robert Bosch GmbHInventor: Peter Rothacher
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Publication number: 20140077355Abstract: A semiconductor package device that includes an integrated circuit device package having a storage circuitry is disclosed. In an implementation, the semiconductor package device includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes one or more integrated circuits formed proximal to (e.g., adjacent to, in, or on) the first surface. The semiconductor package device also includes an integrated circuit device disposed over the second surface, the integrated circuit device including storage circuitry for storing sensitive data. In one or more implementations, the semiconductor package device includes a through-substrate via that furnishes an electrical connection to the integrated circuit package. The semiconductor package device also includes an encapsulation structure disposed over the second surface and at least substantially encapsulates the integrated circuit device package.Type: ApplicationFiled: September 14, 2012Publication date: March 20, 2014Applicant: MAXIM INTEGRATED PRODUCTS, INC.Inventors: Peter R. Harper, Arkadii V. Samoilov, Don Dias
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Publication number: 20140077366Abstract: A wafer level fan-out package with a fiducial die is disclosed and may include a semiconductor die and a transparent fiducial die both encapsulated in a molding compound resin, passivation layers on an upper surface and a lower surface of the molding compound resin except where redistribution layers are formed on upper and lower surfaces of the molding compound resin, and a metal pattern on a lower surface of the transparent fiducial die that is visible through an exposed upper surface of the transparent fiducial die. The pattern may comprise a standard coordinate for forming a through mold via utilizing laser drilling.Type: ApplicationFiled: August 9, 2013Publication date: March 20, 2014Inventors: Sung Kyu Kim, Jin Young Kim, Yoon Joo Kim, Jin Han Kim, Seung Jae Lee, Se Woong Cha, Jae Hun Bae, Dong Jin Kim, Won Myoung Ki
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Patent number: 8669143Abstract: Methods for manufacturing packaged devices are disclosed. In one embodiment a method includes encapsulating a first semiconductor chip with a first encapsulant, wherein the first encapsulant includes a cavity on a first main surface, mounting an electrical component on a carrier, the electrical component being a MEMS device, and placing the carrier on the first main surface of the first encapsulant such that the electrical component is enclosed by the cavity.Type: GrantFiled: December 7, 2012Date of Patent: March 11, 2014Assignee: Infineon Technologies AGInventor: Horst Theuss
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Patent number: 8669138Abstract: A substrate and a semiconductor chip are connected by means of flip-chip interconnection. Around connecting pads of the substrate and input/output terminals of the semiconductor chip, an underfill material is injected. The underfill material is a composite material of filler and resin. Also, a first main surface of the substrate, which is not covered with the underfill material, and the side surfaces of the semiconductor chip are encapsulated with a molding material. The molding material is a composite material of filler and resin. An integrated body of the substrate and the semiconductor chip, which are covered with the molding material, is thinned from above and below.Type: GrantFiled: July 13, 2012Date of Patent: March 11, 2014Assignee: NEC CorporationInventors: Akinobu Shibuya, Koichi Takemura, Akira Ouchi, Tomoo Murakami
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Publication number: 20140061892Abstract: A packaged device, wherein at least one sensitive portion of a chip is enclosed in a chamber formed by a package. The package has an air-permeable area having a plurality of holes and a liquid-repellent structure so as to enable passage of air between an external environment and the chamber and block the passage of liquids.Type: ApplicationFiled: August 29, 2013Publication date: March 6, 2014Applicant: STMicroelectronics S.r.l.Inventors: Federico Giovanni Ziglioli, Fulvio Vittorio Fontana, Luca Maggi
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Publication number: 20140061891Abstract: Disclosed herein are a semiconductor chip package and a manufacturing method thereof. The manufacturing method of the semiconductor chip package includes: a) mounting a semiconductor chip on a printed circuit board (PCB); b) inserting a warpage suppressing reinforcement member into an inner ceiling of a mold manufactured in order to package the PCB having the semiconductor chip mounted thereon; c) combining the mold having the warpage suppressing reinforcement member inserted into the ceiling thereof with the upper surface of the PCB so as to surround the PCB having the semiconductor chip mounted thereon; d) injection-molding and filling a molding material in the mold, and hardening the molding material by applying heat, and e) hardening the molding material and then removing the mold to complete the semiconductor chip package.Type: ApplicationFiled: March 13, 2013Publication date: March 6, 2014Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Po Chul KIM, Kyung Ho Lee, Seung Wan Woo, Young Nam Hwang, Suk Jin Ham
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Patent number: 8664752Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.Type: GrantFiled: March 26, 2012Date of Patent: March 4, 2014Assignee: Fairchild Semiconductor CorporationInventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, David Chong, Tan Teik Keng, Shibaek Nam, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Lay Yeap Lim, Byoung-Ok Lee
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Publication number: 20140054802Abstract: A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A patterned trench is formed in the first insulating layer. A conductive ink is deposited in the patterned trench by disposing a stencil over the first insulating layer with an opening aligned with the patterned trench and depositing the conductive ink through the opening in the stencil into the patterned trench. Alternatively, the conductive ink is deposited by dispensing the conductive ink through a nozzle into the patterned trench. The conductive ink is cured by ultraviolet light at room temperature. A second insulating layer is formed over the first insulating layer and conductive ink. An interconnect structure is formed over the conductive ink. An encapsulant can be deposited around the semiconductor die. The patterned trench is formed in the encapsulant and the conductive ink is deposited in the patterned trench in the encapsulant.Type: ApplicationFiled: March 12, 2013Publication date: February 27, 2014Applicant: STATS CHIPPAC, LTD.Inventors: Il Kwon Shim, Jun Mo Koo
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Patent number: 8659175Abstract: An integrated circuit package system is provided including mounting a first integrated circuit device over a carrier, mounting a second integrated circuit device having an adhesive spacer over the first integrated circuit device in an offset configuration, connecting a first internal interconnect between the carrier and the first integrated circuit device with the first internal interconnect within the adhesive spacer, connecting a second internal interconnect between the carrier and the second integrated circuit device, and encapsulating the first integrated circuit device, the second integrated circuit device, the first internal interconnect and the second internal interconnect.Type: GrantFiled: June 12, 2007Date of Patent: February 25, 2014Assignee: Stats Chippac Ltd.Inventors: Jong Wook Ju, Taeg Ki Lim, Hyun Joung Kim
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Publication number: 20140048960Abstract: There are provided a package substrate, a manufacturing method thereof, and a mold therefor. The method of manufacturing a package substrate includes: preparing a chip component and a substrate; mounting the chip component on a main surface of the substrate; preparing a mold having a cavity and protrusions formed on a ceiling surface thereof; disposing the substrate on a bottom surface of the mold such that the chip component is positioned within the cavity; and forming a resin sealing body that collectively hermetically seals the chip component and the main surface of the substrate by injecting a pressurized liquid resin into the cavity.Type: ApplicationFiled: March 14, 2013Publication date: February 20, 2014Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventor: Zin O YOO
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Patent number: 8653655Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).Type: GrantFiled: August 6, 2013Date of Patent: February 18, 2014Assignee: Renesas Electronics CorporationInventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
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Patent number: 8652880Abstract: To provide a technique that can improve the data retention characteristic of an MRAM device by improving the resistance against an external magnetic field in a semiconductor device including the MRAM device. A first magnetic shield material is disposed over a die pad via a first die attach film. Then, a semiconductor chip is mounted over the first magnetic shield material via a second die attach film. Furthermore, a second magnetic shield material is disposed over the semiconductor chip via a third die attach film. That is, the semiconductor chip is disposed so as to be sandwiched by the first magnetic shield material and the second magnetic shield material. At this time, while the planar area of the second magnetic shield material is smaller than that of the first magnetic shield material, the thickness of the second magnetic shield material is thicker than that of the first magnetic shield material.Type: GrantFiled: August 10, 2012Date of Patent: February 18, 2014Assignee: Renesas Electronics CorporationInventors: Koji Bando, Kazuyuki Misumi, Tatsuhiko Akiyama, Naoki Izumi, Akira Yamazaki
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Patent number: 8642388Abstract: A method for manufacturing LEDs includes following steps: forming circuit structures on a substrate, each circuit structure having a first metal layer and a second metal layer formed on opposite surfaces of the substrate and a connecting section interconnecting the first and second metal layers; cutting through each circuit structure along a middle of the connecting section to form first and second electrical connecting portions insulated from each other via a gap therebetween; arranging LED chips on the substrate and electrically connecting the LED chips to the first and second electrical connecting portions; forming an encapsulation on the substrate to cover the LED chips; and cutting through the substrate and the encapsulation between the first and second electrical connecting portions of neighboring circuit structures to obtain the LEDs.Type: GrantFiled: December 21, 2011Date of Patent: February 4, 2014Assignee: Advanced Optoelectronics Technology, Inc.Inventor: Chao-Hsiung Chang
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Patent number: 8643140Abstract: A suspended beam includes a substrate, a main body and a first metal line structure. A first end of the main body is fixed onto the substrate. A second end of the main body is suspended. The first metal line structure is embedded in the main body. The width of the first metal line structure is smaller than the width of the main body.Type: GrantFiled: July 11, 2011Date of Patent: February 4, 2014Assignee: United Microelectronics Corp.Inventor: Chin-Sheng Yang
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Patent number: 8642387Abstract: Described herein is a stacked package using laser direct structuring. The stacked package includes a die attached to a substrate. The die is encapsulated with a laser direct structuring mold material. The laser direct structuring mold material is laser activated to form circuit traces on the top and side surfaces of the laser direct structuring mold material. The circuit traces then undergo metallization. A package is then attached to the metalized circuit traces and is electrically connected to the substrate via the metalized circuit traces.Type: GrantFiled: November 1, 2011Date of Patent: February 4, 2014Assignee: Flextronics AP, LLCInventors: Samuel Tam, Bryan Lee Sik Pong, Dick Pang
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Patent number: 8642469Abstract: A semiconductor wafer has a contact pad. A first insulating layer is formed over the wafer. A second insulating layer is formed over the first insulating layer and contact pad. A portion of the second insulating layer is removed to expose the contact pad. A first UBM layer is formed over and follows a contour of the second insulating layer and contact pad to create a well over the contact pad. A first buffer layer is formed in the well over the first UBM layer and the contact pad. A second UBM layer is formed over the first UBM layer and first buffer layer. A third UBM layer is formed over the second UBM layer. A bump is formed over the third UBM layer. The first buffer layer reduces stress on the bump and contact pad. A second buffer layer can be formed between the second and third UBM layers.Type: GrantFiled: February 21, 2011Date of Patent: February 4, 2014Assignee: STATS ChipPAC, Ltd.Inventors: DaeSik Choi, JoonYoung Choi, Wonll Kwon
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Publication number: 20140029234Abstract: A surface mount packaging structure that yields improved thermo-mechanical reliability and more robust second-level package interconnections is disclosed. The surface mount packaging structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level metal interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer on a side opposite the semiconductor devices, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to the first surface of a multi-layer substrate structure, with a dielectric material positioned between the dielectric layer and the multi-layer substrate structure to fill in gaps in the surface-mount structure and provide additional structural integrity thereto.Type: ApplicationFiled: July 30, 2012Publication date: January 30, 2014Inventors: Shakti Singh Chauhan, Arun Virupaksha Gowda, Paul Alan McConnelee
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Publication number: 20140027901Abstract: A device includes a device die and a plurality of metal posts at a surface of the device die and electrically coupled to the device die. The device further includes a plurality of through-assembly vias (TAVs), a dam member between the device die and the plurality of TAVs, and a polymer layer encompassing the device die, the plurality of metal posts, the plurality of TAVs, and the dam member.Type: ApplicationFiled: July 26, 2012Publication date: January 30, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Chang Hu, Ching-Wen Hsiao, Chen-Shien Chen
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Publication number: 20140029210Abstract: A surface-mount package structure for reducing the ingress of moisture and gases thereto is disclosed. The surface-mount structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to a substrate structure, with a dielectric material positioned between the dielectric layer and the substrate structure to fill in gaps in the surface-mount structure.Type: ApplicationFiled: July 30, 2012Publication date: January 30, 2014Inventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Ri-an Zhao, Shakti Singh Chauhan
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Patent number: 8637969Abstract: A method of forming a semiconductor package having a large capacity and a reduced or minimized volume includes: attaching a semiconductor substrate on a support substrate using an adhesive layer, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region, wherein first and second ones of the plurality of first semiconductor chips are separated each other by the chip cutting region, and the semiconductor substrate includes a first surface on which an active area is formed and a second surface opposite to the first surface; forming a first cutting groove having a first kerf width, between the first and second ones of the plurality of first semiconductor chips, so that the semiconductor substrate is separated into a plurality of first semiconductor chips; attaching a plurality of second semiconductor chips corresponding to the first semiconductor chips, respectively, to the plurality of first semiconductor chips; forming a molding layer so as to fill the firstType: GrantFiled: June 3, 2013Date of Patent: January 28, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Teak-hoon Lee, Won-keun Kim, Dong-hyeon Jang, Ho-geon Song, Sung-jun Im
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Patent number: 8637971Abstract: A semiconductor device includes a housing made of a thermoplastic resin and having an internal space that is opened on one side and an inner wall portion that has an inner peripheral surface defining the internal space; and a core portion engaged in the internal space of the housing. The core portion includes a substrate, a semiconductor element mounted on the substrate, a wire electrically connecting the substrate and the semiconductor element, and a mold resin sealing the substrate, the semiconductor element and the wire. The core portion has a side surface provided with a convex portion that is in contact with the inner peripheral surface of the inner wall portion. Accordingly, a semiconductor device allowing a lengthened life and improved productivity, and a method of manufacturing the semiconductor device can be provided.Type: GrantFiled: January 10, 2013Date of Patent: January 28, 2014Assignee: Mitsubishi Electric CorporationInventor: Hiroshi Yoshida
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Patent number: 8637977Abstract: A method and apparatus of packaging a semiconductor device with a clip is disclosed. The clip defines a first contact region and a second contact region on a same face of the at least one clip. The chip defines a first face, and a second face opposite to the first face, the first contact region being attached to the first face of the chip and the second contact region being located within a same plane with the second face of the clip.Type: GrantFiled: June 27, 2013Date of Patent: January 28, 2014Assignee: Infineon Technologies AGInventors: Boon Huat Lim, Chee Chian Lim, Yoke Chin Goh
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Publication number: 20140021621Abstract: A packaged semiconductor die has a die support mounting surface mounted to a die support having external connectors. A die connection pad surface opposite to die supporting mount surface has associated die connection pads that are circuit nodes of the semiconductor die. The die connection pad surface also has a power rail pad. The power rail pad has a surface area larger than surface areas of the die connection pads. Bond wires electrically couple the power rail pad to two or more of the die connection pads.Type: ApplicationFiled: July 17, 2012Publication date: January 23, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Boon Yew Low, Navas Khan Oratti Kalandar, Lan Chu Tan
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Publication number: 20140021638Abstract: A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects.Type: ApplicationFiled: July 18, 2012Publication date: January 23, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Joachim Mahler, Edward Fuergut, Khalil Hosseini, Georg Meyer-Berg
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Publication number: 20140021264Abstract: In various aspects of the disclosure, a chip card module is provided. The chip card module may include a flexible substrate having a metallization on a first and second major surface, or side, thereof. An integrated circuit affixed to the second side is oriented with chip pads facing away from the substrate. Wire bonds may connect the chip pads to the metallizations.Type: ApplicationFiled: July 19, 2012Publication date: January 23, 2014Applicant: Infineon Technologies AGInventors: Frank PUESCHNER, Jens POHL, Juergen HOEGERL, Wolfgang SCHINDLER
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Publication number: 20140021583Abstract: A package includes a die, an encapsulant, and a capacitor. The package has a package first side and a package second side. The die has a die first side corresponding to the package first side, and has a die second side corresponding to the package second side. The die first side is opposite the die second side. The encapsulant surrounds the die. The capacitor includes a first plate and a second plate in the encapsulant, and opposing surfaces of the first plate and the second plate extend in a direction from the package first side to the package second side. The external conductive connectors are attached to at least one of the package first side and the package second side.Type: ApplicationFiled: July 18, 2012Publication date: January 23, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sut-I Lo, Ching-Wen Hsiao, Hsu-Hsien Chen, Chen-Shien Chen
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Patent number: 8633602Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The method includes: stacking and adhering a second semiconductor chip on a first semiconductor chip via an adhesive layer; adjusting at least one of an elasticity modulus of the adhesive layer, a sink amount of the adhesive layer, a thickness of a protective film at a surface of the first chip, and an elasticity modulus of the protective film such that “y” in a following formula is 70 or less; and sealing the chips by a molding resin with filler particles. y=74.7?82.7a1+273.2a2?9882a3+65.8a4 a1: a logarithm of the modulus of elasticity [MPa] of the adhesive layer a2: the sink amount [mm] of the adhesive layer a3: the thickness [mm] of the protective film a4: a logarithm of the modulus of elasticity [MPa] of the protective film.Type: GrantFiled: March 15, 2012Date of Patent: January 21, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Nobuhito Suzuya, Atsushi Yoshimura, Hideko Mukaida
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Patent number: 8633057Abstract: Provided is a semiconductor package and a method of fabricating the same. The semiconductor package includes: a package body including a plurality of sheets; semiconductor chips mounted in the package body; and an external connection terminal provided on a first side of the package body, wherein the sheets are stacked in a parallel direction to the first side.Type: GrantFiled: May 2, 2013Date of Patent: January 21, 2014Assignee: Electronics and Telecommunications Research InstituteInventor: Woojin Chang
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Patent number: 8629001Abstract: A semiconductor device includes: a first semiconductor element having a first terminal surface on which a first terminal is disposed and a first rear surface on which no terminal is disposed; a second semiconductor element having a second terminal surface on which a second terminal is disposed and a second rear surface on which no terminal is disposed, the second rear surface being bonded to the first rear surface; a terminal member having a surface set substantially flush with the second terminal surface; and a conductive wire connecting the terminal member and the first terminal.Type: GrantFiled: June 15, 2010Date of Patent: January 14, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Koichi Sugihara
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Patent number: 8623707Abstract: To reduce the thermal stresses that may be caused by a difference in thermal expansion coefficients between a molded casing and an active side of a semiconductor device embedded in the molded casing, and thus reduce the number of corresponding failures caused by the thermal stresses, the active side of the semiconductor device is arranged face-down, towards a substrate supporting the semiconductor device. The semiconductor device includes a through via that electrically connects the active side of the semiconductor device to a passive side of the semiconductor device. A wire bond electrically connects the passive side of the semiconductor device to the substrate. To increase the dissipation of heat generated in the semiconductor device, a thermally conductive slug may be disposed in the substrate, and the active side of the semiconductor device may be attached to the thermally conductive slug.Type: GrantFiled: March 26, 2013Date of Patent: January 7, 2014Assignee: Cisco Technology, Inc.Inventors: Andrew V. Kearney, Peng Su
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Publication number: 20140001632Abstract: A package structure includes a package substrate having a top surface and a bottom surface. A semiconductor die having a top surface and a bottom surface. The semiconductor die is mounted to the package substrate. The bottom surface of the semiconductor die is adjacent to the top surface of the package substrate. An air gap is between the bottom surface of the package substrate and the bottom surface of semiconductor die.Type: ApplicationFiled: June 29, 2012Publication date: January 2, 2014Inventors: Trent S. Uehling, Burton J. Carpenter, Brett P. Wilkerson
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Publication number: 20140001623Abstract: A microelectronic structure comprising a microelectronic package that includes at least one microelectronic device attached to a microelectronic interposer, wherein the microelectronic package is mounted to a microelectronic substrate, such that the microelectronic device is disposed between and in electrical communication with both the microelectronic interposer and the microelectronic substrate.Type: ApplicationFiled: June 28, 2012Publication date: January 2, 2014Inventor: PRAMOD MALATKAR
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Publication number: 20140001622Abstract: A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.Type: ApplicationFiled: June 27, 2012Publication date: January 2, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Michael Bauer, Alfred Haimerl, Angela Kessler, Wolfgang Schober
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Patent number: 8617926Abstract: A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.Type: GrantFiled: September 9, 2010Date of Patent: December 31, 2013Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Michael Z. Su, Gamal Refai-Ahmed, Bryan Black
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Patent number: 8617935Abstract: A mechanism for accurate alignment of semiconductor package back side interconnect processing is provided. As semiconductor die are placed in position for an encapsulated panel, two or more alignment die having fiducial markings formed on the back, or non-active, side of those die are also placed in the panel. Once all the die and other components have been placed for the panel, the panel is encapsulated using an encapsulant. Excess encapsulant, if any, is removed by a process such as backgrinding. The back grinding process exposes the back side of the alignment die and the fiducial features on those alignment die. The fiducial features on the alignment die can then be used for alignment of backside processing operations on the panel.Type: GrantFiled: August 30, 2011Date of Patent: December 31, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Jianwen Xu, Zhiwei Gong, Scott M. Hayes
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Publication number: 20130341786Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. In one embodiment, a PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal pillars are coupled to the first packaged die. The metal pillars have a first portion proximate the first packaged die and a second portion disposed over the first portion. Each of the metal pillars is coupled to a solder joint proximate the second packaged die.Type: ApplicationFiled: June 25, 2012Publication date: December 26, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Lei Hsu, Chung-Shi Liu, De-Yuan Lu, Ming-Che Ho, Yu-Feng Chen