With Electrical Circuit Layout Patents (Class 438/129)
  • Patent number: 12369405
    Abstract: In a semiconductor integrated circuit device, first and second IO cell rows are placed in an IO region on a chip. IO cells in the first IO cell row are larger in plane area than IO cells in the second IO cell row. Pads connected to the IO cells in the first IO cell row are located closer to an outer edge of the chip than any pads connected to the IO cells in the second IO cell row.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: July 22, 2025
    Assignee: SOCIONEXT INC.
    Inventors: Taro Fukunaga, Masahisa Iida, Toshihiro Nakamura
  • Patent number: 12283530
    Abstract: A method of manufacturing semiconductor testing structure includes providing a substrate; forming a first metal layer on the substrate, wherein the first metal layer comprises a plurality of fingers extending along a first direction; forming a dielectric structure on the first metal layer; and forming a plurality of second metal layers on the dielectric structure.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: April 22, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chun-Shun Huang
  • Patent number: 12266402
    Abstract: A phase change memory element has a memory region, a first electrode and a second electrode. The memory region is arranged between the first and the second electrodes and has a bulk zone and an active zone. The memory region is made of a germanium, antimony and tellurium based alloy, wherein germanium is in a higher percentage than antimony and tellurium in the bulk zone of the memory region. The active zone is configured to switch between a first stable state associated with a first memory logic level and a second stable state associated with a second memory logic level. The active zone has, in the first stable state, a uniform, amorphous structure and, in the second stable state, a differential polycrystalline structure including a first portion, having a first stoichiometry, and a second portion, having a second stoichiometry different from the first stoichiometry.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: April 1, 2025
    Assignee: STMicroelectronics S.r.l.
    Inventors: Elisa Petroni, Andrea Redaelli
  • Patent number: 12255257
    Abstract: A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.
    Type: Grant
    Filed: March 7, 2024
    Date of Patent: March 18, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Mongsong Liang, Sung-Dae Suk, Geumjong Bae
  • Patent number: 12219841
    Abstract: What is disclosed is structures and methods to integrate microdevices into system or receiver substrates. The integration of microdevices is facilitated by adding staging pads to microdevices before or after transferring. Creating stages after the transfer of a first microdevice to a substrate for the subsequent microdevice transfer to the first (or the second) microdevice transfer. The stage improves the surface profile of the substrate so that next microdevice can be transferred without the first microdevice on the substrate get damaged by or interfere with the surface of the donor or transfer head. Some embodiments further relate to tiled display device and more particularly, to stacking tiles to a backplane to form the tiled display device.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: February 4, 2025
    Assignee: VueReal Inc.
    Inventors: Gholamreza Chaji, Won Kyu Ha, Aaron Daniel Trent Wiersma, Ehsanollah Fathi
  • Patent number: 12204841
    Abstract: A modeling method includes the following: acquiring electrical parameters of each sub-structure in a through silicon via (TSV) structure; obtaining an electrical topology network model according to a connection relationship of each TSV structure between two dies; and obtaining a simulation model for simulation based on the electrical topology network model and the electrical parameters.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: January 21, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Kun Weng
  • Patent number: 12190034
    Abstract: A logic circuit (for providing a multibit flip-flop (MBFF) function) includes: a first inverter to receive a clock signal and generate a corresponding clock_bar signal; a second inverter to receive the clock_bar signal and generate a corresponding clock_bar_bar signal; a third inverter to receive a control signal and generate a corresponding control_bar signal; and a series-chain of 1-bit transfer flip-flop (TXFF) circuits, each including: a NAND circuit to receive data signals; and a 1-bit transmit gate flip-flop (TGFF) circuit to output signals Q and q, and receive an output of the NAND circuit, the signal q from the TGFF circuit of a preceding TXFF circuit in the series-chain, the clock_bar and clock_bar_bar signals, and the control and control_bar signals; and the first transfer TXFF circuit in the series-chain being configured to receive a start signal in place of the signal q from an otherwise preceding TGFF circuit.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: January 7, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Lin Liu, Jerry Chang-Jui Kao, Wei-Hsiang Ma, Lee-Chung Lu, Fong-Yuan Chang, Sheng-Hsiung Chen, Shang-Chih Hsieh
  • Patent number: 12082417
    Abstract: A 3-dimensional (3D) flash memory having a structure that mitigates an interference phenomenon between neighboring cells in an oxide-nitride-oxide (ONO) layer, which is a charge storage layer, and a method of manufacturing the same are provided.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: September 3, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Yun Heub Song
  • Patent number: 12074056
    Abstract: A method of forming a substrate comprises providing a receiver substrate and a donor substrate successively comprising: a carrier substrate, a sacrificial layer, which can be selectively etched in relation to an active layer, and a silicon oxide layer, which is arranged on the active layer. A cavity is formed in the oxide layer to form a first portion that has a first thickness and a second portion that has a second thickness greater than the first thickness. The cavity is filled with a polycrystalline silicon filling layer to form a second free surface that is continuous and substantially planar. The receiver substrate and the donor substrate are assembled at the second free surface, and the carrier substrate is eliminated while preserving the active layer and the sacrificial layer.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: August 27, 2024
    Assignee: Soitec
    Inventor: Walter Schwarzenbach
  • Patent number: 12063782
    Abstract: Some embodiments include methods of forming integrated assemblies. A conductive structure is formed to include a semiconductor-containing material over a metal-containing material. An opening is formed to extend into the conductive structure. A conductive material is formed along a bottom of the opening. A stack of alternating first and second materials is formed over the conductive structure either before or after forming the conductive material. Insulative material and/or channel material is formed to extend through the stack to contact the conductive material. Some embodiments include integrated assemblies.
    Type: Grant
    Filed: September 9, 2022
    Date of Patent: August 13, 2024
    Inventors: John D. Hopkins, Justin D. Shepherdson, Collin Howder, Jordan D. Greenlee
  • Patent number: 12051696
    Abstract: A semiconductor device includes a substrate with a first active region; first and second active patterns extending in a first direction and spaced apart in a second direction, and each having a source pattern, a channel pattern, and a drain pattern that are sequentially stacked; first and second gate electrodes that surround the channel patterns of the first and second active patterns and extend in the first direction; an interlayer dielectric layer that covers the first and second active patterns and the first and second gate electrodes; a first active contact that penetrates the interlayer dielectric layer and is coupled to the first active region between the first and second active patterns; and a first power rail on the interlayer dielectric layer and electrically connected to the first active contact, each of the first and second active patterns including an overlapping region that vertically overlaps the first power rail.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: July 30, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Taehyung Kim, Panjae Park, Jaeseok Yang
  • Patent number: 12035541
    Abstract: A selector device includes: a first electrode; a second electrode; a selector layer that is disposed between the first electrode and the second electrode; and a stacked film that is disposed in at least one of a portion between the first electrode and the selector layer and a portion between the second electrode and the selector layer, and includes a first layer including at least one first element selected from the group consisting of carbon and metal and not including nitrogen and a second layer including nitride of the first element. The first layer is in contact with the selector layer.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: July 9, 2024
    Assignee: KIOXIA CORPORATION
    Inventor: Gu Tianyi
  • Patent number: 12032893
    Abstract: Simultaneous automatic placement and routing speeds up implementation an integrated circuit layout and improves the resulting layout such that the layout is more compact, has reduced parasitics, and has improved circuit performance characteristics (e.g., power, frequency, propagation delay, gain, and stability). A technique generates solutions based on random normalized polish expression, and includes cost considerations based on routing of interconnect.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: July 9, 2024
    Assignee: Pulsic Limited
    Inventors: Mark Waller, Paul Clewes, Liang Gao, Jonathan Longrigg
  • Patent number: 12022644
    Abstract: Semiconductor structures are provided. A semiconductor structure includes a memory cell and a logic cell. The memory cell includes a latch circuit formed by two cross-coupled inverters, and a pass-gate transistor coupling an output of the latch circuit to a bit line. A first source/drain region of the pass-gate transistor is electrically connected to the bit line through a first contact over the first source/drain region and a first via over the first contact. A second source/drain region of a transistor of the logic cell is electrically connected to a local interconnect line through a second contact over the second source/drain region and a second via over the second contact. The local interconnect line and the bit line are formed in the same metal layer, and a top surface of the local interconnection line is lower than a top surface of the bit line.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 11967372
    Abstract: Methods, systems, and devices for shared decoder architecture for three-dimensional memory arrays are described. A memory device may include pillars coupled to an access line using two transistors positioned between the pillar and the access line. The gates of the two transistors may be coupled with respective gate lines coupled with circuitry configured to bias the gate line as part of an access operation for a memory cell coupled with the pillar. In some cases, the circuitry may be positioned between tiles of the memory device, at an end of one or more tiles of the memory device, between word line combs of a tile of the memory device, or a combination thereof.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: April 23, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Christophe Vincent Antoine Laurent, Andrea Martinelli, Efrem Bolandrina, Ferdinando Bedeschi
  • Patent number: 11961827
    Abstract: A semiconductor device, the device including: a first substrate; a first metal layer disposed over the first substrate; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors each include single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 200 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm, where the fourth metal layer provides a global power distribution, and where processing of the device includes use of a carrier wafer.
    Type: Grant
    Filed: December 23, 2023
    Date of Patent: April 16, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 11942558
    Abstract: A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: March 26, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Mongsong Liang, Sung-Dae Suk, Geumjong Bae
  • Patent number: 11868691
    Abstract: An integrated circuit including a standard cell includes: a plurality of first wells extending in a first horizontal direction with a first width and of a first conductivity type; and a plurality of second wells extending in the first horizontal direction with a second width and having a second conductivity type, wherein the plurality of first wells and the plurality of second wells are alternately arranged in a second horizontal direction that is orthogonal to the first horizontal direction, and when m and n are integers greater than or equal to 3, the standard cell has a length in the second horizontal direction, the length being equal to a sum of m times a half of the first width and n times a half of the second width.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: January 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Raheel Azmat, Sidharth Rastogi, Chul-hong Park, Jae-seok Yang, Kwan-young Chun
  • Patent number: 11758727
    Abstract: A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: September 12, 2023
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Eli Harari, Tianhong Yan
  • Patent number: 11755798
    Abstract: A logic circuit including first and second inverters, first and second NAND circuits, a transmission gate, and a transmission-gate-substitute (TGS) circuit, and wherein: for each of the first and second NAND circuits, a first input is configured to receive corresponding first and second data signals, and a second input is configured to receive an enable signal; the first inverter is configured to receive an output of the first NAND circuit; the transmission gate and the TGS circuit are arranged as a combination circuit which is configured to receive an output of the second NAND circuit as a data input, and outputs of the first inverter and the second NAND circuit as control inputs; the second inverter is configured to receive an output of the combination circuit; and an output of the second inverter represents one of an enable XOR (EXOR) function or an enable XNR (EXNR) function.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Lin Liu, Jerry Chang-Jui Kao, Wei-Hsiang Ma, Lee-Chung Lu, Fong-Yuan Chang, Sheng-Hsiung Chen, Shang-Chih Hsieh
  • Patent number: 11709986
    Abstract: Boundary cells may be provided. A boundary of a first functional cell of a circuit is determined. A first plurality of a first type of dummy cells are placed along a first portion of the determined boundary. The first portion extends in a first direction. Each of the first type of dummy cells comprises first pre-defined dimensions. A second plurality of a second type of dummy cells are placed along a second portion of the determined boundary. The second portion extends in a second direction. Each of the second type of dummy cells comprises second pre-defined dimensions. The second pre-defined dimensions is different than the first pre-defined dimensions.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: July 25, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Jung Chang, Min-Yuan Tsai, Wen-Ju Yang
  • Patent number: 11669482
    Abstract: A memory subsystem is provided, including a memory controller integrated circuit (IC), a memory bus and a memory IC, all which use fewer signals than common DDR type memory of the same peak bandwidth. Using no more than 22 switching signals, the subsystem can transfer data over 3000 Megabytes/second across the bus interconnecting the ICs. Signal count reduction is attained by time-multiplexing address/control commands onto at least some of the same signals used for data transfer. A single bus signal is used to initiate bus operation, and once in operation the single signal can transfer addressing and control information to the memory IC concurrent with data transfer via a serial protocol based on 16 bit samples of this single bus signal. Bus bandwidth can be scaled by adding additional data and data strobe IO signals. These additional data bus signals might be used only for data and data mask transport.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: June 6, 2023
    Assignees: Etron Technology America, Inc.
    Inventor: Richard Dewitt Crisp
  • Patent number: 11658168
    Abstract: A flash memory device includes a plurality of flash memory cell arrays, wherein: a flash memory cell array in the plurality of flash memory cell arrays comprises a plurality of layers of flash memory cell planes; and a flash memory cell plane includes a plurality of flash memory cells. The flash memory device further includes a logic circuitry coupled to the plurality of flash memory cell arrays, configured to perform operations using the plurality of flash memory cell arrays; and a sensing circuitry configured to access a corresponding flash memory cell plane among the plurality of flash memory cell planes.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: May 23, 2023
    Inventors: Fei Xue, Shuangchen Li, Dimin Niu, Hongzhong Zheng
  • Patent number: 11616016
    Abstract: A semiconductor device may include a plurality of active patterns and a plurality of gate structure on a substrate, a first insulating interlayer covering the active patterns and the gate structures, a plurality of first contact plugs extending through the first insulating interlayer, a plurality of second contact plugs extending through the first insulating interlayer, and a first connecting pattern directly contacting a sidewall of at least one contact plug selected from the first and second contact plugs. Each of gate structures may include a gate insulation layer, a gate electrode and a capping pattern. Each of first contact plugs may contact the active patterns adjacent to the gate structure. Each of the second contact plugs may contact the gate electrode in the gate structures. An upper surface of the first connecting pattern may be substantially coplanar with upper surfaces of the first and second contact plugs.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: March 28, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hwi-Chan Jun, Seul-Ki Hong, Hyun-Soo Kim, Sang-Hyun Lee
  • Patent number: 11594473
    Abstract: A 3D semiconductor device including: a first level including a single crystal silicon layer and a plurality of first transistors, the plurality of first transistors each including a single crystal channel; a first metal layer overlaying the plurality of first transistors; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; a second level is disposed above the third metal layer, where the second level includes a plurality of second transistors; a fourth metal layer disposed above the second level; and a connective path between the fourth metal layer and either the third metal layer or the second metal layer, where the connective path includes a via disposed through the second level, where the via has a diameter of less than 800 nm and greater than 5 nm, and where at least one of the plurality of second transistors includes a metal gate.
    Type: Grant
    Filed: September 9, 2022
    Date of Patent: February 28, 2023
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 11538822
    Abstract: Some embodiments include methods of forming integrated assemblies. A conductive structure is formed to include a semiconductor-containing material over a metal-containing material. An opening is formed to extend into the conductive structure. A conductive material is formed along a bottom of the opening. A stack of alternating first and second materials is formed over the conductive structure either before or after forming the conductive material. Insulative material and/or channel material is formed to extend through the stack to contact the conductive material. Some embodiments include integrated assemblies.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: December 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Justin D. Shepherdson, Collin Howder, Jordan D. Greenlee
  • Patent number: 11523504
    Abstract: Proposed is an anodic oxide film structure that includes an anodic oxide film sheet and has high strength, chemical resistance and corrosion resistance.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: December 6, 2022
    Assignee: POINT ENGINEERING CO., LTD.
    Inventors: Bum Mo Ahn, Sung Hyun Byun, Tae Hwan Song
  • Patent number: 11474788
    Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: October 18, 2022
    Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.
    Inventors: Nitin Chawla, Tanmoy Roy, Anuj Grover, Giuseppe Desoli
  • Patent number: 11374057
    Abstract: A device structure includes at least one selector device. Each selector device includes a vertical stack including, from bottom to top, a bottom electrode, a metal oxide semiconductor channel layer, and a top electrode and located over a substrate, a gate dielectric layer contacting sidewalls of the bottom electrode, the metal oxide semiconductor channel layer, and the top electrode, and a gate electrode formed within the gate dielectric layer and having a top surface that is coplanar with a top surface of the top electrode. Each top electrode or each bottom electrode of the at least one selector device may be contacted by a respective nonvolatile memory element to provide a one-selector one-resistor memory cell.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yong-Jie Wu, Yen-Chung Ho, Pin-Cheng Hsu, Mauricio Manfrini, Chung-Te Lin
  • Patent number: 11296093
    Abstract: A method for distributing deep trench (DT) capacitance in an integrated circuit (IC) design is provided. The method includes forming a placement block that includes blockages defining openings in interstitial regions among the blockages, superimposing the placement block over the IC design and providing distributed DT capacitance to the IC design. The providing of the distributed DT capacitance includes adding DT capacitance cells through the openings to portions of the IC design where there are no reserved blocks.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: April 5, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Asaf Regev, Christopher Berry, Ofer Geva, Amit Amos Atias, Timothy A. Schell
  • Patent number: 11165662
    Abstract: Provided are systems, methods, and computer products for interactive cable routing and planning optimization for customized hardware configurations. An example method includes receiving a set of cable characteristics and a set of user selections, in which the set of user selections are received via a graphical user interface (GUI). Identifying possible cabling routes for a hardware configuration based, at least in part, on available plug start and termination locations. Ranking each of the possible cabling routes based, at least in part, on a prioritized list of optimization criteria and the set of cable characteristics. Generating a suggested cabling configuration for one or more applications based, at least in part, on the set of cable characteristics, the set of user selections, and the ranking. Outputting the suggested cabling configuration to the user by at least providing a three-dimensional view of the suggested cabling configuration via the GUI.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: November 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Adam Benjamin Childers, Ryan Elsasser, Karl Owen Casserly, Richard Burton Finch, Paul Samaniego, Michael J Doscher, Mateusz Koziol
  • Patent number: 11081173
    Abstract: Embodiments disclosed herein may relate to electrically conductive vias in cross-point memory array devices. In an embodiment, the vias may be formed using a lithographic operation also utilized to form electrically conductive lines in a first electrode layer of the cross-point memory array device.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: August 3, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Stephen Tang
  • Patent number: 10884794
    Abstract: A control apparatus is communicably connected to a plurality of processing apparatuses, including a processor configured to determine whether the sum of an execution time of a first process, an execution time of a second process, and a time taken for a first processing apparatus among the plurality of processing apparatuses to rewrite a logic for executing the first process to a logic for executing the second process is equal to or smaller than a unit time; determine whether a data traffic between the plurality of processing apparatuses is equal to or smaller than a threshold when the first processing apparatus executes the first and second processes, and cause the first processing apparatus to execute the first and second processes when it is determined that the sum is equal to or smaller than the unit time and the data traffic is equal to or smaller than the threshold.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: January 5, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Noboru Yoneoka
  • Patent number: 10854592
    Abstract: A dummy cell arrangement in a semiconductor device includes a substrate with a dummy region, unit dummy cells arranged in rows and columns in the dummy region, and flexible extended dummy cells arranged in rows and columns filling up remaining dummy region. The unit dummy cell includes exactly one base dummy cell and exactly two fixed dummy cells at opposite sides of the base dummy cell in row direction or in column direction and the flexible extended dummy cell includes at least two base dummy units and a plurality of flexible dummy units at two opposite sides of the two base dummy units in row direction or in column direction. The base dummy cell consists of at least one fin, at least one gate and at least one contact, while the flexible dummy cell consists of one gate and one contact without any fin.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: December 1, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Liang Chu, Yu-Ruei Chen, Yu-Hsiang Lin
  • Patent number: 10831967
    Abstract: Methods, systems and computer program products for providing improved placement and connectivity of local clock buffer controllers are provided. Aspects include determining positions of a plurality of centroid locations within a circuit design based on positions of a plurality of latches within the circuit design. Aspects also include modifying the circuit design to place a local clock buffer controller at each of the plurality of centroid locations within the circuit design. Aspects also include connecting each of a plurality of local clock buffers within the circuit design to a nearest local clock buffer controller.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jesse Surprise, Gerald Strevig, III, Shawn Kollesar, Michael Kazda
  • Patent number: 10628543
    Abstract: Systems and methods are provided for calculating a power characteristic of an integrated circuit design. For each standard cell of a gate-level netlist, a path length and a set of attributes are computed. For each leaf-level instance of a register-transfer level (RTL) netlist, a path length and a set of attributes are computed. The standard cells are partitioned into first subsets, each of the first subsets containing standard cells with a same path length and a same set of attributes. For each first subset, a relative percentage for each type of standard cell included in the first subset is calculated. The leaf-level instances are partitioned into second subsets. For each pair of corresponding first and second subsets, standard cells are associated with the leaf-level instances of the second subset based on the relative percentages. A power characteristic of the RTL netlist is calculated based on the associated standard cells.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: April 21, 2020
    Assignee: Ansys, Inc.
    Inventors: Renuka Vanukuri, Ajay Singh Bisht, Allen Baker
  • Patent number: 10573517
    Abstract: A method for depositing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate is provided. Due to the strong adhesion of graphene and cobalt to a semiconductor substrate, the layer of graphene is epitaxially deposited.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: February 25, 2020
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Vikas Berry, Sanjay Behura, Phong Nguyen, Michael R. Seacrist
  • Patent number: 10388863
    Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and is controlled by a third control line, where the second transistor is overlaying the first transistor and is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and third control line, and where the first transistor, the second transistor and the third transistor are all aligned to each other with less than 100 nm misalignment.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: August 20, 2019
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 10289797
    Abstract: Aspects of the present disclosure address improved systems and methods for local cluster refinement during clock tree synthesis for integrated circuit designs. In accordance with some embodiments, the methods for local cluster refinement may include pin move refinement and local reclustering. With pin move refinement, pins are moved from clusters that fail to satisfy design rule constraints to nearby clusters that satisfy design rule constraints. With local reclustering, groups of neighboring clusters that fail or nearly fail to satisfy design rule constraints are dissolved and corresponding pins are regrouped to form new clusters that satisfy design rule constraints.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Natarajan Viswanathan, Charles Jay Alpert, Wen-Hao Liu, Thomas Andrew Newton
  • Patent number: 10255298
    Abstract: A method for determining a self-assembly pattern of a block copolymer confined inside a closed outline called the guiding outline, comprises the following steps, which are implemented by computer: a) choosing in a database a closed outline called the reference outline that is similar to the guiding outline, a self-assembly pattern of the block copolymer, called the reference pattern, being associated with the reference outline; b) applying a geometric transformation to a plurality of points of said reference pattern in order to convert them to respective points called image points of the self-assembly pattern to be determined. A computer program product for implementing such a method is provided.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: April 9, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Jérôme Belledent
  • Patent number: 10204908
    Abstract: An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: February 12, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10153265
    Abstract: A dummy cell arrangement in a semiconductor device includes a substrate with a dummy region, unit dummy cells arranged in rows and columns in the dummy region, and flexible extended dummy cells arranged in rows and columns filling up remaining dummy region. The unit dummy cell includes exactly one base dummy cell and exactly two fixed dummy cells at opposite sides of the base dummy cell in row direction or in column direction and the flexible extended dummy cell includes at least two base dummy units and a plurality of flexible dummy units at two opposite sides of the two base dummy units in row direction or in column direction. The base dummy cell consists of at least one fin, at least one gate and at least one contact, while the flexible dummy cell consists of one gate and one contact without any fin.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: December 11, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Liang Chu, Yu-Ruei Chen, Yu-Hsiang Lin
  • Patent number: 10078323
    Abstract: A dynamically configurable intelligent controller of a machine tool based on DSP/FPGA and control method thereof are disclosed. The intelligent controller includes a DSP/FPGA information processing module, a data input module, an output execution module and an embedded central processing system module. The DSP/FPGA information processing module includes a hardware reconfigurable information sampling unit, a digital signal processing unit, a hardware reconfigurable algorithm unit, a hardware reconfigurable control information output execution unit and a data storage unit. The DSP/FPGA information processing module configures hardware units according to an intelligent control strategy file created based on the intelligent control needs to generate an intelligent control algorithm graph.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: September 18, 2018
    Assignees: Chongqing University, Chongqing Haiteke System Integration Co., Ltd., Beijing Tsinghua Software Information Technology Co., Ltd.
    Inventors: Ping Yan, Runzhong Yi, Qingning Zhao, Fei Liu, Linqiao Hu
  • Patent number: 10068048
    Abstract: The disclosure describes approaches for generating a clock tree for a circuit design. Initial clock trees are generated and elements are assigned to locations on an integrated circuit (IC). Each of the initial clock trees includes a clock root, a spine including the clock root, and branches connected to and extending from the spine. Each clock load is coupled to one of the branches. The clock tree further includes programmable delay circuits having initial delay values that are balanced. If the circuit design does not satisfy timing constraints, at least one clock root is moved from a respective first location to a respective second location.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: September 4, 2018
    Assignee: XILINX, INC.
    Inventors: Mehrdad Eslami Dehkordi, Marvin Tom, Sridhar Krishnamurthy, Frank Mueller
  • Patent number: 10056387
    Abstract: An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: August 21, 2018
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10042971
    Abstract: Approaches for routing clock signals of a circuit design on an IC include determining initial partitions of clock sources and clock loads. Each initial partition includes one of the clock sources and a subset of the clock loads associated with the one clock source, and initial each partition defines an area of the IC in which the one of the clock sources and the associated subset of clock loads are placed. A processor determines for each of the initial partitions, whether or not the initial partition has a congested clock region. For each initial partition determined to have a congested clock region, the processor defines a respective new partition by excluding the one of the clock sources from the new partition. The new partition includes the subset of the clock loads and does not include the one clock source. The processor then routes clock signals from the clock sources to the clock loads.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: August 7, 2018
    Assignee: XILINX, INC.
    Inventors: Mehrdad Eslami Dehkordi, Raoul Badaoui, Marvin Tom, Sridhar Krishnamurthy
  • Patent number: 9953925
    Abstract: A 3D IC device including: a first semiconductor layer including first mono-crystallized transistors, where the first mono-crystallized transistors are interconnected by at least one metal layer including aluminum or copper; a second layer including second mono-crystallized transistors and overlaying the at least one metal layer, where the at least one metal layer is in-between the first semiconductor layer and the second layer; a global power grid to distribute power to the device overlaying the second layer; and a local power grid to distribute power to the first mono-crystallized transistors, where the global power grid is connected to the local power grid by a plurality of through second layer vias, and where the vias have a radius of less than 150 nm.
    Type: Grant
    Filed: December 20, 2015
    Date of Patent: April 24, 2018
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Zeev Wurman
  • Patent number: 9929091
    Abstract: Semiconductor devices and methods are provided in which vertical fuse devices are integrally formed with FINFET (Fin Field Effect Transistor) devices, wherein the vertical fuse devices are formed as part of a process flow for fabricating the FINFET devices. For example, a semiconductor device comprises first and second vertical semiconductor fins, a vertical fuse device, and a FINFET device. The vertical fuse device comprises a metal fuse element formed over a portion of the first vertical semiconductor fin, and the FINFET device comprises a metal gate electrode formed over a portion of the second vertical semiconductor fin. The metal fuse element and the metal gate electrode are concurrently formed as part of a replacement metal gate process flow.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Junli Wang, Chih-Chao Yang
  • Patent number: 9922981
    Abstract: An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: March 20, 2018
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 9916411
    Abstract: A virtual hierarchical layer (VHL) is constructed for a semiconductor design in order to reduce the computational requirement of design rules checking (DRC) and design rules for manufacture (DRM) procedures. In order to form the VHL, a negative plane is created. A cell and multiple instances of the cell are then identified in the semiconductor design and polygons which overlap the cell and its instances are determined. The polygons are pushed into the negative plane to create holes in the plane. Shapes overlapping other instances of the cell which fall onto holes in the solid virtual cell plane are ignored. The resulting holed solid virtual cell plane can then be inverted to create a VHL to be used for design simulation and verification.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: March 13, 2018
    Assignee: Synopsys, Inc.
    Inventors: Gary B Nifong, Jun Chen, Karthikeyan Muthalagu, James Lewis Nance