Abstract: MRAM cells are placed in the upper regions (BEOL) of an integrated circuit while simultaneously maintaining the dimensions needed for good MRAM performance and also for good operation of the logic circuit by setting the standard vertical dimension of the BEOL at the value that is suitable for logic circuits. In the areas where MRAM cells are to be placed, the (N+1)th level is etched separately. A standard etch is applied in logic areas and a deeper etch is applied in MRAM areas, so that the interlevel distance in the logic areas is the standard amount and the interlevel distance is MRAM areas is a lesser amount that is appropriate to accommodate the vertical dimensions of the material layers that go into the MRAM cells.

Abstract: A semiconductor device has a fuse to be blown with an energy beam. The semiconductor device has copper wiring levels formed on a semiconductor substrate on which semiconductor elements are formed, an uppermost wiring level formed on said copper wiring levels and including a refractory metal film connected to a top one of the copper wiring levels, the fuse formed from a part of the uppermost wiring level, and a surface protective film formed on the uppermost wiring level.

Abstract: A lithographic reticle with subresolution features in the design-pattern is used to control critical dimensions in a semiconductor manufacturing process. After the location of design and processing features is determined, subresolution features are formed in areas devoid of design and processing features. The subresolution features can substantially fill all of the area devoid of design processing features or, instead, selectively fill portions of the area. In one embodiment, the width of the area devoid of design and processing features is less than two times the width of a feature. The presence of the subresolution features results in improved control of small dimensions of features in semiconductor processing, thereby increasing yield and device performance.

Abstract: Two types of topologically different three-dimensional integrated circuits (for example a 4-layer three-dimensional memory array and an 8-layer three-dimensional memory array) are fabricated from a single set of photolithographic masks. In one example, masks 1-5 are used along with other masks to create the first four levels of memory cells in both a 4-layer memory array and an 8-layer memory array. The 8-layer memory array is completed with masks used to form the top four layers of the array. An integrated circuit identification circuit generates an appropriate circuit identification signal for both types of integrated circuits by sensing whether a conductive path across some or all of the device levels of the integrated circuit is continuous, and then by selecting the appropriate circuit identification signal.

Abstract: Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion being positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell.

Abstract: A ROM array which provides for reduced size and power consumption. The bit cell of the ROM provides that a first type of information is stored in the bit cell when a transistor is disposed between a bit line and a word line, and a second type of information is stored in the cell when no transistor is disposed between the bit line and the word line. In the bit cell a contact between a bit line and a region where a transistor drain can be formed in a substrate is provided in those instances when a transistor is formed between the bit line and a word line. In those instances when a bit cell provides no transistors between the word line and the bit line, no contact is provided between the bit line and the region where a transistor drain can be formed. Further, where a bit cell does not provide a transistor between the bit line and the word line a bit cell region in the substrate can consist substantially of an isolating dielectric material.

Abstract: A new structure is disclosed for source/drain bit lines in arrays of MOSFET devices. Rows of conducting regions are formed by ion implantation through openings adjacent to gate structures and in isolation regions separating columns of active areas of the arrays. The openings are filled with insulating material.

Abstract: A new method is provided that allows placing or stacking staggered bond I/O buffers into linear bond I/O buffers. The bond pads are linearly arranged, the interface between the staggered bond pad I/O buffers and the linearly arranged bond pads is achieved by a frame design that sequentially connects the staggered bond pad I/O buffers to the linearly arranged bond pads.

Abstract: A method for making an HDI circuit including backside connections uses parylene as a protective coating. The method includes the steps of: procuring an insulating substrate including an active chip which has exposed electrical or thermal connection(s) on the rear surface thereof, applying a parylene coating to the exposed connections to protect the connections; performing additional HDI interconnect processing steps as desired on the front surface of the substrate; selectively removing a portion of the parylene coating to expose at least a portion of a connection; and making electrical connection to the exposed backside connections by application of a conductive material in its liquid state to the removed regions. The parylene coating is removed by an excimer laser. The step of making electrical connection to the backside electrical connections may be performed by application of solder, or conductive epoxy in its liquid state.

Abstract: An integrated programmable conductor memory cell and diode device in an integrated circuit comprises a diode and a glass electrolyte element, the glass electrolyte element having metal ions mixed or dissolved therein and being able to selectively form a conductive pathway under the influence of an applied voltage. In one embodiment, both the diode and the memory cell comprise a chalcogenide glass, such as germanium selenide (e.g., Ge2Se8 or Ge25Se75). The first diode element comprises a chalcogenide glass layer having a first conductivity type, the second diode element comprises a chalcogenide glass layer doped with an element such as bismuth and having a second conductivity type opposite to the first conductivity type and the memory cell comprises a chalcogenide glass element with silver ions therein. In another embodiment, the diode comprises silicon and there is a diffusion barrier layer between the diode and the chalcogenide glass memory element.

Abstract: A micromechanical memory 100 element comprising a deflectable member 102 located between a first member 104 and a second member 106. The first member 104 is biased at a first member voltage, and the second member 106 is biased at a second member voltage. A bias voltage applied to the deflectable member will drive the deflectable member to either the first member 104 or the second member 106. A first contact 108 is positioned on the top, or end, of the first member 104. A second contact 110 is positioned on the top, or end, of the second member 106. These contacts are biased through resistors 112 and 114 with a first and second contact voltage sufficient to hold the deflectable member in place even after removal of the bias voltage applied to the deflectable member. The state of the micromechanical memory element can be determined by sensing the voltage of the deflectable member 102.

Abstract: A tuning circuit comprising a first reactance, a second reactance and a insulated gate field effect transistor having a gate arranged to receive a control signal. The first reactance is connected between the source of the field effect transistor and a first node. The second reactance has the same value as the first reactance and is connected between the drain of the field effect transistor and a second node. The first and second nodes are arranged so as to experience a balanced ac signal. Turning the field effect transistor on has the effect of making the first and second reactances effective in the circuit and vice versa.

Abstract: A submount substrate is used for the dual purposes of enabling simultaneous burn-in processing for a relatively large number of arrays of optical transmitters and enabling conventional dicing techniques to be used to form mounting-ready assemblies. In the preferred embodiment, the submount substrate is a silicon wafer that is specifically designed to provide connectivity between VCSEL arrays and burn-in equipment during the testing stage, but is also designed to be segmented and used in the final packaging stage. Because the submount is a silicon wafer, conventional integrated circuit fabrication techniques may be used to form conductive patterns that define array-receiving areas and that allow external circuitry to communicate with the various VCSEL arrays.

Abstract: In a chip package, when a Ni/Au layer is formed by electroless plating, there is no problem with density increasing of interconnections and the like, since leads for plating and tie bars are not formed. However, the adhesive strength of solder balls to ball pads is low, so that the adhesion tends to be unstable. In the present invention, no leads for plating are formed, while the adhesive strength of solder balls to ball pads is improved by electroplating the ball pads with a Ni/Au layer. In addition, an increase in the density of interconnections and an improvement of the electrical properties is also obtained. The Ni/Au layer is formed by electroplating on the base metal layer surface which is not covered with a DFR (Dry Film Resist) by applying an electric current to the base metal layer.

Abstract: A semiconductor device includes a semiconductor chip and a circuit formed in the semiconductor chip. Pads are arranged in a plurality of rows on the semiconductor chip and electrically connected to the circuit. The pads on adjacent rows are offset from each other. Leads are provided on the semiconductor chip and bonding wires selectively connect the leads to the pads.

Abstract: A semiconductor device includes a real pattern and dummy patterns in respective different coordinate systems. Using a dummy pattern in a single coordinate system does not allow an effective dummy pattern arrangement. To the contrary, if the dummy patterns in different coordinate systems are used, minimum interval requirements may be satisfied in one coordinate system while such requirements are not met in another coordinate system.

Abstract: A lithographic reticle with subresolution features in the design-pattern is used to control critical dimensions in a semiconductor manufacturing process. To determine the location of subresolution features the location of design and processing features is determined and the subresolution features are formed in areas devoid of design and processing features. The subresolution features can substantially fill all of the area devoid of design and processing features or, instead, selectively fill portions of the area. In one embodiment, the width of the area devoid of design and processing features is less than two times the width of a feature. The presence of the subresolution features results in improved control of small dimensions of features in semiconductor processing, thereby increasing yield and device performance.

Abstract: A semiconductor device includes a power supply semiconductor chip that has a plurality of current passing electrodes. Conductive plates are disposed on the current electrodes, and conductive wires used for an external connection of the device are fixed on the conductive plates, but not directly on the current passing electrode. A large plate is first fixed on the semiconductor chip, and then the back surface of the large plate is removed to form the individual conductive plates. Because the conductive wires are soldered onto the conductive plates, the semiconductor chip does not receive impact of wire bonding. Even when the conductive wires are wire bonded to the conductive plates, the plates may serve as shock absorbers during wire bonding procedure to reduce the impact of the wire bonding.

Abstract: A semiconductor chip has standard cells which are disposed in a plurality of mutually adjacent rows, wiring channels are disposed between the rows and at at least one location along at least one wiring channel, the width of the wiring channel determined by a prescribed unambiguous and variable assignment specification. The width of the wiring channels can thus be varied in a flexible manner, so that a circuit can be fabricated in a space-saving manner.

Abstract: A method for forming an integrated circuit device having dummy features and the resulting structure are disclosed. One embodiment comprises a first active feature separated from a substantially smaller second active feature by a dummy-available region void of active features. Within the dummy-available region and in close proximity to the second active feature exists a dummy feature.

Abstract: A memory device includes memory cells, bit lines, active area lines running generally in parallel to the bit lines, and transistors formed in each active area line and electrically coupling memory cells to corresponding bit lines. Each bit line includes slanted portions that intersect a corresponding portion of an active area line at an angle. Contacts electrically coupling the bit line to portions of the active area line are formed in a region generally defined by the angled intersection of the bit line to the active area line. The memory cells can have an area of about 6F2, and the bit lines can be coupled to sense amplifiers in a folded bit line configuration. Each bit line includes a first level portion and a second level portion.

Abstract: Methods and apparatus for increasing the yield achieved during high density interconnect (HDI) production. In particular, processes in which panels are tested to identify good cells/parts, good cells are removed from the panels, and new panels created entirely of identified/known good cells allow increases in the number of layers used in a HDI without incurring the decrease in yield normally associated with such a layering process.

Abstract: A technique and structure for simplifying the stitching process is disclosed. According to one aspect of the present system, a floor plan that minimizes the number of blocks for a two-dimensional stitching project is described. Another technique describes a special layout method for a row/column decoder that reduces the number of blocks when stitching.

Abstract: A method and apparatus for a driver layout is described. The layout includes an first number of gate lines arranged along a first axis and a second equal number of gates arranged along a second axis, such that the first set of gates lines is orthogonal to the second set of gates lines. The layout includes a total of N discrete transistors.

Abstract: A method of fabricating a mask ROM comprising: preparing a substrate defined by a memory cell array region and a peripheral region; forming a device isolation film between the memory cell array region and the peripheral region; forming a gate-forming material layer; covering the memory cell array region and selectively etching the gate-forming material layer in the peripheral region to form a first gate; forming an insulation spacer in a lateral portion of the gate; injecting ion to the substrate in the peripheral region to form a source/drain region; forming salicide on the gate-forming material layer of the memory cell array region and the gate and in the source/drain region; covering the peripheral region and selectively etching the gate-forming material layer in the memory cell array region to form a second gate; and forming a protective film on the resultant substrate.

Abstract: A method of fabricating a microdevice having the steps of forming a first regular array of lines and spaces from a first layer of material deposited on a substrate; patterning the first regular array of lines and spaces to form a first portion of a microdevice component; providing an intermediate layer over the first portion of the microdevice component; forming a second regular array of lines and spaces from a second layer of material deposited on the intermediate layer; patterning the second regular array of lines and spaces to form a second portion of the microdevice component; and forming contact holes in the intermediate layer to establish conductivity between the first portion of the microdevice component and the second portion of the microdevice component.

Abstract: A drain electrode wiring conductor through which a main current of a MOS transistor takes the form of a flat board, being inserted into a first side of the frame of a case, and extends along the first side. The source electrode wiring conductor also takes the form of a flat board, being inserted into the first side and a second side, and extends parallel to a drain electrode wiring conductor along the first side. The flow of the current in the drain electrode wiring conductor is opposite in direction to the flow of the current in the source electrode wiring conductor. With the configuration, the parasitic inductance of a semiconductor module including a plurality of MOS transistors can be reduced.

Abstract: Concave portions and convex portions are formed on an insulating layer. First bit lines are arranged on the convex portions. A width of the first bit lines is set to L, and a space between the first bit lines is set to L+2S. Each of the first bit lines is electrically connected to a drain diffusion layer by a contact plug. Second bit lines are arranged in a trench between the first bit lines. A width of the second bit lines is set to L, and a space between the first and second bit lines is equal to a width S of a side wall. Each of the second bit lines is electrically connected to a drain diffusion layer by a contact plug.

Abstract: A method for installing protective components in integrated circuits constructed from standard cells includes reserving sufficient space in the standard cells for at least one protective component, wiring the standard cells and determining which standard cells require a protective component and inserting at least one protective component into the standard cells. A place marker can mark the space required for a protective component in the integrated circuit layout. The protective component can be a protective diode. Protective component connections can be provided in the standard cells. The standard cells can be gate arrays.

Abstract: In a method of manufacturing modules (4), each with at least one integrated circuit (2), the integrated circuits (2) are separated from a previously manufactured circuit configuration (1), which is in the form of a flexible film comprising a plurality of integrated circuits (2) on the basis of a polymer, by a combined stamping-vacuum conveying device (6), after which each of the separated integrated circuits (2) is conveyed to a module substrate (5) and connected to the module substrate (5) so as to form a module (4).

Abstract: A method and apparatus relating to fabricating semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites, wherein the evaluated information is saved in an electronic file as mapped information. A die attach apparatus attaches dice to the die attach sites in accord with the mapped information, wherein known good dice are attached to the good die attach sites and known defective dice are attached to the defective die attach sites. The assembly is then encapsulated in a transfer molding operation. Since each die attach site includes a die attached thereto, the structural integrity of the mounting substrate is maintained and there is greater volume control of encapsulation material in the transfer molding operation to prevent waste and shortage of the encapsulation material.

Abstract: A memory structure has an antifuse material that is unpatterned and sandwiched between each of a plurality of antifuse electrode pairs. The antifuse material is continuous between the antifuse electrode pairs. Furthermore the present invention includes a memory structure comprising a plurality of antifuse electrode pairs forming a plurality of row conductors and a plurality of middle conductors in electrical communication with a plurality of control elements.

Abstract: A structure and a method for forming buffer cells in power line areas between macro cell in a macro block area. In a power line level, a pin is formed between VSS and VDD lines. The pin is connected to the buffer cell. Next a signal line layer is formed and the signal line is connected to the pin and to a driver. In a first embodiment the driver is formed in a standard cell area. In a second embodiment, the driver is formed in a macro cell. A signal line is connected to the pin and the driver.

Abstract: For providing a semiconductor package with improved moisture resistance and high reliability and a production method thereof, a solder resist is also provided in an appropriate thickness between electrodes of conductor circuits on a surface of a substrate. The resist in these portions is obtained by patterning the solder resist while leaving the solder resist between the conductor circuits by removing the unnecessary solder resist under irradiation of a laser.

Abstract: A method used to form a semiconductor device comprises providing first and second circuit portions having first and second pad portions respectively. The second circuit portion is electrically isolated from the first circuit portion. The first and second pad portions are then electrically connected, for example with a ball bond or a wire bond, to electrically couple the first and second circuit portions. In various embodiments the semiconductor device will not function until the pad portions are electrically coupled, and in other embodiments the functionality of the device may be selectively controlled by connecting selected pad portions from a plurality of pad portions. Isolating the first and second circuit portions allows electrical operations such as antifuse programming to be carried out without adversely affecting related circuits. Once electrical operations are completed, the isolated circuit portions are electrically coupled to provide a complete circuit.

Abstract: Method to optimize net lists used in the design and fabrication of integrated circuits by using simultaneous placement optimization, logic function optimization and net buffering algorithms. Method simultaneously obtains a placement of logic functions, mapping of logic functions on to library elements and buffering of nets connecting the logic functions.

Abstract: MOS transistors (TR1, TR2) are arranged closer to a pad (SP) in descending order of current-driving capability. Namely, the MOS transistors (TR1, TR2) are arranged from closer part to the pad (SP) in descending order of value of W/L obtained by dividing a gate width (W) of a gate electrode by a gate length (L) of the same. When a transistor has a large current-driving capability, the value of source-to-drain current is high. For this reason, the MOS transistors are arranged from closer part to the pad for source electrode in descending order of current-driving capability, to thereby reduce the amount of voltage drop in an interconnect line. A current value of the transistor becomes lower as a distance between the pad and the transistor increases. As a result, it is allowed to reduce influence on the transistor characteristics exerted by voltage drop due to interconnection resistance.

Abstract: An architecture to efficiently handle primary input and output signals for an embedded FPGA core in an ASIC is disclosed. Only the FPGA core is used without wire-bonding pads and pad ring found in conventional embedded FPGAs. The input and outputs of the embedded FPGA core can be made peripherally or at selected locations throughout the core to obtain high I/O-to-logic ratios and flexibility in I/O placement with high routability.

Abstract: A method is disclosed for noise distribution in high resistivity substrates containing differential or balanced integrated circuitry obtaining a noise suppression by an introduction of noise distributors. Noise from an external noise source (5) is made isotropic in relation to branches of a differential or balanced integrated circuitry by creating a low resistivity path adjacent to the differential or balanced integrated circuitry typically formed by two integrated transistors (A, B) or group of transistors. The low resistivity path in the general case is made symmetrical in relation to the integrated transistors thereby forming a noise distributor for distributing the noise evenly. The noise distributor then is formed as a floating substrate contact (10) of the same doping kind as a substrate or a well within which the differential or balanced circuitry is contained.

Abstract: The present invention relates to an improved memory circuit with a divided bit-line, shared sense amplifier architecture. In a conventional divided bit-line, shared sense amplifier configuration, two adjacent memory sub-arrays are generally located between two banks of sense amplifiers and selected bit lines of the two adjacent memory sub-arrays are generally connected to metal lines with metal contacts to reduce capacitive loading. Under the present invention, some sense amplifiers from either banks of sense amplifiers are repositioned to the area between the two adjacent memory sub-arrays thereby permitting the repositioned sense amplifiers to be shared. As a result, any two adjacent memory sub-arrays share a bank of sense amplifiers. Furthermore, selected bit lines from the two adjacent memory sub-arrays are coupled to metal lines within the repositioned sense amplifiers.

Abstract: For a selection of semiconductor chips stacked on top of one another, the invention includes leading through selection contact points of one chip on a rear side thereof and connecting them to corresponding selection contact points of the other semiconductor chip. Programmable input amplifiers are programmed to be transmissive or blocking through fuses/antifuses so that selection signals applied to the selection contact points either activate or block functional elements only of one or only of the other semiconductor chip. As a result, simple stacking of identically prefabricated semiconductor chips is made possible.

Abstract: A multichip semiconductor device with an improved yield and a reduced inspection cost is provided in which a fuse is provided on a first semiconductor chip while a fuse is not provided on a second semiconductor chip as a rewritable memory, and these chips are connected inside a package. The second semiconductor chip includes redundancy cells to be replaced for defective bits. To produce a post-redundancy-restoration state in which the defective bits are replaced with the redundancy cells before the second semiconductor chip is connected with the first semiconductor chip, the second semiconductor chip includes a restoration state determining circuit and a command decode circuit. The restoration state determining circuit is for storing a redundancy restoration solution for restoring defective bits supplied via a first external input pad.

Abstract: A semiconductor memory device has a reference section which includes a first reference cell block and second reference cell blocks. The first reference cell block includes a second contact diffusion region which is arranged under a virtual ground line and is connected to this virtual ground line via a contact hole. The second reference cell blocks include first and third contact diffusion regions which are arranged under a bit line and can be connected to the bit line via contact holes as needed. Thereby, the number of reference cell blocks to be connected in series can be selected freely, allowing finer settings of a reference current value.

Abstract: A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e.g., orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.

Abstract: The present invention enables to design a semiconductor integrated circuit with a small chip area and the number of wiring layers at a low cost for a short time. In the present design method of the semiconductor integrated circuit, a first wiring group (a horizontal power wiring and horizontal ground wirings) and a second wiring group (a horizontal power wiring and horizontal ground wirings), which are opposite to each other, are arranged at the outside of a macro outer frame, a third wiring group (a vertical power wiring and a vertical ground wring) is arranged to correspond to a power terminal and a ground terminal on a macro cell, and these first and second wiring groups are connected to the power terminal and the ground terminal by the third wiring group.

Abstract: A plurality of first contact holes reaching an n+-type semiconductor area used as the source of a MISFET employed in a logic-DRAM mixture LSI and a plurality of second contact holes reaching another n+-type semiconductor area used as the drain of the MISFET are bored through an insulation layer created over a gate electrode of the MISFET. A conductive film on the same layer as a bit line shunts the n+-type semiconductor area used as the source through the first contact holes. Another conductive film shunts the n+-type semiconductor area used as the drain through the second contact holes.

Abstract: A semiconductor element wherein only one of two mutually adjacent electrodes has a split pattern that is formed on the same layer as the other electrode. The split electrode is connected to a wiring layer provided on a separate layer. When the semiconductor element is a MOSFET, the mutually adjacent electrodes are provided on a source diffusion layer and a drain diffusion layer. Specifically, they serve as a source electrode and a drain electrode, respectively. The split electrode is connected to the source diffusion layer or drain diffusion layer through a single contact hole. This allows the parasitic capacitance in the semiconductor element region to be easily reduced even when the semiconductor element, such as a MOSFET, which comprises the semiconductor integrated circuit is miniaturized.

Abstract: A semiconductor memory comprises: a first conductivity type semiconductor substrate and one or more memory cells each constituted of an island-like semiconductor layer having a recess on a sidewall thereof, a charge storage layer formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, and a control gate formed on the charge storage layer, wherein at least one charge storage layer of said one or more memory cells is partially situated within the recess formed on the sidewall of the island-like semiconductor layer.

Abstract: A semiconductor device having a memory cell including first and second load transistors, first and second driver transistors, and first and second transfer transistors. The semiconductor device includes first and second gate-gate electrode layers, first and second drain-drain wiring layers, and first and second drain-gate wiring layers. The first drain-gate wiring layer and the second drain-gate wiring layer are located in different layers. The first drain-gate wiring layer is located below the first drain-drain wiring layer, and the second drain-gate wiring layer is located in above the first drain-drain wiring layer. This structure provides a semiconductor device that has reduced cell area. The invention also provides a memory system and electronic apparatus that include the above semiconductor device.

Abstract: An integrated circuit includes a serpentine conductor track extending through a plurality of conductor layers and having ends coupled to first and second circuit elements, the ends being in opposing outermost ones of the conductor layers. The serpentine conductor track can selectively be made to be (i) continuous and electrically couple the first and second circuit elements together or (ii) discontinuous so that the first and second conductor elements are not electrically coupled. In the latter case, the discontinuity can be formed in any one of the conductor layers and a bridging conductor track is further formed in that one conductor layer which is coupled to the serpentine conductor track and which bypasses either of the first and second circuit elements. This structure has the advantage that circuit changes can be made in any conductor layer.