Abstract: A structure and a method for forming cells in power line areas between macro cell in a macro block area. In a power line level, a pin is formed between VSS and VDD lines. The pin is connected to the buffer cell. Next a signal line layer is formed and the signal line is connected to the pin and to a driver. In a first embodiment the driver is formed in a standard cell area. In a second embodiment the driver is formed in a micro cell. A signal line is connected to the pin and the driver.

Abstract: An object of the present invention is to provide a semiconductor device and a method of manufacturing the semiconductor device which can improve the flatness after the chemical mechanical polishing by inserting necessary and minimum dummy patterns and has high throughput.

Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

Abstract: The present invention is a level of an integrated circuit. The level of integrated circuit has a first area having a plurality of features having a first density and the level of the integrated circuit has a second area adjacent to the first area wherein the second area has a plurality of dummy features having a density substantially similar to the first density.

Abstract: A method is provided for forming a device. The method provides a substrate, and provides a plurality of nanotubes in contact with the substrate. The method comprises depositing metal contacts on the substrate, wherein the metal contacts are in contact with a portion of at least one nanotube. The method further comprises selectively breaking the at least one nanotube using an electrical current, removing the metal contacts, cleaning a remaining nanotube, and depositing a first metal contact in contact with a first end of the nanotube and a second metal contact in contact with a second end of the nanotube.

Abstract: The present invention provides an array of customizable functional cells having high density and high drive capacity. It further provides an architecture that maximizes the width of P-channel transistors in an array of standard cells to compensate for the lower speed operation of P-type devices. More particularly, the invention discloses a digital circuit comprising a plurality of inputs for receiving respective logic signal and circuitry, coupled to the inputs, for passing one of the signals responsive to the order in which a transition is received on each of the inputs.

Abstract: The semiconductor configuration has a packing material that is permeable to radiation energy in a given wavelength band. One or more fuses that adjoin the packing material absorb the energy in the given wavelength band. The fuses are formed of AIIIBV semiconductor material, of titanium silicide, germanium, PbS, InSb, or of SiGe.

Abstract: A library used for manufacturing a semiconductor IC and a method of manufacturing the semiconductor IC. The library includes structures designed with a predetermined design rule. The library has a main part including one or more circuit elements, and a connecting terminal connected to the main part. The connecting terminal has a width less than a minimum space between the conductive patterns of the predetermined design rule. The library further includes a head portion connected to the connecting terminal at an end thereof. A width of the head portion is greater than the minimum space between the conductive patterns of the predetermined design rule.

Abstract: A method for forming a sensing apparatus having a sensor and signal conditioner angled relative to each other at a predetermined angle and formed in a seamless monolithic semiconductor substrate is provided. The sensor and the signal conditioner are formed on distinct surface portions of a single seamless monolithic semiconductor substrate. The sensor, moreover, can be formed in the cut plane of the seamless monolithic semiconductor substrate. The signal conditioner correspondingly can be formed in a wafer surface of the same seamless monolithic semiconductor substrate. The seamless monolithic semiconductor substrate further can be mounted on a mounting base and at least the signal conditioner encapsulated in an encapsulation to provide a protective cover. An additional conductor connected to the signal conditioner and extending outwardly from the encapsulation can connect the sensing apparatus to a remote electrical device such as a sensing monitor.

Abstract: A substrate for electrically connecting to an integrated circuit, where the integrated circuit has differential pairs of signals that are associated with differential pairs of integrated circuit contacts. Differential pairs of substrate contacts are disposed on a first substrate layer in alignment with the differential pairs of integrated circuit contacts. Differential pairs of vias are also disposed on the first substrate layer, and extend to at least one underlying substrate layer. The differential pairs of vias make electrical connections with the differential pairs of substrate contacts. Each via within a given one of the differential pairs of vias is disposed within a column with each other on the first substrate layer. The columns for each of the differential pairs of vias are in a substantially parallel arrangement one with another. Differential pairs of traces are disposed on the at least one underlying substrate layer.

Abstract: A method for forming a wafer level package incorporating a multiplicity of elastomeric blocks as stress buffering layer and package formed are described. The method incorporates the step of forming metal lines in-between the plurality of IC dies on a wafer during the same process used for forming the metal vias. The metal lines are subsequently removed by either a mechanical method such as dicing with a diamond saw or by a chemical method such as wet etching. The method allows the fabrications of a wafer level package that has a multiplicity of elastomeric blocks formed on top as stress buffering layer without the CTE mismatch problem with other layers on the wafer.

Abstract: A design support system 100 according to the present invention comprises: an LSI library 10, in which rated characteristics of various LSIs are stored by an LSI library preparation unit 70; a decoupling capacitor library 20, in which rated characteristics of various capacitors are stored; a PCB library 30, in which the cross-sectional structures of various power wiring lines are stored; a decoupling capacitor search unit 40, for employing the LSI library 10 and the decoupling capacitor library 20; a power wiring determination unit 50, for employing the results obtained by the decoupling capacitor search unit 40, the LSI library 10 and the PCB library 30; and a design results output unit 60, for outputting the results received from the power wiring determination unit 50. Furthermore, the data in the three libraries can be updated or new data can be added.

Abstract: A method for concentric metal density power distribution is disclosed that reduces metal density and increases available area for routing clock and signal traces. A method of concentric metal density power distribution includes the steps of partitioning an area of standard cells in an integrated circuit chip into a plurality of power regions, forming a power boundary around each of the plurality of power regions, and forming a plurality of concentric straps in a metal layer of the integrated circuit chip wherein each of the plurality of concentric straps has a strap width that varies from a maximum strap width at a periphery of each of the plurality of power regions to a minimum strap width toward a center of each of the plurality of power regions.

Abstract: The memory cell configuration has a large number of memory cells provided in a semiconductor substrate and having bit-line trenches which extend in parallel in the longitudinal direction in the main face of the semiconductor substrate, at the bottoms of which in each case a first conductive region is provided, at the peaks of which in each case a second conductive region of the same conduction type as the first conductive region is provided, and in the walls of which in each case an intermediately located channel region is 0 provided; and having word lines which extend in the transverse direction along the main face of the semiconductor substrate, through specific bit-line trenches, to activate transistors provided there. An additional dopant is introduced into the trench walls of the bit-line trenches which are located between the word lines, in order to increase the corresponding transistor turn-on voltage there to suppress leakage currents.

Abstract: Disclosed is a technique capable of enhancing the degree of freedom in the layout of a rerouting layer in a wafer level CSP in which defect repairing is performed by cutting a fuse. More specifically, after the defect repairing is performed by irradiating a laser beam to a fuse, an organic passivation layer (photo-sensitive polyimide layer) is filled in a fuse opening. Thereafter, a rerouting layer, a bump land, an uppermost wiring layer, and a solder bump are formed on the organic passivation layer. In the following steps of the defect repairing, the baking process to cure an elastomer layer and the uppermost protection layer is conducted at a temperature below 260° C. in order to prevent the variance of the refresh times of memory cells.

Abstract: An integrated circuit chip includes a substrate having edges defining an inner area; circuit modules located on the substrate; and input/output terminals for inputting and outputting one or more signals to and from the circuit modules. The input/output terminals include (i) input/output terminals used for operation, which input/output one or more operation signals during operation of the circuit modules, and (ii) input/output terminals used for inspection of the circuit modules. The input/output terminals used for operation are arranged along the edges of the substrate, and the circuit modules and the input/output terminals used for inspection are arranged on the inner area of the substrate.

Abstract: Methods and apparatus for manufacturing a semi-custom integrated circuit by using a standard mask and a custom mask to select from a standardized set of features in a way that obviates the need to create a customized mask containing only the selected features, and mask sets created using such methods and apparatus. For some integrated circuit fabrication processes, the second mask has an additional purpose, so it is not created only to perform this selection function. For some fabrication processes, the selection can be achieved without use of additional processing steps.

Abstract: A semiconductor integrated circuit has a logic circuit operated at a small power supply voltage of about 0.5V, wherein a noise margin of the logic circuit can be set at a larger value even if characteristics of the circuit vary depending upon manufacturing process conditions. Satisfactory speed can be ensured during an operation and power consumption can be reduced during a stand-by time. This is attained by controlling individual potentials of first and second conductivity type wells in which a logic circuit is formed. For this purpose, two voltage supply circuits for controlling voltages of the wells and a logic threshold voltage generator are provided.

Abstract: A method for producing bit lines for a memory cell array comprises as a first step the step of providing a layer structure which comprises a substrate having transistor wells implanted in a surface thereof, a sequence of storage medium layers provided on the surface of said substrate, and a gate region layer provided on said sequence of storage medium layers. Bit line recesses, which extend down to the sequence of storage medium layers, are produced in said gate region layer. Subsequently, insulating spacer layers are produced on lateral surfaces of said bit line recesses, whereupon a source/drain implantation is executed in the area of said bit line recesses, after a complete or partial removal of the sequence of storage medium layers. Following this, the substrate is exposed completely in the area of the bit line recesses, if this has not yet been done prior to the implantation.

Abstract: A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby creating a double metal scheme wherein the strapping layer is a second metal layer overlying metal wordlines. In a method of a first embodiment the strapping material is electrically connected to the digit line through a planar landing pad overlying the conductive plug. An insulative material is sloped to the planar landing pad in order to provide a surface conducive to the formation of the strapping material.

Abstract: In placement of 6-bit interconnection lines in parallel, for example, interconnection lines for three lower-order bits having a high signal change frequency and interconnection lines for three higher-order bits having a low signal change frequency are placed alternately, so that each interconnection line for a lower-order bit is sandwiched by interconnection lines for higher-order bits. With this layout, the interconnection lines for higher-order bits serve like shield lines for the interconnection lines for lower-order bits. This effectively suppresses increase in delay in signal propagation due to change of a signal propagating through an interconnection line for a lower-order bit and a signal propagating through an interconnection line for a higher-order bit to opposite phases, without increasing the area.

Abstract: A method for assigning signal traces to one of a plurality of power planes on a power layer of an integrated circuit package. The integrated circuit package has an integrated circuit signal contact region, a top routing layer, and a bottom routing layer. The power layer underlies both the top routing layer and the bottom routing layer. First signal traces on the bottom routing layer are routed from contacts disposed in a core portion of the integrated circuit signal contact region to first ball contacts disposed within a first perimeter of the integrated circuit package. The first perimeter has dimension corresponding to a first distance from the integrated circuit signal contact region. Second signal traces on the top routing layer are routed from contacts disposed in a peripheral portion of the integrated circuit signal contact region to second ball contacts.

Abstract: A semiconductor device is disclosed, by which the parasitic capacitance of each signal line can be decreased, the time necessary for developing the device can be decreased, and which has a structure for simply and quickly performing the characteristic evaluation of the semiconductor device. The semiconductor device comprises a lower-layer signal line provided below one of a main power-supply line and a main ground line via an insulating layer; and an upper-layer signal line provided above said one of the main power-supply line and the main ground line via an insulating layer. A window is formed in said one of the main power-supply line and the main ground line; and the lower-layer signal line and the upper-layer signal line are electrically connected in a space inside the window, without contacting said one of the main power-supply line and the main ground line.

Abstract: In a conventional LSI, since a minimum chip size is inevitably determined by the number and size of input/output pads formed on a chip, an no-patterned region occurs in an active region surrounded by an I/O region in a highly integrated circuit or a circuit with a small number of gates. The present invention intends to solve this problem to improve a semiconductor device. In a semiconductor device comprising on the same chip at least an I/O region where an input/output pad is formed and active regions where a circuit can be mounted, a plurality of logic circuits having the same functions or different functions are mounted in the active regions on the same chip.

Abstract: The layout method of a semiconductor integrated circuit device according to the present invention includes a net list modification process for adding a cell to a flip-flop group directly connected to the clock source, a process for generating gated circuit division information which allocates the division number of the gated circuit and the drive ability of the cell so that the drive ability of the cell is selected and the delay value becomes uniform, a gated circuit division process for forming a cluster by dividing each of the gated circuits through clustering, a gated cell division process for allocating to each cluster the same number of gated cells as that of the formed clusters and a gated cell front stage CTS process in order to reduce the skew of the clock signal from the clock source via the gated cell to the flip-flop and to control the power consumption of the clock signal part.

Abstract: Conductive planes in a power delivery region of a microelectronic package substrate are stitched to correlated conductive planes in a signal region of the substrate. The conductive planes occupy varying horizontal levels of the substrate and are stitched together at a junction between the power delivery region and the signal region of the substrate using alternating tabs connected with vias.

Abstract: An electronic component includes an internal conductor (conductor coil) made of a metal that is embedded in a molded body. The molded body is formed by molding a ferrite resin into a fixed shape, such that at least a portion of the internal conductor is exposed on the surface of the molded body, and external electrodes, which are connected to the internal conductor, are provided in a fixed area, including the exposed portion of the internal conductor, on the surface of the molded body. The electronic component is manufactured by depositing palladium at a density of about 0.5 &mgr;g/cm2 to about 1.5 &mgr;g/cm2 in the area in which the internal conductor is not exposed on the molded body, and at a density of about 0.05 &mgr;g/cm2 to about 0.3 &mgr;g/cm2 on the internal conductor exposed on the surface of the molded body. The external electrodes are formed via a process of forming a metal film (electroless plating film) on the surface of the molded body by conducting electroless plating.

Abstract: A semiconductor nonvolatile memory device improving reproducibility and reliability of insulation breakage of a silicon oxide film and capable of reducing the manufacturing cost and a method for production of the same, wherein each of the memory cells arranged in a matrix form has an insulating film breakage type fuse comprising an impurity region of a first conductivity type formed on a semiconductor substrate, a first insulating film formed on the semiconductor substrate while covering the impurity region, an opening formed in the first insulating film so as to reach the impurity region, and a first semiconductor layer of a first conductivity type, a second insulating film, and a second semiconductor layer of a second conductivity type successively stacked in the opening from the impurity region side, or has an insulating film breakage type fuse comprising an impurity region of a first conductivity type in the first semiconductor layer having an SOI structure, a first insulating film on the SOI layer, an op

Abstract: The present invention is a level of an integrated circuit. The level of integrated circuit has a first area having a plurality of features having a first density and the level of the integrated circuit has a second area adjacent to the first area wherein the second area has a plurality of dummy features having a density substantially similar to the first density.

Abstract: A compact semiconductor circuitry device capable of providing a high production efficiency and of shortening time required for packaging and a method for manufacturing a same are provided. A terminal supplying tape having a metal thin film member mounted, on a base material film, in a same arrangement pattern as for a chip terminal of a semiconductor chip and in a state in which it can be peeled off, is prepared in advance. The terminal supplying tape and the semiconductor chip are so disposed as to face each other. The metal thin film member of the terminal supplying tape is connected to the chip terminal, with the terminal supplying tape remaining fixed on the base material film. Then, the base material film is peeled off. An underfill is mounted as necessary. A resin molded portion is also mounted.

Abstract: Conductive planes in a power delivery region of a microelectronic package substrate are stitched to correlated conductive planes in a signal region of the substrate. The conductive planes occupy varying horizontal levels of the substrate and are stitched together at a junction between the power delivery region and the signal region of the substrate using alternating tabs connected with vias.

Abstract: A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semiconductor substrate. A portion of the well forming layer is removed effective to form at least one well within the well forming layer. An array of memory cell capacitors is formed within the well. The peripheral memory circuitry is formed laterally outward of the well forming layer memory array well. In one implementation, memory circuitry includes a semiconductor substrate. A plurality of word lines is received over the semiconductor substrate. An insulative layer is received over the word lines and the substrate. The insulative layer has at least, one well formed therein. The well has a base received over the word lines. The well peripherally defines an outline of a memory array area.

Abstract: The present invention relates to an integrated circuit, at least one portion of which includes at least one group of standby cells for possible connection to said portion of the integrated circuit by replacement connections, the length of which cannot exceed a predetermined value. The inputs and outputs of the standby cells are connected to metal standby tracks being disposed on the circuit such that any node of the circuit portion is distant by at most said predetermined value from any point on the tracks.

Abstract: A semiconductor memory device includes a bit line stack and a storage node contact hole which are aligned at bit line spacers formed at both side walls of the bit line stack and exposes a pad. The semiconductor memory device includes a multi-layered storage node contact plug in which a first storage node contact plug and a second storage node contact plug are sequentially formed. The first storage node contact plug is formed of titanium nitride and the second storage node contact plug is formed of polysilicon. An ohmic layer may be formed on the pad and under the first storage node contact plug. A barrier metal layer, which acts as a third storage node contact plug, may be formed on the second storage node contact plug.

Abstract: A function cell capable of shortening the term necessary for circuit designing, a semiconductor device including the function cell, and a semiconductor circuit designing method using the function cell are obtained. The semiconductor device includes first and second function cells that realize the same logic circuit function and have different electrical characteristics from each other. The first function cell includes a first externally connected interconnection. The second function cell includes a second externally connected interconnection. The external shape of the first function cell is almost the same as the external shape of the second function cell. The position of the first externally connected interconnection on the first function cell plane is almost the same as the position of the plane.

Abstract: In an integrated circuit structure, the improvement comprising a self-passivating Cu-laser fuse characterized by resistance to oxidation and corrosion and improved adhesion in the interface between Cu and metallization lines and Cu and a dielectric cap subsequent to blowing the fuse by an energizing laser, the fuse comprising:

Abstract: Disclosed is a contact hole forming method capable of reducing parasitic capacitance between a conductive layer patterns, preventing bad contacts caused by mask misalignment and effectively filling an interlayer insulating layer between the conductive layer patterns. The method including forming many conductive layer patterns on a substrate, forming an interlayer insulating layer on a resulting structure where the conductive layer patterns are completed, exposing a conductive layer pattern which at least one sidewall of a contact region between conductive layer patterns is neighboring the contact region, and forming an insulating spacer on the sidewall of the exposed conductive layer pattern.

Abstract: A semiconductor memory device may be formed from a pair of transfer MOS transistors 1, 2 controlled by a word line 11 and a pair of data retaining flip-flop circuit formed from serially connected load elements 5, 6 and drive MOS transistors 3, 4. In the semiconductor memory device, the transfer MOS transistors 1, 2 have a threshold voltage greater than a threshold voltage of the drive MOS transistors 3, 4. The memory device may display an improved &bgr; ratio, and reduce the size of the drive MOS transistors to thereby reduce the cell area.

Abstract: Disclosed is a nonvolatile memory device comprising a semiconductor substrate defining first and second active regions arranged in one direction; a first gate insulating layer and a floating gate deposited on the first and second active regions in a predetermined pattern; a second gate insulating layer and a control gate line deposited in one direction perpendicular to the first and second active regions and covering the floating gate; first impurity regions formed in the first and second active regions at one side of the control gate line; second impurity regions formed in the first and second active regions at other side of the control gate line; first contact plugs contacted with the first impurity regions; and a common conductive line formed in one direction on the semiconductor substrate at the other side of the control gate line, for connecting the second impurity regions of the first and second active regions.

Abstract: Integrated circuit arrangement having at least one electrical conductor which, when a current flows through it, produces a magnetic field which acts on at least a further part of the circuit arrangement, wherein seen in cross section, the electrical conductor (2, 3, 16) has at least one recess (17) or depression, or a region (22) of reduced conductivity on the side facing that part, in order to influence the magnetic field which can be produced.

Abstract: A read only memory (ROM) device includes a semiconductor substrate having a first type of conductivity, and a plurality of memory cells on the semiconductor substrate. Each memory cell includes first and second regions of a second conductivity type opposite the first conductivity type. A first dielectric layer is on the plurality of memory cells, and a plurality of first contacts extend through the first dielectric layer for contacting the first regions. A second dielectric layer is on the first dielectric layer and the plurality of first contacts. A plurality of second contacts extend through the second dielectric layer and overlie the corresponding second regions.

Abstract: Techniques for self assembly of macro-scale objects, optionally defining electrical circuitry, are described, as well as articles formed by self assembly. Components can be joined, during self-assembly by minimization of free energy, capillary attraction, or a combination.

Abstract: A semiconductor device having regions for forming a plurality of functional blocks and a region for forming wiring layers for connecting the functional blocks, wherein each of the regions for forming the functional blocks includes a multilayer wiring, and the region for forming the wiring layers for connecting adjacent functional blocks includes a coaxial line comprised of a signal line and a ground line surrounding the signal line via an insulating film.

Abstract: Layers of metallic lines and layers of memory cells are disposed alternately one above the other. The memory cells each have a diode and a memory element connected in series therewith. The memory element has a layer structure with a magnetoresistive effect. The diode has a layer structure containing at least two metal layers and an insulating layer disposed in between. The layer structure of the memory element and the layer structure of the diode are disposed above one another. The metallic lines of a respective one of the layers run parallel to one another. The metallic lines of mutually adjacent layers run transversely with respect to one another.

Abstract: A trench isolation structure for a semiconductor is provided including an isolation ring and an isolation path. The isolation ring surrounds active semiconductor areas and is bordered on the outside by inactive semiconductor area. The isolation path extends from the isolation ring through the inactive semiconductor area. A first level conductor on the isolation path electrically connects or capacitively couples a device in the active semiconductor area to a location on the substrate outside the isolation ring. The isolation path has a configuration derived from the layout of the conductor.

Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in increase of time required for manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved in the entire part of the dummy region FA. Moreover, increase of mask data can be controlled when the first dummy patterns DP1 occupy the relatively wide region among the dummy region FA.

Abstract: An auto placement and routing device lays out wiring with consideration for influences of an increase in an effective coupling capacitance. A layout data generation unit 11 allots signal lines (21 to 27) to grids (11, 13, 15, 17, 19, 111, 113), respectively. The signal lines (21, 23, 25, 27) have a signal attribute B, and the signal lines (22, 24, 26) have a signal attribute A. Thus, the signal line having the signal attribute A and the signal line having the signal attribute B are placed by turns so that the signal lines having the same signal attribute are not to be adjacent to each other. Accordingly, the potential transitions of the signal lines (23, 25) adjacent to an observed signal line (24) do not take place at a time when the potential transition of the observed signal line (24) takes place. This prevents an increase in the effective coupling capacitance of the observed signal line (24) due to the potential transitions of the signal lines (23, 25) adjacent to the observed signal line (24).

Abstract: The present invention discloses a semiconductor memory device having a bit line and a metal contact stud, wherein the metal contact stud is formed on a different layer from a layer on which the bit lines are formed.

Abstract: A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby creating a double metal scheme wherein the strapping layer is a second metal layer overlying metal wordlines. In a method of a first embodiment the strapping material is electrically connected to the digit line through a planar landing pad overlying the conductive plug. An insulative material is sloped to the planar landing pad in order to provide a surface conducive to the formation of the strapping material.

Abstract: The present invention relates to a memory and an information apparatus and more specifically realizes a memory having large capacity through a simplified process and an information apparatus utilizing the same memory by generating the data cell region with a process that is different from the process used to generate the system region to control the data cells.