Abstract: A method for manufacturing a nonvolatile semiconductor memory device having a step of forming a first gate electrode on a peripheral circuit portion and a second gate electrode on a memory cell portion, a step of introducing impurity into the peripheral circuit portion and memory cell portion, a step of forming a first insulating film above at least the memory cell portion, and a step of annealing the semiconductor substrate into which the impurity has been introduced. The first gate electrode has a first gate length. The second gate electrode has a second gate length shorter than the first gate length.

Abstract: A NAND type non-volatile memory device and a method for forming the same. Well bias lines are disposed substantially parallel to other wiring lines at equal intervals. Active regions that are electrically connected to the well bias line are disposed substantially parallel to other active regions at the same equal intervals. As a result, continuity and repeatability in patterns may be maintained and pattern defects may be minimized or prevented.

Abstract: There is disclosed a liquid crystal display for a mobile phone that is adaptive for minimizing horizontal flicker. A liquid crystal display for a mobile phone according to an embodiment of the present invention includes a liquid crystal display panel where liquid crystal cells are each arranged in a matrix at each intersection part of data lines and gate lines; and a driver supplying a data signal to the data line and, in addition, supplying a gate signal to the adjacent gate lines in a different direction from each other.

Abstract: In a NAND type nonvolatile memory device, a first insulating layer covers a common drain region formed in a string active region and a peripheral active region. A second insulating layer covers the first insulating layer. A bit line plug penetrates the first and second insulating layers and is connected to the common drain region. A peripheral lower plug penetrates the first insulating layer and is connected to the peripheral active region. A peripheral upper plug penetrates the second insulating layer and is stacked on the peripheral lower plug.

Abstract: An NROM semiconductor memory device and fabrication method are disclosed. According to one aspect, a method for fabricating an NROM semiconductor memory device can include providing a plurality of u-shaped MOSFETs, which are spaced apart from one another and have a multilayer dielectric. The dielectric suitable for charge trapping along rows in a first direction and alone columns in a second direction in trenches of a semiconductor substrate. Source/drain regions are provided between the u-shaped MOSFETs in interspaces between the rows which run parallel to the columns. Isolation trenches are provided in the source/drain regions between the u-shaped MOSFETs of adjacent columns as far as a particular depth in the semiconductor substrate. The isolation trenches are filled with an insulation material. Word lines are provided for connecting respective rows of u-shaped MOSFETs.

Abstract: A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure.

Abstract: A method for making a memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure which traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.

Abstract: In the present invention, a method for manufacturing a liquid crystal display is provided. The method includes steps of providing a substrate, forming a first metal layer on the substrate, etching the first metal layer to form a plurality of gate lines on the substrate, forming a common electrode on the substrate, forming a second metal layer on the substrate, etching the second metal layer to form a first electrode, a second electrode, a common line and a plurality of data lines on the substrate, and forming a pixel electrode overlapping the common electrode, wherein the gate lines intersect the data lines to form at least one enclosed area, the common electrode and the pixel electrode are positioned in the enclosed area, the first electrode is connected to the pixel electrode and the second electrode is connected to the data lines.

Abstract: A semi-transmissive type liquid-crystal display device suppresses the reduction and corrosion of the transmission or common electrode due to the cell corrosion reaction with a simple method. In each pixel region, the reflection electrode is formed over the glass plate, where the interlayer insulating film and the barrier metal film intervene between them. The reflection electrode is electrically connected to the transmission electrode by way of the barrier metal film. The transmission electrode and the corresponding scanning line thereto are apart from each other at a distance of 2 ?m (preferably, 3 ?m) or greater. A developer solution penetrating through the crack formed in the barrier metal film does not reach the transmission electrode (or common electrode), preventing the reduction and corrosion of the transmission or common electrode.

Abstract: A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.

Abstract: Disclosed is a method for manufacturing an array substrate utilizing a laser ablation process. With the laser ablation process, a photoresist layer is removed along with the transparent conductive layer therefrom, while maintaining other portions of the transparent conductive layer. Moreover, the laser ablation process of the invention does not need additional photo-mask, so the fabrication cost can be reduced.

Abstract: An electro-optical device includes a substrate having a display region; TFTs each including a first electrode in the display region, a first insulating layer on the first electrode, a second electrode on the first insulating layer, and a second insulating layer on the second electrode; and terminals each including a first metal on a protruding section extending from the display region, which is located at the same level and made of the same metal as the first electrode, a second metal which is located at the same level and made of the same metal as the second electrode, and which partly overlaps the first metal in plan view, and a portion of the first insulating layer. The first insulating layer separates the first and second metals and the first metal is electrically connected to the first electrode or the second metal is electrically connected to the second electrode.

Abstract: The object of providing a method for manufacturing solid body electrolyte memory cells or CB memory cells, respectively, which is suited for the simplified manufacturing of highly dense arrays with crosspoint architecture is solved by the present invention in that the solid body electrolyte memory cells are manufactured by self-aligned etching of the word lines that constitute simultaneously the top electrodes of the memory cells, and of the CB memory cells themselves. An advantage of the inventive method consists in that no via lithography is required, so that the manufacturing method is easier to perform, less expensive, and yields reliable results.

Abstract: An integrated circuit memory system including a substrate formed with equidistant spaced shallow trench isolation regions. Forming active regions and dummy active regions within the substrate between the equidistant spaced shallow trench isolation regions. Forming sources and drains within the active regions. Providing wordlines and source lines extending in a first direction and bitlines extending in a second direction. Forming contact regions over the dummy active regions for strapping the wordlines and the source lines to the bitlines.

Abstract: An active matrix type display device, wherein a pixel circuit is formed using a plurality of thin film transistors in which thin semiconductor films forming channel regions of the thin film transistors are made in different crystal states.

Abstract: A pixel unit of TFT-LCD array substrate and a manufacturing method thereof is disclosed. In the manufacturing method, besides a first insulating layer and a passivation layer, a second insulating layer is adopted to cover the gate island, and forms an opening on the gate island to expose the channel region, the source region and the drain region of the TFT. A gray tone mask and a photoresist lifting-off process are utilized to perform patterning, so that the TFT-LCD array substrate can be achieved with just three masks.

Abstract: A semiconductor integrated circuit has a first functional block, a second functional block, and a signal line routed from the first functional block to the second functional block in a metal interconnection layer. A complementary pair of metal-oxide-semiconductor circuits with source, gate, and drain terminals are located near the signal line between the first and second functional blocks. The drain terminals extend to the same metal interconnection layer as the signal line, but are not connected to the signal line. The circuit can be redesigned to invert the signal transmitted on the signal line by altering a single mask defining the metal interconnection layer, so as to divide the signal line into a first part connected to the gate terminals and a second part connected to the drain terminals of the complementary pair of metal-oxide-semiconductor circuits.

Abstract: A method for manufacturing electrically non-active structures for an electronic circuit integrated on a semiconductor substrate is provided, with the electronic circuit including first and second electrically active structures. The method includes inserting the electrically non-active structures in the electronic circuit to make uniform a surface above the semiconductor substrate. The inserting includes identifying, among the electrically non-active structures, a first group of electrically non-active structures to be adjacent the first and second electrically active structures, and identifying, among the electrically non-active structures, a second group of electrically non-active structures not adjacent to the first and second electrically active structures. The method further includes defining, on the semiconductor substrate, the first and second groups of electrically non-active structures through different photolithographic steps.

Abstract: An array substrate for an in-plane switching mode liquid crystal display device includes: a gate line on a substrate; a data line crossing the gate line to define a pixel region on the substrate; a common line parallel to and spaced apart from the gate line; a gate electrode connected to the gate line; a semiconductor layer disposed over the gate electrode, wherein an area of the semiconductor layer is less than an area of the gate electrode; a source electrode connected to the data line, and a drain electrode spaced apart from the source electrode, the source and drain electrodes disposed on the semiconductor layer; a plurality of pixel electrodes integrated with the drain electrode and extending from the drain electrode in the pixel region; and a plurality of common electrodes connected to the common line and alternately arranged with the plurality of pixel electrodes, wherein each of the source electrode, the drain electrode, the data line and the plurality of pixel electrodes are comprised from a first co

Abstract: A liquid crystal display (LCD) device having an array substrate with a top gate type TFT includes a first transparent metal layer deposited to enhance the adhesion between a data metal layer and an insulating substrate before a data metal deposition, and a second transparent metal layer deposited to enhance the adhesion between a gate metal layer and an insulating substrate before a gate metal deposition. The LCD device having the array substrate with a top gate type TFT can be fabricated with a reduced number of masking or sputtering processes, thereby reducing the fabrication time of the LCD device and increasing the yield of the LCD device.

Abstract: A method of fabricating a thin film transistor substrate for reducing a mask process and, at the same time removing a transparent electrode ITO which remains at a non-display area by a contact hole filling process is disclosed. In the method of fabricating the thin film transistor substrate having a display area and a non-display area where is located at the exterior of the display area, a gate pattern, which is comprised of a gate line which is formed at a display area, a gate electrode which is connected to a gate line, a gate link which is formed at a non-display area, and a lower gate pad electrode which is connected, via a gate link, to a gate line, is formed.

Abstract: Method and apparatus for facilitating signal routing within a programmable logic device having routing resources is described. In an example, the routing resources are formed into groups where, for each of the groups, the routing resources are of a same type. Pairs of the groups are related by an association of at least one routing resource in one group of a pair of groups capable of being electrically connected to at least one other routing resource in another group of the pair of groups.

Abstract: In a method of forming micro traces, stamping techniques are employed to define a target pattern of the micro traces. The stamping is applied to electrically conductive material and may be limited to pressure, but a thermal stamping approach may be utilized. Following the stamping, a portion of the conductive material is removed, leaving the target pattern of conductive micro traces. In the pressure-application step, the pressure or the combination of pressure and temperature is sufficient to at least weaken the integrity of the bulk conductive material along the area of contact. Typically, this step causes shearing of the conductive material. Following the pressure-application step, excess conductive material is removed. In some embodiments of the invention, the thickness of the micro traces is not determined in a single step. The original thickness may be formed using a “seed” material. The subsequent material buildup may occur after the target pattern is established.

Abstract: In an interconnect layout 100, the first gate pattern, the second gate pattern, the first dummy pattern, and the second dummy pattern are arranged so that, if a wavelength of a light used to expose the first gate pattern and the second gate pattern is ?, natural numbers are m1, m2, and m3, the first predetermined distance is P1, the second predetermined distance is P2, the third predetermined distance is P3, a design value of the first predetermined distance is P1?, a design value of the second predetermined distance is P2?, and a design value of the third predetermined distance is P3?, then the first predetermined distance satisfies relationships of P1=m1? and P1??0.1??P1?P1?+0.1?, the second predetermined distance satisfies relationships of P2=m2? and P2??0.1??P2?P2?+0.1?, and the third predetermined distance satisfies relationships of P3=m3? and P3??0.1??P3?P3?+0.1?.

Abstract: A device includes a substrate; a bank provided on the substrate; and a metal wiring in a wiring forming region of the substrate that is sectioned by the bank with a liquid phase method. The metal wiring includes a first film formed along a bottom of the wiring forming region and a side face of the bank facing the wiring forming region. The metal wiring also includes a second film disposed on the first film.

Abstract: To ensure the connectability of wiring lines in a semiconductor device having terminals or reservoirs, plural terminals of a cell, which constitutes the semiconductor device, are each formed in a shape having a length corresponding to two or more lattice points. The terminals are arranged so that one or more lattice points are interposed between adjacent terminals. Among the terminals, as to terminals that are adjacent to each other in their shorter direction, it is allowable for them to partially overlap each other in their shorter direction. In this state, second-layer wiring lines are connected to the terminals via through holes, whereby reservoirs can be generated at the terminals, respectively.

Abstract: A multibit phase change memory device structured such that a plurality of individual phase change memory devices are aligned in a plan area or vertically, and a method of driving the same are provided. The multibit phase change memory device includes a phase change material layer having a plurality of contact portions being in contact with a heating electrode, and having a plurality of active regions, each active region forming a unit phase change memory device. The phase change material layer may be composed of one material layer in which the plurality of active regions are aligned in plural arrays. Alternatively, the phase change material layer may be composed of a plurality of phase change material layers in which one or plural active regions are respectively aligned in one array. The plurality of phase change material layers may be disposed in a same level of a plan area, or the plurality of phase change material layers may be respectively disposed on different plan areas in a same vertical line.

Abstract: A method for fabricating a semiconductor product first provides an embedded semiconductor product comprising: (1) a logic region having formed therein a logic field effect transistor device; (2) a memory region having formed therein a memory field effect transistor device; and (3) a kerf region having formed therein a kerf field effect transistor device. The method also provides for measuring for the embedded semiconductor product a gate electrode linewidth for each of the logic field effect transistor device, the memory field effect transistor device and the kerf field effect transistor device. The measured gate electrode linewidths may be compared among themselves or to specified target values for purposes photoexposure process control.

Abstract: Primitive cells, which are circuit patterns of the constituent elements of a semiconductor device, are arranged in the element formation area of a semiconductor device, and at least one fill cell with a diffusion layer and no wiring, is arranged in the vacant areas that are generated in the element formation area after the primitive cells have been arranged.

Abstract: A thin film transistor substrate for a display device having a plurality of thin film transistors and pixel electrodes connected to the thin film transistors, said thin film transistor substrate includes: a plurality of pad electrodes in a non-display area of the display device for applying signals to the plurality of thin film transistors in a non-display area of the display device; a protective film covering the pad electrodes in the non-display area; and a slit in the protective film adjacent to at least one of the plurality of pad electrodes.

Abstract: The facility of operation in a manufacturing process and the reliability of the finished product can be improved by making a design based on two basic wiring pattern layers in which wiring traces are formed with regularity, and a basic via array layer inserted between the two basic wiring pattern layers, in which vias are formed with regularity

Abstract: An LDMOS device includes elementary MOS cells. The gate structure of the elementary cell includes a first conductor material finger. The LDMOS device includes first metal stripes for contacting source regions, second metal stripes for contacting drain regions, and third metal stripes placed on inactive zones for contacting a material finger by forming a contact point. The contact point is formed by a first prolongation of the material finger for connecting with one of the third stripes. The third metal stripe includes at least one fourth metal stripe placed on a separation zone. The material finger has a second prolongation and the fourth metal stripe has a first prolongation to form an additional contact point.

Abstract: In a preferred embodiment, the invention provides a circuit and method for a high reliability triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, three voting structures with inputs from the first, second, and third settable memory elements and control to the settable memory elements determine the logical values held on the settable memory elements. The propagation delay through a latch is the only propagation delay of the triple redundant latch.

Abstract: The present invention discloses a TFT array substrate that is fabricated using a four-mask process and a method of manufacturing that TFT array substrate. The gate line and gate electrode of the array substrate is surrounded by the metallic oxide after finishing a first mask process using thermal treatment. As a result, the gate line and gate electrode are not eroded and damaged by the etchant and stripper during a fourth mask process. Further, buffering layer can optionally be formed between the substrate and the gate line and gate electrode. Thus, silicon ions and oxygen ions included in the substrate are not diffused into the gate line and electrode. Accordingly, the line defect such as a line open of the gate line and gate electrode is prevented, thereby preventing inferior goods while increasing the manufacturing yield.

Abstract: A method of making a circuitized substrate in which the substrate's commoning bar, used during the plating of the circuitry on the substrate, is terminated from the various conductors using a laser. In a preferred embodiment, the laser acts through a dielectric layer (soldermask) which is applied over the circuitry, including the commoning bar and connected parts. The laser may also be used to expose selected ones of the circuit's other parts, including various pads used to accommodate a wirebond (from a chip) and also solder balls for eventual placement of the substrate on a larger circuit board.

Abstract: By making use of the remaining film thickness distribution (CMP pattern ratio) that is a distribution of estimates of the remaining film thickness after the CMP process, the first region A is abstracted from the patterning mask that corresponds to the region X where values of the remaining film thickness distribution is higher than the first threshold. Correction of the layout of the first dummy mask pattern (40a) is designed for forming the first dummy active region having a width no less than a predetermined width on the semiconductor outside the active region forming mask pattern (16) within the region A. In accompany with this patterning mask correction, correction of the insulation film removing mask pattern (40a?) is designed in the first region A? of the insulation film removing mask so as to removed a predetermined area of the insulation film formed on the first dummy active region. Based on these designs, actual patterning and insulation film removing masks are formed.

Abstract: The semiconductor regions for source and drain of unused p-channel type MISFETQp and the power supply wiring 2VDD are electrically connected and the semiconductor regions for source and drain of n-channel type MISFETQn and the power supply wiring 2VSS are electrically connected. Moreover, the switch elements 3SW1, 3SW2 are formed of the p-channel type MISFETQp and n-channel type MISFETQn in the basic cells and these switch elements 3SW1, 3SW2 are discretely arranged in the n-well NWL and p-well PWL. Thereby, noise generated in the wells can be reduced in the semiconductor device where the switch elements are provided between the power supply wiring and wells and the threshold voltage of transistor formed in the well can be controlled through the ON/OFF controls of such switch elements.

Abstract: A semiconductor manufacturing device includes a prober whose needles are at once engaged for contacting pads of two chip forming regions within a wafer. In one chip forming region, trimming is performed, while in the other chip forming region, inspecting posterior to trimming is performed.

Abstract: First, a conductive material made of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer including a lower layer of Cr and an upper layer of aluminum-based material is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and a thermal treatment process using annealing step is executed. At this time, all or part of aluminum oxide (AlOx) layer having a high resistivity, which is formed on the gate wire and/or the data wire during manufacturing process, may be removed. Then, the passivation layer is patterned to form contact holes exposing the drain electrode, the gate pad and the data pad, respectively.

Abstract: Methods are provided for fabricating plated through hole conductive core substrate which eliminate the secondary step of producing a through hole in the dielectric material plugging the core through hole. In one embodiment of the method in accordance with the invention, a two-step lamination process is provided. One side of the conductive core is provided with a dielectric laminate, a portion of which flows into and coats the core through hole wall. Excess dielectric material flows out of the core through hole preventing plugging. Similarly, the other side of the conductive core is provided with a dielectric laminate, a portion of which flows into the core through hole completing the coating of the core through hole wall forming a dielectric liner. The dielectric liner insulates the conductive core through hole wall from a conductive layer deposited onto the dielectric liner forming a plated through hole.

Abstract: Methods of forming and the integrated circuit device structure formed having vertical interfaces adjacent an existing crack stop around a perimeter of a chip, whereby the vertical interface controls cracks generated during side processing of the device such as dicing, and in service from penetrating the crack stop. The vertical interface is comprised of a material that prevents cracks from damaging the crack stop by deflecting cracks away from penetrating the crack stop, or by absorbing the generated crack energies. Alternatively, the vertical interface may be a material that allows advancing cracks to lose enough energy such that they become incapable of penetrating the crack stop. The present vertical interfaces can be implemented in a number of ways such as, vertical spacers of release material, vertical trenches of release material or vertical channels of the release material.

Abstract: A field programmable gate array is described for use in a semiconductor chip such as a VLSI chip. The array is provided with variable wire-through porosity to allow for optimum chip-level routing through the array. This is achieved by dividing the array into blocks which can be individually assessed for required porosity. Then blocks that have been prefabricated with differing porosities are placed in the macro to optimize local chip level routing. The routing of wires is determined by developing a chip floor plan to include early timing allocation and a proposed placement of the array. The floor plan is then overlaid with critical logical wiring nets. From this, an initial selection of blocks is made based on proposed wiring density, and the macro is assembled with the blocks strategically placed therein. The procedure is likewise applicable to other types of densely obstructed cores embedded with a chip.

Abstract: A method of making a circuitized substrate in which a commoning bar, used during the plating of the circuitry on the substrate and coupled to a second set of conductors which in turn are coupled to a first set of conductors, is terminated from the second set of conductors.

Abstract: A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby creating a double metal scheme wherein the strapping layer is a second metal layer overlying metal wordlines. In a method of a first embodiment the strapping material is electrically connected to the digit line through a planar landing pad overlying the conductive plug. An insulative material is sloped to the planar landing pad in order to provide a surface conducive to the formation of the strapping material.

Abstract: Power is gated from global terrain to a voltage island while controlling leakage and managing transient power supply noise. The voltage island includes a field effect transistor (FET) power gate, a first connection to a global voltage source and a second connection to a disable signal source, and an island voltage net for supplying voltage to devices on the island. A power gate control circuit is responsive to the disable signal source for generating a test signal for selectively turning off the FET power gate as the disable signal source goes to a logical ‘1’, and for turning on the FET power gate as said disable source goes to a logical ‘0’. The FET power gate is responsive to the disable signal source being off for connecting the island voltage net to the global voltage source.

Abstract: A method of making a circuitized substrate in which the substrate's commoning bar, used during the plating of the circuitry on the substrate, is terminated from the various conductors using a laser. In a preferred embodiment, the laser acts through a dielectric layer (soldermask) which is applied over the circuitry, including the commoning bar and connected parts. The laser may also be used to expose selected ones of the circuit's other parts, including various pads used to accommodate a wirebond (from a chip) and also solder balls for eventual placement of the substrate on a larger circuit board.

Abstract: A reliable microchip controller board and a manufacturing method thereof suitable for mass production are provided. A board wherein a programmable microchip controller is mounted includes; terminals for writing a program into the microchip controller and a circuit pattern connecting an operating terminal to shared terminals which are disconnected. A non-programmed microchip controller is mounted on the board in a state where patterns are disconnected and then programmed. The disconnected portion is connected thereafter.

Abstract: The present invention provides a system for electrostatic discharge protection in a semiconductor device, utilizing a silicon-controlled rectifier (502). The system includes the silicon controlled rectifier, which has a first p-type region (508) coupled to a voltage node (504), a first n-type region (512) having a first side adjoining the first p-type region, a second p-type region (510) having a first side adjoining a second side of the first n-type region, and a second n-type region (514) having a first side adjoining a second side of the second p-type region. A clamping structure (506) is intercoupled between the second n-type region and ground, to prevent the junction between the second p-type region and the second n-type region from retaining a forward bias. A switching structure (518) is intercoupled between the second p-type region and ground to ground the second p-type region during normal operation of the semiconductor device.

Abstract: A semiconductor integrated circuit device has: a semiconductor substrate defining a plurality of rows, each row including areas for a sequence of cells; a plurality of active regions disposed in each of the rows constituting semiconductor elements of associated cells; and a wiring region of stripe shape elongated along a direction of row, defined on the semiconductor substrate outside of the active regions in each row, and including wirings belonging to the associated cells, each wiring region having height in a direction crossing the row direction, the wiring region having locally different height.

Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.