Making Regenerative-type Switching Device (e.g., Scr, Igbt, Thyristor, Etc.) Patents (Class 438/133)
  • Patent number: 10319714
    Abstract: High voltage drain-extended metal-oxide-semiconductor (DEMOS) bipolar switches for electrical overstress protection are provided. In certain configurations herein, an electrical overstress switch embodiment for providing electrical overstress protection, such as electrostatic discharge/electrical overstress (ESD/EOS) protection includes both a DEMOS device and an embedded bipolar device. The switch is implemented to achieve the advantages provided by the combined conduction of DEMOS and bipolar devices. For example, the DEMOS device provides surface conduction at the gate region for relatively fast switch device turn on and low voltage overshoot, while the bipolar device provides high current conduction during stress condition and a high holding voltage characteristics to prevent latch-up in mission critical integrated circuit applications.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: June 11, 2019
    Assignee: ANALOG DEVICES, INC.
    Inventors: Sirui Luo, Javier Alejandro Salcedo
  • Patent number: 10274787
    Abstract: The present disclosure provides a liquid crystal display apparatus having a reduced area of a dark line occurring when light is transmitted through a pixel region, and excellent transmittance of light and image quality.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: April 30, 2019
    Assignee: Sakai Display Products Corporation
    Inventor: Mitsuaki Hirata
  • Patent number: 10224348
    Abstract: Disclosed are a pixel unit structure and a display device. The pixel unit structure includes a thin film transistor formed on a substrate, and a first insulating layer, a first transparent electrode layer, a second insulating layer, and a second transparent electrode layer formed in sequence from bottom to top above the thin film transistor. A storage capacitor is formed between the first transparent electrode layer and the second transparent electrode layer.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: March 5, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jianjian Ying, Peng Du
  • Patent number: 9885917
    Abstract: A liquid crystal display panel and a method for manufacturing the same. The liquid crystal display panel includes lower substrate having a first substrate; an upper substrate having a second substrate that is opposite to the first substrate; a liquid crystal layer is disposed between the lower and upper substrates such that liquid crystals are arranged in a first region between the first substrate and the second substrate; and a dam pattern arranged in a second region which surrounds a circumference of the first region as a region between the first substrate and the second substrate, the dam pattern having both a physical barrier function and a chemical barrier function.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: February 6, 2018
    Assignee: Samsung Display Co., Ltd
    Inventors: Taek Joon Lee, Tae Jin Kong, Sang Gyun Kim, Su Jeong Kim, Seul Gee Lee
  • Patent number: 9799729
    Abstract: A method of manufacturing a semiconductor device includes: forming field electrode structures extending in a direction vertical to a first surface in a semiconductor body; forming cell mesas from portions of the semiconductor body between the field electrode structures, including body zones forming first pn junctions with a drift zone; forming gate structures between the field electrode structures and configured to control a current flow through the body zones; and forming auxiliary diode structures with a forward voltage lower than the first pn junctions and electrically connected in parallel with the first pn junctions, wherein semiconducting portions of the auxiliary diode structures are formed in the cell mesas.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: October 24, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Oliver Blank, Franz Hirler, Martin Henning Vielemeyer
  • Patent number: 9595678
    Abstract: A photovoltaic element (110) is proposed for conversion of electromagnetic radiation to electrical energy. The photovoltaic element (110) may especially be a dye solar cell (112). The photovoltaic element (110) has at least one first electrode (116), at least one n-semiconductive metal oxide (120), at least one electromagnetic radiation-absorbing dye (122), at least one solid organic p-semiconductor (126) and at least one second electrode (132). The p-semiconductor (126) comprises at least one metal oxide (130).
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: March 14, 2017
    Assignee: BASF SE
    Inventors: Neil Gregory Pschirer, Ingmar Bruder, Rüdiger Sens, Peter Erk
  • Patent number: 9520561
    Abstract: Provision of fabrication, construction, and/or assembly of a memory device including a two-terminal memory portion is described herein. The two-terminal memory device fabrication can provide enhanced capabilities in connection with precisely tuning on-state current over a greater possible range.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: December 13, 2016
    Assignee: CROSSBAR, INC.
    Inventors: Kuk-Hwan Kim, Ping Lu, Chen-Chun Chen, Sung Hyun Jo
  • Patent number: 9478646
    Abstract: A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: October 25, 2016
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Anup Bhalla, Madhur Bobde, Yongping Ding, Xiaotian Zhang, Yueh-Se Ho
  • Patent number: 9312330
    Abstract: Provision of a super-junction semiconductor device capable of reducing rises in transient on-resistance at the time of repeated switching operation. A super-junction structure is provided that has a striped parallel surface pattern, where a super-junction stripe and a MOS cell 6 stripe are parallel, and a p column Y2 over which no MOS cell 6 stripe is arranged and a p column Y1 over which the MOS cell 6 stripe is arranged are connected at an end.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: April 12, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Manabu Takei
  • Patent number: 9299818
    Abstract: An object of the present invention is to provide a trench gate type IGBT achieving both retention of withstand voltage and lowering of ON-state voltage and to provide a method for manufacturing the trench gate type IGBT. The IGBT according to the present invention is an SJ-RC-IGBT which includes a drift layer having super junction structure, and includes an IGBT area and an FWD area on the rear surface. In the IGBT according to the present invention, a first drift layer has an impurity concentration of 1×1015 atms/cm3 or higher and lower than 2×1016 atms/cm3, and a thickness of 10 ?m or larger and smaller than 50 ?m; and that a buffer layer has an impurity concentration of 1×1015 atms/cm3 or higher and lower than 2×1016 atms/cm3, and a thickness of 2 ?m or larger and smaller than 15 ?m.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: March 29, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinji Aono, Tadaharu Minato
  • Patent number: 9240471
    Abstract: An electrostatic discharge protection circuit is disclosed. A method of manufacturing a semiconductor structure includes forming a semiconductor controlled rectifier including a first plurality of fingers between an n-well body contact and an anode in an n-well, and a second plurality of fingers between a p-well body contact and a cathode in a p-well.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: January 19, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: James P. Di Sarro, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam
  • Patent number: 9202938
    Abstract: A method for manufacturing a transient voltage suppressing (TVS) array substantially following a manufacturing process for manufacturing a vertical semiconductor power device. The method includes a step of opening a plurality of isolation trenches in an epitaxial layer of a first conductivity type in a semiconductor substrate followed by applying a body mask for doping a body region having a second conductivity type between two of the isolation trenches. The method further includes a step of applying an source mask for implanting a plurality of doped regions of the first conductivity type constituting a plurality of diodes wherein the isolation trenches isolating and preventing parasitic PNP or NPN transistor due to a latch-up between the doped regions of different conductivity types.
    Type: Grant
    Filed: June 8, 2013
    Date of Patent: December 1, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Madhur Bobde
  • Patent number: 9178147
    Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode comprising hafnium oxide and having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a material including metal titanium and having a second thickness that is less than 25 percent of the first thickness.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: November 3, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Ronald J. Kuse, Tony P. Chiang, Imran Hashim
  • Patent number: 9142264
    Abstract: Techniques for refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region coupled to a source line and a second region coupled to a carrier injection line. Each memory cell may also include a body region capacitively coupled to at least one word line and disposed between the first region and the second region and a decoupling resistor coupled to at least a portion of the body region.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: September 22, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Yogesh Luthra
  • Patent number: 9129983
    Abstract: A memory cell includes a thyristor having a plurality of alternately doped, vertically superposed semiconductor regions; a vertically oriented access transistor having an access gate; and a control gate operatively laterally adjacent one of the alternately doped, vertically superposed semiconductor regions. The control gate is spaced laterally of the access gate. Other embodiments are disclosed, including methods of forming memory cells and methods of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: September 8, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Sanh D. Tang
  • Patent number: 9104975
    Abstract: A memristor apparatus comprising a plurality of meta-stable switching elements.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: August 11, 2015
    Assignee: KnowmTech, LLC
    Inventor: Alex Nugent
  • Patent number: 9093635
    Abstract: Provision of fabrication, construction, and/or assembly of a memory device including a two-terminal memory portion is described herein. The two-terminal memory device fabrication can provide enhanced capabilities in connection with precisely tuning on-state current over a greater possible range.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: July 28, 2015
    Assignee: Crossbar, Inc.
    Inventors: Kuk-Hwan Kim, Ping Lu, Chen-Chun Chen, Sung Hyun Jo
  • Patent number: 9082812
    Abstract: A p-type base layer is selectively formed on a surface of an n-type drift layer; an n-type source layer is selectively formed on a surface of the p-type base layer; and a p-type contact layer is formed to be in contact with the selectively-formed n-type source layer. A p-type counter layer is formed to be in contact with the n-type source layer, so as to overlap the p-type contact layer, so as to be separated from an interface where the p-type base layer and the gate oxide film are in contact with each other, and to be shallower than the p-type base layer. Accordingly, switching destruction caused by process defects in an insulated gate semiconductor device is reduced.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: July 14, 2015
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yuichi Onozawa, Takashi Shiigi
  • Patent number: 9059071
    Abstract: A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: June 16, 2015
    Assignee: ROHM CO., LTD.
    Inventors: Yuji Okamura, Masashi Matsushita
  • Patent number: 9059236
    Abstract: According to one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode; a second semiconductor layer provided between the first semiconductor layer and the second electrode, and the second semiconductor layer having a lower impurity concentration than the first semiconductor layer; a first semiconductor region provided between part of the second semiconductor layer and the second electrode; a second semiconductor region provided between a portion different from the part of the second semiconductor layer and the second electrode, and the second semiconductor region being in contact with the first semiconductor region; and a third semiconductor region provided between at least part of the first semiconductor region and the second electrode.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: June 16, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Ogura, Tomoko Matsudai, Yuichi Oshino, Shinichiro Misu, Yoshiko Ikeda, Kazutoshi Nakamura
  • Publication number: 20150144990
    Abstract: A power semiconductor device may include a first semiconductor region having a first conductivity type, a second semiconductor region having a second conductivity type formed on an upper portion of the first semiconductor region, a third semiconductor region having a first conductivity type formed in an inner portion of an upper portion of the second semiconductor region, a trench gate formed to penetrate from the third semiconductor region to the first semiconductor region and including a first insulating layer formed on a surface thereof, and a second insulating layer formed in a lower portion of the trench gate.
    Type: Application
    Filed: May 8, 2014
    Publication date: May 28, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Hoon PARK, In Hyuk SONG, Dong Soo SEO, Ji Yeon OH, Kee Ju UM
  • Patent number: 9029206
    Abstract: A structure includes first and second silicon controlled rectifiers (SCRs) formed in a substrate. The first and the second SCRs each include at least one component commonly shared between the first and the second SCRs.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: May 12, 2015
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Gauthier, Jr., Junjun Li, Ankit Srivastava
  • Patent number: 9024285
    Abstract: A nanoscale switching device is provided. The device comprises: a first electrode of a nanoscale width; a second electrode of a nanoscale width; an active region disposed between the first and second electrodes, the active region having a non-conducting portion comprising an electronically semiconducting or nominally insulating and a weak ionic conductor switching material capable of carrying a species of dopants and transporting the dopants under an electric field and a source portion that acts as a source or sink for the dopants; and an oxide layer either formed on the first electrode, between the first electrode and the active region or formed on the second electrode, between the second electrode and the active region. A crossbar array comprising a plurality of the nanoscale switching devices is also provided. A process for making at least one nanoscale switching device is further provided.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: May 5, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jianhua Yang, Gilberto Ribeiro, R. Stanley Williams
  • Patent number: 9023692
    Abstract: IGBT and diode are formed with optimal electrical characteristics on the same semiconductor substrate. IGBT region and FWD region are provided on the same semiconductor substrate. There are a plurality of trenches at predetermined intervals in the front surface of an n? type semiconductor substrate, and P-type channel regions at predetermined intervals in the longitudinal direction of the trench between neighboring trenches, thereby configuring a MOS gate. The p-type channel region and n? type drift region are alternately disposed in longitudinal direction of the trench in the IGBT region. The p-type channel region and a p? type spacer region are alternately disposed in the longitudinal direction of the trench in the FWD region. Pitch in longitudinal direction of the trench of p-type channel region in the IGBT region is shorter than pitch in longitudinal direction of the trench of p-type channel region in the FWD region.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: May 5, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Souichi Yoshida, Toshihito Kamei, Seiji Noguchi
  • Patent number: 9018070
    Abstract: The present invention discloses a transient voltage suppressor (TVS) circuit, and a diode device therefor and a manufacturing method thereof. The TVS circuit is for coupling to a protected circuit to limit amplitude of a transient voltage which is inputted to the protected circuit. The TVS circuit includes a suppressor device and at least a diode device. The diode device is formed in a substrate, which includes: a well formed in the substrate; a separation region formed beneath the upper surface; a anode region and a cathode region, which are formed at two sides of the separation region beneath the upper surface respectively, wherein the anode region and the cathode region are separated by the separation region; and a buried layer, which is formed in the substrate below the well with a higher impurity density and a same conductive type as the well.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: April 28, 2015
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Tsung-Yi Huang, Jin-Lian Su
  • Publication number: 20150111347
    Abstract: Electronic device structures including semiconductor ledge layers for surface passivation and methods of manufacturing the same are disclosed. In one embodiment, the electronic device includes a number of semiconductor layers of a desired semiconductor material having alternating doping types. The semiconductor layers include a base layer of a first doping type that includes a highly doped well forming a first contact region of the electronic device and one or more contact layers of a second doping type on the base layer that have been etched to form a second contact region of the electronic device. The etching of the one or more contact layers causes substantial crystalline damage, and thus interface charge, on the surface of the base layer. In order to passivate the surface of the base layer, a semiconductor ledge layer of the semiconductor material is epitaxially grown on at least the surface of the base layer.
    Type: Application
    Filed: June 20, 2014
    Publication date: April 23, 2015
    Inventors: Qingchun Zhang, Anant Kumar Agarwal
  • Publication number: 20150108538
    Abstract: An electrostatic discharge protection device is disclosed. The electrostatic discharge protection device comprises a N+ well, a P doping region, a first N doping region, a plurality of N sub-doping regions, a first N+ doping region, a first P+ doping region, a second N+ doping region, and a second doping region. The P doping region is disposed in the N+ well. The first N doping region is disposed in the P doping region. The plurality of N sub-doping regions is disposed in parallel in the P doping region. The first N+ doping region is disposed in the first N doping region. The first P+ doping region is disposed in the first N doping region. The second N+ doping region is disposed in the P doping region.
    Type: Application
    Filed: January 16, 2014
    Publication date: April 23, 2015
    Applicant: ISSC Technologies Corp.
    Inventor: CHE-HONG CHEN
  • Patent number: 9012881
    Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode comprising hafnium oxide and having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a material including metal titanium and having a second thickness that is less than 25 percent of the first thickness.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: April 21, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Ronald J. Kuse, Tony P. Chiang, Imran Hashim
  • Patent number: 9006839
    Abstract: In a semiconductor substrate of a semiconductor device, a drift layer, a body layer, an emitter layer, and a trench gate electrode are formed. When the semiconductor substrate is viewed in a plane manner, the semiconductor substrate is divided into a first region covered with a heat dissipation member, and a second region not covered with the heat dissipation member. A density of trench gate electrodes in the first region is equal to a density of trench gate electrodes in the second region. A value obtained by dividing an effective carrier amount of channel parts formed in the first region by an area of the first region is larger than a value obtained by dividing an effective carrier amount of channel parts formed in the second region by an area of the second region.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: April 14, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Tadashi Misumi
  • Patent number: 8999768
    Abstract: A semiconductor device and its method of manufacture. In the method, a front surface element structure is formed on a front surface of a semiconductor wafer, for example an SiC wafer. Then, a supporting substrate is bonded to wafer's front surface through an adhesive. The wafer's rear surface is ground and polished to thin it, with the supporting substrate bonded to the wafer. Next a V groove passing through the SiC wafer and reaching the adhesive is formed in the wafer's rear surface, and the wafer is cut into individual chips. An electrode film is formed on the groove's side wall and the chip's rear surface and a Schottky junction is formed between a drift layer, which is the chip, and the film. Then, the film is annealed. A tape is attached to the wafer's rear surface which has been cut into the chips. Then, the supporting substrate peels off from the wafer.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: April 7, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Haruo Nakazawa, Masaaki Ogino, Tsunehiro Nakajima
  • Patent number: 8993397
    Abstract: A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: March 31, 2015
    Assignee: Crossbar, Inc.
    Inventor: Scott Brad Herner
  • Patent number: 8987743
    Abstract: The present disclosure discloses a method for manufacturing a TFT array substrate, comprising: depositing a gate metal layer, a gate insulating layer, a semiconductor layer and a source-drain electrode layer in this order on a base substrate, performing a first photolithograph process to form a common electrode line, a gate line, a gate electrode, a source electrode, a drain electrode and a channel defined between the source electrode and the drain electrode; depositing a passivation layer, performing a second photolithograph process to form a first via hole and a second via hole in the passivation layer; and depositing a pixel electrode layer and a data line layer in this order, perform a third photolithograph process to form a data line connected to the source electrode through the first via hole and a pixel electrode connected to the drain electrode through the second via hole.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: March 24, 2015
    Assignees: Boe Technology Group Co., Ltd., Hefei Boe Optoelectroncis Technology Co., Ltd.
    Inventor: Yunqi Zhang
  • Patent number: 8987778
    Abstract: Embodiments of the invention provide increased ESD protection suitable for high-voltage devices. In one embodiment, an internal DMOS circuit is placed in parallel with a lateral NPN ESD clamp. The clamp has both a high holding voltage, above the operating voltage of the DMOS circuit, and a high maximum current before breakdown. The discharge path of the clamp includes a high-voltage lightly doped well containing a low-voltage higher doped well. The dopant of both wells is the same type, and the interface between the two defines a graded junction. The emitter of the entire circuit is grounded and the collector is coupled to the voltage of the DMOS circuit.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: March 24, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Yue Zu, Hoang Phung Nguyen, Thomas E. Harrington, III
  • Patent number: 8981328
    Abstract: A resistive random access memory cell formed in an integrated circuit includes first and second resistive random access memory devices, each including an anode and a cathode. The anode of the second resistive random access memory device is connected to the anode of the first resistive random access memory device. A programming transistor has a first source/drain terminal connected to a programming potential node, a second source/drain terminal connected to the anodes of the first and second resistive random access memory devices, and a gate connected to a program-enable node.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: March 17, 2015
    Assignee: Microsemi SoC Corporation
    Inventors: Jonathan Greene, Frank Hawley, John McCollum
  • Patent number: 8980699
    Abstract: Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4F2, and methods for forming the same are provided. The thyristor-based memory cells each include a thyristor having vertically superposed regions of alternating dopant types, and a control gate. The control gate may be electrically coupled with one or more of the thyristors and may be operably coupled to a voltage source. The thyristor-based memory cells may be formed in an array on a conductive strap, which may function as a cathode or a data line. A system may be formed by integrating the semiconductor devices with one or more memory access devices or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: March 17, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Sanh D. Tang
  • Patent number: 8975114
    Abstract: Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 10, 2015
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Dipankar Pramanik, Tony P. Chiang, Tim Minvielle, Takeshi Yamaguchi
  • Patent number: 8969152
    Abstract: A field-effect transistor (FET) and methods for fabricating such. The FET includes a substrate having a crystalline orientation, a source region in the substrate, and a drain region in the substrate. Gate spacers are positioned over the source region and the drain region. The gate spacers include a gate spacer height. A source contact physically and electrically contacts the source region and extends beyond the gate spacer height. A drain contact physically and electrically contacts the drain region and extends beyond the gate spacer height. The source and drain contacts have the same crystalline orientation as the substrate.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Wilfried E. Haensch, Effendi Leobandung, Min Yang
  • Patent number: 8969102
    Abstract: A method of testing a device includes setting a potential of a cap terminal of the device to a first voltage, setting a potential of a self test plate of the device to a testing voltage, and detecting a first displacement of a proof mass of the device when the cap terminal is set to the first voltage and the self test plate is set to the testing voltage. The method includes setting a potential of the cap terminal of the device to a second voltage, detecting a second displacement of the proof mass of the device when the cap terminal is set to the second voltage and the self test plate is set to the testing voltage, and comparing the first displacement and the second displacement to evaluate an electrical connection between the cap terminal and a cap of the device.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: March 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Peter S. Schultz
  • Patent number: 8963201
    Abstract: One embodiment of the present invention relates to a silicon-controlled-rectifier (SCR). The SCR includes a longitudinal silicon fin extending between an anode and a cathode and including a junction region there between. One or more first transverse fins traverses the longitudinal fin at one or more respective tapping points positioned between the anode and the junction region. Other devices and methods are also disclosed.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: February 24, 2015
    Assignee: Intel Mobile Communications GmbH
    Inventors: Mayank Shrivastava, Christian Russ, Harald Gossner
  • Publication number: 20150048415
    Abstract: A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate, a first doping region, a first well, a resistor element, and a first, a second, and a third heavily doping regions. The first well and the third heavily doping region are disposed in the first doping region, which is disposed on the substrate. The first heavily doping region and the second heavily doping region, which are separated from each other, are disposed in the first well. The second and the third heavily doping regions are electrically connected via the resistor element. Each of the substrate, the first well, and the second heavily doping region has a first type doping. Each of the first doping region, the first heavily doping region, and the third heavily doping region has a second type doping, complementary to the first type doping.
    Type: Application
    Filed: August 19, 2013
    Publication date: February 19, 2015
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Ling Hung, Hsin-Liang Chen, Wing-Chor Chan
  • Patent number: 8956924
    Abstract: A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: February 17, 2015
    Assignee: Infineon Technologies AG
    Inventors: Krzysztof Domanski, Cornelius C. Russ, Kai Esmark
  • Patent number: 8956948
    Abstract: A semiconductor device is formed with extended STI regions. Embodiments include implanting oxygen under STI trenches prior to filling the trenches with oxide and subsequently annealing. An embodiment includes forming a recess in a silicon substrate, implanting oxygen into the silicon substrate below the recess, filling the recess with an oxide, and annealing the oxygen implanted silicon. The annealed oxygen implanted silicon extends the STI region, thereby reducing leakage current between N+ diffusions and N-well and between P+ diffusions and P-well, without causing STI fill holes and other defects.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: February 17, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yanxiang Liu, Bin Yang
  • Patent number: 8952456
    Abstract: A representative electrostatic discharge (ESD) protection circuit includes a silicon-controlled rectifier comprising an alternating arrangement of a first P-type semiconductor material, a first N-type semiconductor material, a second P-type semiconductor material and a second N-type semiconductor material electrically coupled between an anode and a cathode. The anode is electrically coupled to the first P-type semiconductor material and the cathode is electrically coupled to the second N-type semiconductor material. The ESD protection circuit further includes an inductor electrically coupled between the anode and the second P-type semiconductor material or between the cathode and the first N-type semiconductor material.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Do Ker, Chun-Yu Lin
  • Patent number: 8952418
    Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: February 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Rajesh N. Gupta, Farid Nemati, Scott T. Robins
  • Patent number: 8940588
    Abstract: Aspects of the disclosure provide a dual electrostatic discharge (ESD) protection device in fin field effect transistor (FinFET) process technology and methods of forming the same. In one embodiment, the dual ESD protection device includes: a bulk silicon substrate; a shallow trench isolation (STI) region formed over the bulk silicon substrate; a first ESD device positioned above the STI region; and a second ESD device positioned below the STI region, wherein the first ESD device conducts current above the STI region and the second ESD device conducts current below the STI region.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher Stephen Putnam
  • Publication number: 20150022921
    Abstract: A semiconductor structure for enhanced ESD protection is disclosed. The semiconductor structure includes a plurality of fingers, wherein each finger of the plurality of fingers includes a plurality of voltage clamps, and each voltage clamp of the plurality of voltage clamps includes at least a first well having a first conductivity type and a second well having a second conductivity type, and a connection between a well tie of the first well of a first voltage clamp of the plurality of voltage clamps and a well tie of the first well of a second voltage clamp of the plurality of voltage clamps, wherein the connection is enabled to couple a bias voltage associated with a current flow in the first voltage clamp to the second voltage clamp, and the first voltage clamp and the second voltage clamp are thereby enabled to trigger on substantially simultaneously.
    Type: Application
    Filed: October 3, 2013
    Publication date: January 22, 2015
    Applicant: INTERSIL AMERICAS LLC
    Inventor: James Edwin Vinson
  • Patent number: 8928030
    Abstract: An A-NPC circuit is configured so that the intermediate potential of two connected IGBTs is clamped by a bidirectional switch including two RB-IGBTs. Control is applied to the turn-on di/dt of the IGBTs during the reverse recovery of the RB-IGBTs. The carrier life time of an n? drift region in each RB-IGBT constituting the bidirectional switch is comparatively longer than that in a typical NPT structure device. A low life time region is also provided in the interface between the n? drift region and a p collector region, and extends between the n? drift region and the p collector region. Thus, it is possible to provide a low-loss semiconductor device, a method for manufacturing the semiconductor device and a method for controlling the semiconductor device, in which the reverse recovery loss is reduced while the reverse recovery current peak and the jump voltage peak during reverse recovery are suppressed.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: January 6, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Hong-fei Lu
  • Patent number: 8927347
    Abstract: A semiconductor device includes: an n?-type base layer; a p-type base layer formed in a part of a front surface portion of the n?-type base layer; an n+-type source layer formed in a part of a front surface portion of the p-type base layer; a gate insulating film formed on the front surface of the p-type base layer between the n+-type source layer and the n?-type base layer; a gate electrode that faces the p-type base layer through the gate insulating film; a p-type column layer formed continuously from the p-type base layer in the n?-type base layer; a p+-type collector layer formed in a part of a rear surface portion of the n?-type base layer; a source electrode electrically connected to the n+-type source layer; and a drain electrode electrically connected to the n?-type base layer and to the p+-type collector layer.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: January 6, 2015
    Assignee: Rohm Co., Ltd.
    Inventors: Toshio Nakajima, Syoji Higashida
  • Patent number: 8923666
    Abstract: Embodiments of the present invention provide an electrically controlled optical fuse. The optical fuse is activated electronically instead of by the light source itself. An applied voltage causes the fuse temperature to rise, which induces a transformation of a phase changing material from transparent to opaque. A gettering layer absorbs excess atoms released during the transformation.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Raghavasimhan Sreenivasan
  • Patent number: 8921126
    Abstract: A process for manufacturing a TMR sensor is disclosed wherein the blocking temperature of the AFM layer in the TMR sensor has been raised by inserting a magnetic seed layer between the AFM layer and the bottom shield. This gives the device improved thermal stability, including improved SNR and BER.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: December 30, 2014
    Assignee: Headway Technologies, Inc.
    Inventors: Junjie Quan, Kunliang Zhang, Min Li, Hui-Chuan Wang