Abstract: A memory cell comprises a region containing one or more vertical pass transistor, and a support region containing, e.g. one or more planar transistors. During processing, a polysilicon layer is formed for the planar devices gate. The polysilicon layer is removed from the array region by etching with a first etch mask. A subsequently formed insulating oxide layer is formed and removed from over the polysilicon (i.e. the support region) by etching with a second etch mask. Because the polysilicon layer is left intact only where it is needed, above the region with the planar devices, and the oxide layer is left intact only where it is needed, above the region with the vertical devices, the resulting structure has a substantially planar top surface, allowing for optional subsequent metal depositions and structuring as a wiring level.

Abstract: An IGBT is formed in a thin (less than 250 microns thick) float zone silicon wafer using a hydrogen implant to form an N+ buffer layer at the bottom of the wafer. A weak anode is formed on the bottom of the wafer. A single hydrogen implant, or a plurality of hydrogen implants of progressively shallower depth and increasing dose can be used to form the implant in a diffused float zone wafer. The process may also be used to form an N+ contact region in silicon to permit a good ohmic contact to the silicon for any type device.

Abstract: Test structures for a high voltage MOSFET are provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. A plurality of trenches are located in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches. The test structures allow the simultaneous optimization of the breakdown voltage and on-resistance of the device.

Abstract: Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers (52) in different ways. The trench-gate (11) is accommodated in a narrow trench (20) that is etched via a narrow window (52b) defined by the spacers (52) at sidewalls of a wider window (51a) of a mask (51) at the body surface (10a). The spacers (52) permit a source region (13) adjacent to the trench-gate (11) and an insulating overlayer (18) over the trench-gate (11) to be self-aligned to this narrow trench (20). The overlayer (18), which defines a contact window (18a) for a source electrode (33), is provided in a simple but reproducible manner by deposition and etch-back, after removing the spacers (52). Its overlap (y4, y4′) with the body surface (10a) is well-defined, so reducing a short-circuit risk between the source electrode (33) and the trench-gate (11).

Abstract: N+ or P+ diffusions are formed in a lightly doped P type or N type starting wafer. Individual planar and spaced cells or tubs are then formed by etching an array of intersecting trenches between the P+ (or N+) diffusions. The trenches extend through the thin device layer to a predefined depth and are filled with a dielectric and with polysilicon to dielectrically insulate each of the tubs. At least one diffusion of each cell is connected to a diffusion of an adjacent cell to connect each of a predetermined number of the cells. The N+ or (P+) diffusions may be each enclosed by a ring shaped P+ or N+ contact diffusion. An MOS-gated device may be integrated into the same chip and may be a lateral or vertical MOSFET or a lateral or vertical IGBT.

Abstract: Openings are formed in a laminate of a polycrystalline silicon film and an LTO film on a channel layer. While the laminate is used as a mask, impurities are implanted into a place in the channel layer which is assigned to a source region. Also, impurities are implanted into another place in the channel layer which is assigned to a portion of a second gate region. A portion of the polycrystalline silicon film which extends from the related opening is thermally oxidated. The LTO film and the oxidated portion of the polycrystalline silicon film are removed. While a remaining portion of the polycrystalline silicon film is used as a mask, impurities are implanted into a place in the channel layer which is assigned to the second gate region. Accordingly, the source region and the second gate region are formed on a self-alignment basis which suppresses a variation in channel length.

Abstract: Disclosed is a method for fabricating thin wafer insulated gate bipolar transistors (IGBTs), in which a portion on the back side of the device region is removed to form a hollow region with a depth that results in a device region thickness equivalent to the thickness of a thin wafer while the rest of the wafer remains its standard thickness. In other words, the method according to the present invention is suitable for the currently used wafer transfer stations under thin wafer conditions. The non-punch-through type insulated gate bipolar transistor (NPT-IGBT) fabricated with this method gets rid of an epi-layer and the “lifetime killer” process. The punch-through type insulated gate bipolar transistor (PT-IGBT) fabricated with this method has higher switching efficiency due to reduced injection efficiency of the p+-type minority carriers.

Abstract: A method for manufacturing a semiconductor device constituting an IGBT is provided that allows to manufacture the device using an inexpensive wafer and with high yields, and achieves low losses. Specifically, after an emitter electrode is formed, a reverse principal surface is polished to a specified thickness. The center line average height Ra of the polished surface is controlled to be not more than 1 &mgr;m, and the filtered center line waviness Wca is kept within 10 &mgr;m. The polished surface is selectively cleaned with chemicals-dissolved water to remove particles. To the cleaned surface, phosphorus ions are implanted for forming a field-stop layer and boron ions are implanted for forming a collector layer. The wafer is then put into a diffusion furnace and annealed at a temperature from 300° C. to 550° C. to form a field-stop layer and a collector layer. Finally, a collector electrode is formed.

Abstract: A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inversion region between the source region and drain region. Blocking is achieved by a gate controlled depletion barrier. Located between the source and drain regions is a fairly lightly doped body region. The gate electrode, located in a trench, extends through the source and body regions and in some cases into the upper portion of the drain region. The dopant type of the polysilicon gate electrode is the same type as that of the body region. The body region is a relatively thin and lightly doped epitaxial layer grown upon a highly doped low resistivity substrate of opposite conductivity type. In the blocking state the epitaxial body region is depleted due to applied drain-source voltage, hence a punch-through type condition occurs vertically.

Abstract: A method for a vertical MOS transistor whose vertical channel width can be accurately defined and controlled. Isolation regions are formed in a substrate. The isolation regions defining an active area. Then, we form a source region in the active area. A dielectric layer is formed over the active area and the isolation regions. We form a barrier layer over the dielectric layer. We form an opening in the barrier layer. A gate layer is formed in the opening. We form an insulating layer over the conductive layer and the barrier layer. We form a gate opening through the insulating layer, the gate layer and the dielectric layer to expose the source region. Gate dielectric spacers are formed over the sidewalls of the gate layer. Then, we form a conductive plug filling the gate opening. The insulating layer is removed. We form a drain region in top and side portions of the conductive plug and form doped gate regions in the gate layer. The remaining portions of the conductive plug comprise a channel region.

Abstract: A high voltage radiation hardened power integrated circuit (PIC) with resistance to TID and SEE radiation effects for application in high radiation environments, such as outer space. TID hardness modification include forming gate oxide layers after high temperature junction processes, adding implant layers to raise the parasitic MOSFET thresholds with respect to native thresholds, and suppressing CMOS drain-to-source and intrawell transistor-to-transistor leakage. In addition, radhard field oxide is utilized. SEE ruggedness is improved by reducing the epi thickness over that of non-radhard devices, and increasing the epi concentration near the substrate junction. A radhard PIC rated to 400 V and capable of operating at 600 V or more is provided. The inventive PIC can withstand 100 krads of TID and a heavy ion Linear Energy Transfer of 37 MeV/(mg/cm2) at full rated voltage.

Abstract: A vertical double diffuses MOSFET includes a nitride film (26) formed on a gate electrode (18). An ion implant window (34) is formed through the nitride film. P-type ions are implanted through the ion implant window into the semiconductor substrate (12), and the implanted ions are diffused to thereby form a main diffusion region (14). At the same time, the oxide film is grown inside the ion implant window to form a thick walled portion (36). Ions of the p-type are implanted through, as a mask, the thick walled portion, gate electrode and nitride film into semiconductor substrate, and thermally diffused thus forming a channel diffusion region (22). Further, n-type ions are implanted through the same mask and then thermally diffused to provide source diffusion regions.

Abstract: A method for forming a laterally diffused metal-oxide semiconductor is disclosed. The invention normally is for forming a transistor device, which includes the following steps. Firstly a semiconductor layer is provided. Then a field insulating region is formed into the semiconductor layer. Sequentially forming a gate dielectric layer over a portion of the field insulating region is carried out. Then forming a deep portion of a first drain/source region within the semiconductor layer and spaced from the field insulating region/the top surface. Here, the deep portion is doped with dopants of a conductivity type, with the deep portion having a first doping concentration. The next step is forming a lightly doped portion of the first drain/source region within the semiconductor layer and a neighbouring portion of the field insulating region/the oxide top surface and adjacent the channel region. Generally the lightly doped portion is doped with dopants of the conductivity type.

Abstract: A submicrometer vertical-channel MOSFET of high quality and reproducibility is produced by a method compatible with DPSA technology. The method steps are performed on a wafer of semiconductor material having a layer with n conductivity. First, n impurity ions and p impurity ions are implanted in an area of the layer and the wafer is subjected to a high-temperature treatment. The impurities, the implantation doses and energies, and the high-temperature treatment time and temperature being such as to form a first p region, and a second n region which forms a pn junction with the first region. A trench is hollowed out which intersects the first region and the second regions.

Abstract: The invention relates to a method for producing a semiconductor component including semiconductor areas of different conductivity types which are alternately positioned in a semiconductor body. The semiconductor areas of different conductivity types extend at least from one first zone to a position near a second zone. Because of variable doping in trenches and in the trench fillings, an electric field is generated which increases from both the first zone and the second zone.

Abstract: A power rectifier having low on resistance, mass recovery times and low forward voltage drop. In a preferred embodiment, the present invention provides a power rectifier device employing a vertical device structure, i.e., with current flow between the major surfaces of the discrete device. The device employs a large number of parallel connected cells, each comprising a MOSFET structure with a gate to drain short via a common metallization. This provides a low Vf path through the channel regions of the MOSFET cells to the source region on the other side of the integrated circuit. A thin gate structure is formed annularly around the pedestal regions on the upper surface of the device and a precisely controlled body implant defines the channel region and allows controllable device characteristics, including gate threshold voltage and Vf. A parallel Schottky diode is also provided which increases the switching speed of the MOSFET cells.

Abstract: A semiconductor body (1) is provided having a first semiconductor region (3) of one conductivity type separated from a first major surface (5a) by a second semiconductor region (5) of the opposite conductivity type. A trench (7) is etched through the second semiconductor region (5) to an etch stop layer (4) provided in the region of the pn junction between the first (3) and second (5) regions, by using an etching process which enables the etching process to be stopped at the etch stop layer. A gate (8, 9) is provided within the trench (7). A source (12) separated from the first region (3) by the second region (5) is formed adjacent the trench so that a conduction channel area (50) of the second region (5) adjacent the trench provides a conduction path between the source and first regions which is controllable by the gate.

Abstract: To markedly reduce wafer warping of semiconductor wafers without weakening the strength of adhesion to substrate materials, a novel back side metallizing system is presented. On a silicon semiconductor body an aluminum layer and a diffusion barrier layer that includes titanium are provided. A titanium nitride layer is incorporated into the titanium layer because it has been demonstrated that the titanium nitride layer can compensate for a large proportion of the wafer warping that occurs. Preferably, the usual tempering for improving the ohmic contact between the aluminum layer and the silicon semiconductor body is not performed after the complete metallizing of the semiconductor body, but rather after a first, thin aluminum layer has been deposited onto the silicon semiconductor body.

Abstract: A semiconductor device and method for manufacturing the same includes a plurality of memory cells, each cell having a transistor formed on a first semiconductor substrate and comprising first and second impurity regions and a gate electrode, and a capacitor comprising a first electrode connected with the first impurity region of the transistor and a second electrode formed on the first electrode with a dielectric film disposed therebetween, wherein a channel region formed between the first impurity region and the second impurity region of the transistor is vertically located on the capacitor, and a contact hole connecting the second impurity region of the transistor with the bit-line is vertically located on the channel region, thus achieving the cell area required for one-giga-bit memory devices and beyond and enabling increased capacitance.

Abstract: A method for attaching an integrated circuit die to a mounting structure, the method having the steps of: forming a mounting structure having a die pad and at least one spreader; applying an adhesive to the die pad and the at least one spreader of the mounting structure; and attaching the integrated circuit die to the adhesive, wherein the at least one spreader is between the die pad and the integrated circuit die. Also, an integrated circuit package having: a mounting structure having a die pad and at least one spreader; an adhesive adhered to the die pad and the at least one spreader of the mounting structure; and an integrated circuit die adhered to the adhesive, wherein the at least one spreader is between the die pad and the integrated circuit die. Finally, a mounting structure for an integrated circuit die, the mounting structure comprising: a die pad for supporting the integrated circuit die; and at least one spreader for supporting the integrated circuit die at a distance from the die pad.

Abstract: Power semiconductor devices having recessed gate electrodes are formed by methods which include the steps of forming a semiconductor substrate having a drift region of first conductivity type therein extending to a face thereof and forming a trench in the substrate so that the trench has a bottom which extends opposite the drift region and a sidewall which extends from the drift region to the face. The sidewall may extend orthogonal to the face or at an angle greater than 90°. A preferred insulated gate electrode is formed by lining the face and trench with a gate electrode insulating layer and then forming a conductive layer on the gate electrode insulating layer. The conductive layer is preferably formed to extend opposite a portion of the face adjacent to the trench and into the trench. A step is then performed to pattern the conductive layer to define a T-shaped or Y-shaped gate electrode which fills the trench and also extends opposite the face at a location adjacent the trench.

Abstract: Area efficient static memory cells and arrays containing p-n-p-n transistors which can be latched in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.

Abstract: A process for forming a groove in a semiconductor substrate, to be used to fabricate grooved gate, MOSFET devices, has been developed. The process features the use of an insulator mask, used as an etch mask for definition of the groove feature in the semiconductor substrate. A selective, anisotropic RIE procedure, using an etchant with a specific etch rate ratio of silicon, (semiconductor substrate), to silicon oxide, (insulator mask), is used to establish the desired groove depth, in the semiconductor substrate. The combination of a specific thickness of insulator shape, and a specific etch rate ratio for the selective, anisotropic RIE procedure, allows the desired depth of the groove to be established when the insulator shape is completely removed from the top surface of the semiconductor substrate.

Abstract: A method for fabricating a high voltage MOS device. A substrate has a first P-type well region and a N-type well region formed thereon. A field oxide is then formed on the N-well region and patterned until field oxide projections project from the field oxide layer. With the field oxide projections serving as masks, second P-type well regions are formed in both P-type and N-type lightly doped well regions. A gate oxide layer and a gate polysilicon layer are formed in sequence on a part of the substrate and the field oxide projection, wherein the gate oxide layer and the gate polysilicon layer form a gate electrode. With the gate electrode and the field oxide layer serving masks, a source/drain region is consequently formed in the first P-type well region and the N-type well region.

Abstract: A method of fabricating a self-aligned bipolar junction transistor in a semiconductor structure having a first layer of silicon carbide generally having a first conductivity type and a second layer of silicon carbide generally having a second conductivity type, opposite to the first conductivity type. The method comprises forming a pillar in the second silicon carbide layer, the pillar having a side wall and defining an adjacent horizontal surface on the second layer, forming a dielectric layer having a predetermined thickness on the second semiconductor layer, including the side wall and the horizontal surface. After formation of the dielectric layer, the dielectric layer on a portion of the horizontal surface adjacent the side wall is anisotropically etched while at least a portion of the dielectric layer remains on the side wall, thereby exposing a portion of the horizontal surface.

Abstract: A semiconductor power device comprising an insulated gate bipolar transistor, of the type which comprises a semiconductor substrate with a first type of conductivity and an overlying epitaxial layer with a second type of conductivity, opposite from the first, and whose junction to the substrate forms the base/emitter junction of the bipolar transistor, has the junction formed by a layer of semiconductor material with conductivity of the second type but a higher concentration of dopant than that of the epitaxial layer. Furthermore, the device has the epitaxial layer with conductivity of the second type provided with at least two zones at different dopant concentrations, namely a first lower zone being part of the junction and having a higher dopant concentration, and a second upper zone having a lower concentration.

Abstract: A method for forming a concave bottom oxide layer in a trench, comprising: providing a semiconductor substrate; forming a pad oxide layer on the semiconductor substrate; forming a silicon nitride layer on the pad oxide layer; etching the silicon nitride layer, the pad oxide layer and the semiconductor substrate to form the trench in the semiconductor substrate; depositing a silicon oxide layer to refill into the trench and cover on the silicon nitride layer, wherein the silicon oxide layer has overhang portions at corners of the trench; anisotropically etching the silicon oxide layer to form a concave bottom oxide layer in the trench; etching the silicon oxide layer to remove the silicon oxide layer on the silicon nitride layer and the sidewalls of the trench; removing the silicon nitride layer and the pad oxide layer.

Abstract: A method is described of manufacturing a semiconductor material having a zone (200) with p-conductivity type and n-conductivity type regions with dopant concentrations and dimensions such that, when the n- and p-conductivity type regions are depleted of free charge carriers the space charge per unit area of the regions balances at least to the extent that the resulting electric field is lower than that at which avalanche breakdown would occur in the area. The method starts with a semiconductor body having adjacent a first major surface (10b) a first semiconductor region (2) of one conductivity type. A mask (3, 4, 5) is provided on the first major surface, having at least one mask area masking a part (2a) of the first region. At least a part of the unmasked first region (2) is then removed to provide at least one opening (7) in the first region.

Abstract: A suppression method is applied to an integrated circuit formed on a substrate of p-type material having at least one region of n-type material with junction isolation, a first electrical contact on the frontal surface of the substrate, a second electrical contact on the n-type region and a third electrical contact on the back of the substrate connected to a reference (ground) terminal of the integrated circuit. To avoid current in the substrate due to the conduction of parasitic bipolar transistors in certain operating conditions of the integrated circuit, the method provides for monitoring the potential of the second contact to detect if this potential departs from the (ground) potential of the reference terminal by an amount greater than a predetermined threshold value. If this occurs the first contact is taken to the potential of the second contact, otherwise they are held at the (ground) potential of the reference terminal. A device and an integrated circuit which utilize the method are also described.

Abstract: The collector (anode) of a non punch through IGBT formed in a float zone silicon monocrystaline wafer is formed with a DMOS top structure and is thereafter ground at its bottom surface to a less than 250 micron thickness. A shallow P type implant is then made in the bottom surface and the wafer is then heated in vacuum to about 400° C. for about 30 to 60 seconds to remove moisture and other contaminants from the bottom surface. An aluminum layer is then sputtered on the bottom surface, followed by other metals to form the bottom electrode. No activation anneal is necessary to activate the weak collector junction.

Abstract: In a semiconductor device with a high breakdown voltage, insulating layers are buried at regions in n− silicon substrate located between gate trenches which are arranged with a predetermined pitch. This structure increases a carrier density at a portion near an emitter, and improves characteristic of an IGBT of a gate trench type having a high breakdown voltage.

Abstract: An interface is provided, the interface having at least two form factors—one for interfacing to a connector on a fiber channel drive and one or more other form factors for interfacing to one or more other styles of connectors. The first form factor is on a first part of the printed circuit board and the others are on a second part of the printed circuit board. Further, the first part of the printed circuit board is on one side of the printed circuit board and the other part of the printed circuit board is on an opposite side. Further, one or more non-SCA connectors are mounted on a front side of a substrate for receiving one or more non-SCA style connectors and an SCA2 receptacle is mounted on the back side of the substrate for interfacing the non-SCA connector an SCA connector on a fiber channel cable. Further, the non-SCA2 connector can include a DB9 receptacle, a high speed serial data connector (HSSDC), or RJ-45. Further, the fiber channel drive can receive a media interface adapter (MIA).

Abstract: A process for forming a vertical semiconductor device having increased source contact area comprises forming a gate and a well region in a silicon substrate. Using dopant of a second conductivity type, a shallow source region is formed in the well region, and a first oxide layer is deposited over the gate and the source and well regions. The first oxide layer of oxide is etched to form a first oxide on the substrate adjacent the gate, a thin nitride layer is deposited over the gate and source regions, and a second oxide layer is deposited over the nitride layer and etched to form a second oxide spacer separated from the first oxide spacer and substrate by the nitride layer. These spacers are used as a mask to selectively remove the thin nitride layer from the gate and substrate and portions of the gate polysilicon and source region and thereby form in the source region a recessed portion comprising vertical and horizontal surfaces.

Abstract: A power MOSFET suitable for use in RF applications and a method for making the same is disclosed. The power MOSFET has an increased distance between gate and drain regions of the device in order to decrease the device gate to drain capacitance Cgd. The distance between the gate and drain regions is increased by selective doping of a polysilicon layer of the gate to produce at least two polysilicon gate regions separated by a region of undoped polysilicon that is positioned over a substantial portion of the drain region that resides between the channel portions of the body region of the device. The addition of a contact oxide layer formed directly above the region of undoped polysilicon further increases the distance between gate and drain. Finally, a metal layer is deposited over the entire structure to form the gate and source electrodes of the device.

Abstract: A method of manufacturing a semiconductor component includes providing a semiconductor substrate (200) having top and bottom surfaces, forming a drain electrode (160) at the bottom surface of the semiconductor substrate (200), and simultaneously forming source and gate electrodes (251, 254, 255, 253) at the first surface of the semiconductor substrate (200).

Abstract: A process for fabricating a vertical MOSFET device for use in integrated circuits is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET. In the process the first and third layers have etch rates that are significantly lower than the etch rate of the second layer in an etchant selected to remove the second layer. The top layer, which is either the third or subsequent layer, is a stop layer for a subsequently performed mechanical polishing step that is used to remove materials formed over the at least three layers. After the at least three layers of material are formed on the substrate, a window or trench is formed in the layers.

Abstract: A high voltage transistor or thyristor having a base layer which is a thinned neutron transmuted wafer 102, 152 instead of a diffused or epitaxially grown base layer. The neutron transmuted wafer has high resistivity and a desired thickness while the layer formed overlying the surface of the neutron transmuted wafer has a desired thickness and doping level. Adjusting the thicknesses and doping levels within these two structures produce a device having the desire high voltage characteristics. The various embodiments provides for a high voltage MOSFET 100, IGBT 170, and thyristor.

Abstract: A method for increasing the operating voltage of a transistor formed on a substrate of a first conductivity region of a second conductivity type in a surface of the substrate. An N-well adjust region of the first conductivity type is then formed in the N-well region. The N-well adjust region extends to a first depth in the N-well region. A double diffusion well of the first conductivity type is then formed in the N-well. The double diffusion well extends to a second depth greater than the first depth of the N-well adjust region, and contains a portion of the N-well. Two N- channel stop regions are then formed in the N-well. The two N-channel stop regions extending to a third depth greater than the depth of the N-well adjust region, and contain a portion of the N-well.

Abstract: A DMOS device in a complex integrated circuit having a well region defined by a buried isolation region and an overlapping deep drain region within an epitaxial layer formed over a substrate, a body region having two source regions within the well region, insulated gates over the two source regions, and a Schottky contact over a central portion of the well region and spaced from the body region. The Schottky contact defines a Schottky diode within the epitaxial layer for diverting current from the substrate in the event of a below ground effect or an oversupply effect. The invention reduces or eliminates altogether the effects of parasitic transistors in the complex integrated circuit.

Abstract: A method of fabricating a MOS controlled thyristor (MCT) semiconductor power device which reduces process time, reduces cell size, and increases the density of turn-off channels. The method uses a single, dopant-opaque mask to form MCT structure above the bottom N and P layers, including the upper portions of PNP and NPN transistors which form the MCT and On-FETs and Off-FETs which operate the MCT. The single mask may also be used to fabricate floating field rings for the device. The method may also be used on both sides of the device to provide a Fast Turn Off (FTO) device with both On- and Off-FETs on one side and at least an Off-FET on the other side.

Abstract: A method of manufacturing high-voltage MOS devices that uses trenches instead of field oxide layer as the isolating structure, and employs a vertical layout rather than a horizontal layout to lengthen the drift region for a given device area in a wafer. Therefore, this invention is capable of fabricating CMOS transistors in the sub-micron regime, and hence is able to increase the level of circuit integration for a given wafer. Furthermore, the present invention provides a method of manufacturing an assembly with different types of high-voltage MOS devices. By making minor adjustments in the height of the N.sup.- regions underneath the source/drain (N.sup.+) regions of different devices, an assembly of MOS devices each having a different voltage operating range can be obtained on an integrated circuit. Moreover, the minor adjustments can be achieved simply by etching the N.sup.- regions to different degrees.

Abstract: Silicon carbide power devices are fabricated by implanting p-type dopants into a silicon carbide substrate through an opening in a mask, to form a deep p-type implant. N-type dopants are implanted into the silicon carbide substrates through the same opening in the mask, to form a shallow n-type implant relative to the p-type implant. Annealing is then performed at temperature and time that is sufficient to laterally diffuse the deep p-type implant to the surface of the silicon carbide substrate surrounding the shallow n-type implant, without vertically diffusing the p-type implant to the surface of the silicon carbide substrate through the shallow n-type implant. Accordingly, self-aligned shallow and deep implants may be performed by ion implantation, and a well-controlled channel may be formed by the annealing that promotes significant diffusion of the p-type dopant having high diffusivity, while the n-type dopant having low diffusivity remains relatively fixed.

Abstract: A manufacturing method of a vertical type MOSFET, which can suppress vaporization of impurity from a semiconductor substrate and prevent variation in carrier density of the channel, is disclosed. The vertical type MOSFET is formed by forming a local oxide film to form a concavity on the element surface, removing the local oxide film by wet-etching technique, forming the gate oxide film at the sidewall of the concavity by thermal oxidation, and forming a gate electrode. Further, a polycrystalline silicon is formed on a back surface of the semiconductor substrate before removing the local oxide film. Accordingly, since the polycrystalline silicon is not removed when removing the local oxide film, vaporization of impurity from the semiconductor substrate is suppressed during the thermal oxidation for forming the gate oxide film, thereby preventing change in the carrier density of the channel.

Abstract: A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inversion region between the source region and drain region. Blocking is achieved by a gate controlled depletion barrier. Located between the source and drain regions is a fairly lightly doped body region. The gate electrode, located in a trench, extends through the source and body regions and in some cases into the upper portion of the drain region. The dopant type of the polysilicon gate electrode is the same type as that of the body region. The body region is a relatively thin and lightly doped epitaxial layer grown upon a highly doped low resistivity substrate of opposite conductivity type. In the blocking state the epitaxial body region is depleted due to applied drain-source voltage, hence a punch-through type condition occurs vertically.

Abstract: An n.sup.- layer (2E) having a low impurity concentration is epitaxially grown on a surface (S1) of an n.sup.+ silicon substrate (1) having a high impurity concentration to a depth (D), and phosphorus ions (P) are implanted from the surface (S1) to the inside of the n.sup.- layer (2E). A SiO.sub.2 film is formed on the surface S1 by thermal oxidation, and an opening hole is formed in the SiO.sub.2 film. Using the opening hole, p-type impurities are implanted and diffused by thermal oxidation in the ion-implanted n.sup.- layer (2E), forming a p-type diffusion layer (well) from the surface (S1) to a predetermined depth. In this way, an n layer is formed in place of the n.sup.- layer (2E). The concentration distribution of impurity in the n layer monotonically decreases from the side of the surface (S1) and reaches its minimum on the side of an interface (BS). Then, a predetermined electrode is formed, completing the device.

Abstract: A method of manufacturing a silicon carbide vertical MOSFET is presented which includes: providing a first conductivity type silicon carbide substrate; a first conductivity type drift layer comprising silicon carbide which is formed on the first conductivity type silicon carbide substrate; a second conductivity type base region formed in a selected region of a surface layer of the first conductivity type drift layer; a first conductivity type source region formed in a selected region of the second conductivity type base region; a gate electrode layer formed on a gate insulating film over at least a part of an exposed surface portion of the second conductivity type base region interposed between the first conductivity type source region and the first conductivity type drift layer; a source electrode formed in contact with surfaces of the first conductivity type source region and the second conductivity type base region; and a drain electrode formed on a rear surface of the silicon carbide substrate.

Abstract: A method of forming a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device on a semiconductor substrate with reduced masking steps is disclosed. In the first method, the reduced masking steps are arranged in an optimal sequence in which the gate layer is patterned first as a self-aligned mask. The gate layer includes a plurality of gate segments separated by spacings. An active mask for defining active body regions is then patterned in the spacings of the gate layer to form a combination mask. Using the combination mask as a shield, body and source regions are ion-implanted into the substrate. During the formation of the active mask, remnant material of the active mask adheres to the boundaries of the gate segments to form a spacer layer which is utilized to alleviate the cell-to-cell encroachment problem due to the side diffusion effect of the body and source regions.

Abstract: The on-resistance of a vertical power transistor is substantially reduced by forming a thick metal layer on top of the relatively thin metal layer that is conventionally used to make contact with the individual transistor cells in the device. The thick metal layer is preferably plated electrolessly on the thin metal layer through an opening that is formed in the passivation layer.

Abstract: An MOS-gated power semiconductor device is formed by a process in which a self-aligned device cell is formed without any critical alignments. A sidewall spacer is used to mask the etching of a depression in the silicon to reduce the number of critical alignment steps. An optional selectively formed metal connects the polysilicon layer to the P+ and N+ diffusion regions. The sidewall spacer, in combination with the selectively formed metal, prevents impurities from diffusing to the parasitic DMOS channels and inverting them to cause leakage. A termination structure may also be formed by this process.

Abstract: A process for fabricating a vertical MOSFET device for use in integrated circuits is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET. In the process the first and third layers have etch rates that are significantly lower than the etch rate of the second layer in an etchant selected to remove the second layer.After the at least three layers of material are formed on the substrate, a window or trench is formed in the layers. The window terminates at the surface of the silicon substrate in which one of either a source or drain region is formed in the silicon substrate. The window or trench is then filled with a semiconductor material.