Abstract: A hydrogen gas sensor and/or switch fabricated from arrays nanowires composed of metal or metal alloys that have stable metal hydride phases. The sensor and/or switch response times make it quite suitable for measuring the concentration of hydrogen in a flowing gas stream. The sensor and/or switch preferably operates by measuring the resistance of several metal nanowires arrayed in parallel in the presence of hydrogen gas. The nanowires preferably comprise gaps or break junctions that can function as a switch that closes in the presence of hydrogen gas.

Abstract: A solid picture element that transfers charges completely from a photodiode portion to an amplifying transistor portion to substantially eliminate residual images and methods of its manufacture are disclosed. The solid picture element includes a buried photodiode and a transistor in communication with a transfer gate that is a selective transfer path for charges from the photodiode to the transistor. The charge accumulation region is located so that it is not in contact with the upper surface of the semiconductor substrate and so that a margin of the charge accumulation region is located 0.0 to 0.2 ?m closer to the transistor than any portion of the depletion prevention region. Methods of manufacture of the picture element of the present invention include using the transfer gate as a mask and implanting ions into a semiconductor substrate at a first angle to form the charge accumulation region and at a second, steeper, angle to form the depletion prevention region.

Abstract: A technique for forming Charge-Coupled Devices (CCDs) in a conventional Complementary Metal Oxide Semiconductor (CMOS) process. A number of single-layer polysilicon gates are formed on an as-grown, native doped silicon substrate, with gaps between them. Masking is used to selectively dope the gates while preventing doping of the silicon in the gaps. Masking may likewise be used to selectively silicide the gates while preventing silicide formation in the gaps. Conventional source-drain processing produces input/output diffusions for the CCD.

Abstract: A method of forming a fin field effect transistor on a semiconductor substrate includes forming an active region in the substrate, forming an epitaxial layer on the active region, and removing a portion of the epitaxial layer to form a vertical fin on the active region. The fin has a width that is narrower than a width of the active region. Removing a portion of the epitaxial layer may include oxidizing a surface of the epitaxial layer and then removing the oxidized surface of the epitaxial layer to decrease the width of the fin. The epitaxial layer may be doped in situ before removing a portion of the epitaxial layer. The method further includes forming a conductive layer on a top surface and on sidewalls of the fin. Related transistors are also discussed.

Abstract: An adjustable charge coupled device (CCD) charge splitter includes a channel control structure and an associated plurality of output channels. Control signals applied to the channel control structure determine an amount of charge, which passes into each one of the plurality of output channels.

Abstract: A charge coupled device of the present invention includes a charge transfer region layer and a gate insulation film that are formed in the stated order on a semiconductor substrate, first gate electrodes formed at predetermined spaces on the gate insulation film, and second gate electrodes arranged between the first gate electrodes with at least silicon oxide films being interposed there between. Each silicon oxide film has constricted portions where the silicon oxide film is in contact with the gate insulation film, and electric insulation films are formed on the constricted portions so as to form sidewalls. This configuration decreases the charge transfer efficiency and increases a dielectric breakdown voltage between gate electrodes. Thus, a charge coupled device having high performance and high dielectric strength is provided.

Abstract: The method for manufacturing a test pattern for use in a CMOS image sensor is employed to measure a sheet resistivity of each ion implantation region, respectively.

Abstract: More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge collecting gate and the gate downstream to the charge collecting gate. To reduce the gaps between gates, an insulator cap with spacers on its sidewalls is formed for each gate over a conductive layer. The gates are then etched from the conductive layer using the insulator caps and spacers as hard masks, enabling the gates to be formed significantly closer together than previously possible, which, in turn increases charge transfer efficiency. By providing a lightly doped region on between adjacent gates, a more complete charge transfer is effected from the charge collecting gate.

Abstract: The method for manufacturing a CMOS image sensor is employed to prevent bridge phenomenon between adjacent microlenses by employing openings between the microlenses. The method includes the steps of: preparing a semiconductor substrate including isolation regions and photodiodes therein obtained by a predetermined process; forming an interlayer dielectric (ILD), metal interconnections and a passivation layer formed on the semiconductor substrate in sequence; forming a color filter array having a plurality of color filters on the passivation layer; forming an over-coating layer (OCL) on the color filter array by using a positive photoresist or a negative photoresist; forming openings in the OCL by patterning the OCL by using a predetermined mask; and forming dome-typed microlenses on a patterned OCL.

Abstract: Methods of coating a semiconductor device with phosphor particles are disclosed. In the methods, a bath is provided which contains suspended particles of a first phosphor material and suspended particles of a second phosphor material. The particles of the first phosphor material have a mean particle size in the range from about 1 micron to about 6 microns, and the particles of the second phosphor material have a mean particle size in the range from about 12 microns to about 25 microns, wherein the particle size distribution of the phosphor material in the bath is bimodal. The semiconductor device is disposed in the bath containing the suspended particles, and a first biasing voltage is applied between an anode in electrical contact with the bath and the p side to hold the anode at a positive voltage with respect to the p side. A second biasing voltage is applied between the p side and the n side.

Abstract: A retrograde well structure for a CMOS imager that improves the quantum efficiency and signal-to-noise ratio of the imager. The retrograde well comprises a doped region with a vertically graded dopant concentration that is lowest at the substrate surface, and highest at the bottom of the well. A single retrograde well may have a single pixel sensor cell, multiple pixel sensor cells, or even an entire array of pixel sensor cells formed therein. The highly concentrated region at the bottom of the retrograde well repels signal carriers from the photosensor so that they are not lost to the substrate, and prevents noise carriers from the substrate from diffusing up into the photosensor. Also disclosed are methods for forming the retrograde well.

Abstract: A frame transfer-type solid imaging device is provided, which can be operated without reducing the transfer efficiency or the transfer charge quantity. A plurality of N-type regions 5 constituting photoelectric conversion regions and a plurality of P+-type regions 6 constituting channel stop regions are formed on a P-type silicon substrate 4, and a transparent electrode 1 is further formed through an insulating film 7 on the substrate 4. The thickness of the transparent electrode at a portion above the photoelectric conversion region is made thinner than the thickness of the other part of the transparent electrode 1, and an antireflection film 8 is formed above the photoelectric conversion region 2.

Abstract: A solid-state imaging device of the present invention includes a vertical charge transfer portion and a horizontal charge transfer portion that is connected to at least one end of the vertical charge transfer portion. The vertical charge transfer portion includes a vertical transfer channel region and a plurality of vertical transfer electrodes formed on the vertical transfer channel region. The horizontal charge transfer portion includes a horizontal transfer channel region, a plurality of first horizontal transfer electrodes formed on the horizontal transfer channel region, and a plurality of second horizontal transfer electrodes arranged between the plurality of first horizontal transfer electrodes. A potential below the first horizontal transfer electrode is higher than a potential below the second horizontal transfer electrode that is arranged adjacent to the first horizontal transfer electrode and backward along a transfer direction with respect to the first horizontal transfer electrode.

Abstract: Large area, fast frame rate, charge coupled devices (CCDs) are provided. Interline transfer CCDs can have interleaved pinned photodiodes and vertical shift registers. The interline transfer CCDs are ideal for producing high frame rate video images from a continuous light source. The photodiodes transfer charge indicative of the previous video frame to an adjacent vertical shift register with little or no lag, while light from the current video frame is integrating in the photodiodes. The charge signals only have to travel a short distance from a photodiode to an adjacent vertical shift register. The charge signals indicative of each video frame are then shifted out of the vertical shift registers. Each vertical shift register has a doping gradient that increases the charge transfer rate. All of these factors provide a fast and efficient video frame rate, even in a large area CCD.

Abstract: A solid-state imaging device includes: a base made of an insulation material and having a frame form in planar shape with an aperture formed at an inner region; a plurality of wirings provided on one surface of the base and extending toward an outer periphery of the base from a region along the aperture; and an imaging element mounted on the surface of the base with wirings provided thereon so that a light-receptive region of the imaging element faces the aperture. An end portion on the aperture side of each of the plurality of wirings forms an internal terminal portion and an end portion on the outer peripheral side of each of the plurality of wirings forms an external terminal portion, the internal terminal portion of the wiring being connected electrically with an electrode of the imaging element.

Abstract: There is provided a laminated type photoelectric converter whose sensitivity is enhanced uniformly. In the photoelectric converter in which a photoelectric conversion device is laminated above a signal transfer device, the sensitivity is enhanced by providing bends on a lower electrode of the photoelectric conversion device and by confining light uniformly.

Abstract: In a solid state image sensor, tranfer electrodes are formed by selectively etch-removing a single layer of conducting electrode material at a plurality of first regions which divide the single layer of conducting electrode material in a row direction for each one pixel. A patterned mask is formed to cover the first regions and the single layer of conducting electrode material but to expose the single layer of conducting electrode material at a second region above each of the photoelectric conversion sections, and the single layer of conducting electrode material is selectively etch-removed using the patterned mask as a mask. Thereafter, a first conductivity type impurity and a second conductivity type impurity are ion-implanted using the patterned mask and the single layer of conducting electrode material as a mask, to form the photoelectric conversion section at the second region.

Abstract: A method of manufacturing a charge-coupled device, the method includes the steps of providing a substrate; covering the substrate with a single gate dielectric or a gate dielectric stack; covering the dielectric with a conducting material; depositing a second dielectric on the conducting material; etching the second dielectric and the conducting material in selected regions; depositing a third dielectric on the both the etched away and non-etched away regions; etching the third dielectric such that a portion of the third dielectric remains on a sidewall of the etched away portions which forms a gap region; and depositing a second conducting material in the gap region.

Abstract: A method for forming edge-defined structures with sub-lithographic dimensions which are used to further form conduction channels and/or storage structures in memory cells. Sacrificial silicon nitride islands are deposited at low temperatures and then patterned and etched by high resolution etching techniques. Polysilicon is next deposited over the sacrificial silicon nitride islands and directionally etched to form edge-defined polysilicon dot and strip structures which are about one tenth the minimum feature size. The edge-defined polysilicon strips and dots are formed between the source and drain region of an NMOS device. Subsequent to the removal of the sacrificial silicon nitride islands, the edge-defined polysilicon strips and dots are used to mask a threshold voltage implantation in a conventional CMOS process. A conduction channel and two adjacent potential minimum dots are formed after the removal of the edge-defined polysilicon strips and dots.

Abstract: Generally, and in one form of the invention, a monolithic solid state image-sensing device is disclosed. The device utilizes only a single layer of polysilicon deposition in its fabrication process that is split into two or more phases by very narrow gaps. The single polysilicon layer makes the fabrication process simpler and more compatible with modern semiconductor manufacturing technology. The device also incorporates a lateral anti-blooming drain structure that is formed by a self-aligned diffusion process and does not need a polysilicon gate for its proper function.

Abstract: A solid state image sensor that prevents a reduction of transfer efficiency even if pixel size is reduced. A first semiconductor region is formed on a semiconductor substrate and a second semiconductor region is formed on the first semiconductor region. A plurality of parallel isolation regions are arranged in the second semiconductor region at predetermined intervals. Depth of the isolation regions is less than the thickness of the second semiconductor region such that the potential of transfer regions in the second semiconductor region is affected by a potential barrier formed in first semiconductor region rather than a potential barrier formed around the isolation regions when the intervals between the isolation regions are relatively narrow.

Abstract: Methods of fabricating an image sensor equipped with a lens are disclosed. The disclosed methods can attach a lens directly onto a device without fabricating a separate lens module in a fabrication process of an image sensor device by forming a concave groove on the bottom surface of the lens and coupling the device and the lens by alignment marks after forming a metal convex portion around a pixel array and forming a lens from a mobile material in the final step of device fabrication prior to performing a packaging process.

Abstract: The present invention discloses an array substrate (and method for making the same) for use in a liquid crystal display device, including: gate lines arranged in a transverse direction and organized as odd and even gate lines; data lines arranged in a longitudinal direction perpendicular to the gate lines, and organized as odd and even data lines; gate shorting bars organized as odd and even gate shorting bars, the odd gate shorting bar electrically connecting all of the odd gate lines, the even gate shorting bar electrically connecting all of the even gate lines; data shorting bars organized as odd and even data shorting bars, the odd data shorting bar electrically connecting all of the odd data lines, the even data shorting bar electrically connecting all of the even data lines; and a first active line electrically connecting all of the data lines.

Abstract: A process for forming a portion of a charge coupled device (CCD) is described. More particularly, wells (105) are formed self-aligned under gate stacks (132, 134). By forming wells (105) self-aligned to respective first and second gates (107, 207) of gate stacks (132, 134), potential for misalignment is reduced. First gates (107) of gate stacks (132) may be coupled together, and second gates (207) of gate stacks (134) may be coupled together, and these first and second gates (107, 207) may be coupled to respective signal sources (23, 24) to form a two-phase CCD.

Abstract: A charge storing layer of a photodiode having an N-type conductivity includes an N+-type additional implant area in the vicinity of a junction between the charge storing layer and an isolation region. The additional implant area provides an increase of stored charge and suppression of increase of the pulse voltage for a substrate shutter, and can be made to have a smaller width within a current design rule.

Abstract: A display device comprising a multi-color light emitting layer and method of depositing the multi-color light emitting layer over a glass substrate are provided. The display device comprises multiple light emitting materials deposited over a glass substrate in coplanar relationship to each other. The method provides depositing one light emitting polymer material over one portion of the glass substrate and depositing other light emitting polymer materials over other portions of the glass substrate, such that the multiple light emitting polymer materials are deposited in a coplanar relationship to each other. The light emitting polymer materials are deposited using flexographic mats, the relief portion of which have patterns corresponding to the respective portions of the glass substrate being covered by the light emitting polymer materials being deposited.

Abstract: An anti-reflective coating having a composite layer of silicon nitride and silicon dioxide may be formed over the entire photosensitive region of the photodetector to minimize the amount of reflection. The composite layer comprises a silicon nitride layer and a dielectric layer contiguous to the silicon nitride layer. The anti-reflective coating may be formed in a CMOS process for fabricating the PN junction in the photodiode and CMOS devices for amplifying the photodetector signal, where the polysilicon gate layer is used as a etch stop. The P+ or N+ material in the PN junction of the photodiode has a distributed design where two portions of the region are separated by a distance in the range of Xd to 2Xd, where Xd is the one-sided junction depletion width, to enhance the electric field and to reduce the distance traveled by the carriers for enhancing bandwidth. A heavily doped region of the opposite type may be added between the two portions to further enhance the electric field.

Abstract: In a method of manufacturing a solid-state image pickup device having a virtual gate structure, in a process of forming a profile of a sensor portion, when ion implantation to form a p+ type layer at a substrate surface side is carried out while the ion implantation direction is tilted with respect to the substrate surface, the ion implantation is divisively carried out at plural times and from multiple ion implantation directions so that the total dose amount is matched, whereby impurities can be implanted into any area of the sensor portion and thus no impurities-unformed area occurs.

Abstract: A photodiode for use in an imager having an improved charge leakage. The photodiode has a doped region that is spaced away from the field isolation to minimize charge leakage. A second embodiment of invention provides a second implant to improve charge leakage to the substrate. The photodiodes according to the invention provide improve charge leakage, improved reactions to dark current and an improved signal to noise ratio. Also disclosed are processes for forming the photodiode.

Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon.

Abstract: A method for re-forming a semiconductor layer of a thin film transistor-liquid crystal display device, including the steps of forming a gate electrode on a substrate, and forming a first gate insulation film on the gate electrode and the substrate; forming a semiconductor layer on the first gate insulation film; etching the semiconductor layer to remove the semiconductor layer if the formed semiconductor layer is defective; etching an upper portion of the first gate insulation film to a certain thickness damaged as the interface is exposed to the air by the etching of the semiconductor layer; forming a second gate insulation film on the remaining first gate insulation film; and forming a semiconductor layer on the second gate insulation film.

Abstract: A solid-state imaging device comprises: an electric charge transfer portion for transferring an electric charge produced in a photodetector through photoelectric conversion from incident light to the electric charge; and, an output amplifier portion for detecting the electric charge to issue a signal. The charge transfer portion is provided with a first gate insulation film having a sufficient film thickness to keep a predetermined transfer efficiency. The output amplifier portion is provided with a second gate insulation film having a film thickness suitable for obtaining a predetermined mutual conductance capable of increasing the gain of the output amplifier portion.

Abstract: Object: To provide a solid-state imaging device having contacts for a charge sweeping component or the like, with which increases in dark current can be suppressed while increases in contact resistance and the production of alloy spikes can be prevented, and to provide a method for manufacturing this device.

Abstract: This invention provides a manufacturing process for a charge transfer device comprising an N-type well formed in a P-type well on a semiconductor substrate for transferring a signal charge, an N+ region formed on both sides along the charge transfer direction of the N-type well and containing a dopant in a higher concentration than that in the N-type well, a P-type region formed around the N+ region, and a gate electrode covering the N+ region and the N-type well and formed via a gate insulator, comprising ion-implanting an N-type dopant into the region to be the N-type well and the N+ region using the first mask and ion-implanting a P-type dopant into the region to be the N-type well using the second mask. Thus, there can be provided a charge transfer device which has a structure where there is an N+ region on both sides of the N-type well, a large maximum transferable charge and a compact CCD with a width up to 3 times the minimum design dimension.

Abstract: A method for manufacturing a thin film transistor is disclosed. Afterforming a channel region on a surface of a substrate, an insulating layer is deposited on the surface of the substrate to cover the channel region. The insulating layer is pataterned such that a portion of the channel region is exposed. Then, a silicon layer and a metal layer are sequentially deposited on the insulating layer. The silicon and metal layers are etched to define source, drain and gate electrode sections. After doping positive ions on a portion corresponding to a MOS circuit portion, an intermediate insulating layer is deposited on the metal layer while covering the source, drain and gate electrode sections. The intermediate insulating layer is patterned to form a plurality of contact holes. An electrode material is deposited on the intermediate insulating layer and patterned to define a pixel electrode section and a wire section.

Abstract: It is known in charge coupled devices to use a dual layer of silicon oxide and silicon nitride as the gate dielectric. Since silicon nitride is practically impermeable to hydrogen, the nitride layer is usually provided with openings through which hydrogen can penetrate up to the surface of the silicon body during the annealing step carried out for passivating the surface. The openings in the nitride layer are provided by a known method, with gates in a first poly layer serving as a mask, in that the nitride is removed from between these gates and an oxidation step is subsequently carried out. According to the invention, the openings in the nitride layer are formed by means of a separate mask (20), such that the edges of the openings (9) in the nitride layer (8) lie at some distance from the edges of the gates.

Abstract: A simple, low-cost package consisting of a plurality of charge-coupled devices (CCD) having a transparent cover integrated to the CCDs is described. Interconnecting wires having a fine pitch are defined on the cover away from the light sensitive area of the CCDs to provide enhanced wiring capability. The cover is constructed on the same semiconductor wafer containing the CCDs, which are preferably arranged in a matrix formation, allowing the wafer to be diced into individual chips having any desired number of CCDs, all of which are protected by the integrated transparent cover facing the light sensitive surface of the CCDs. This structure has the further advantage of reducing defects by mounting the cover before dicing and handling the individual chips only after the cover window is already in place. Dicping width control is achieved using oxide trench as an etch channel.

Abstract: This invention relates to a TFT-LCD and a manufacturing method therefor which etches triple layer patterns in a single process step. As a result, the number of masking processes is reduced and a high quality device is produced with less defects.

Abstract: An optical device is enclosed within a package or module having an optically transmissive or transparent cover that is sealed with an adhesive preform that has been pre-applied onto the bonding areas of the cover. The adhesive preforms are formed of a wet adhesive deposited on a sheet of optically transmissive or transparent material as a preform in predetermined locations and are B-staged or dried to form dry solid adhesive preforms. The preforms may be continuous or have one or more small gaps therein. The sheet of optical material is diced or singulated to produce individual optical covers having an adhesive preform thereon.

Abstract: A charge transfer device has a charge transfer region under charge transfer electrodes for stepwise conveying charge packets through potential wells to a floating diffusion region, and the charge transfer region has a boundary sub-region contracting toward the floating diffusion region, wherein the final potential well is created at a certain portion in said boundary sub-region close to the floating diffusion region so that each charge packet travels over a short distance, thereby enhancing a charge transfer efficiency.

Abstract: A method and apparatus of forming adjacent, non-overlapping CCD electrodes within an image sensing device such the electrodes are U-shaped. The device provided by the disclosed method employs a substrate with a gate dielectric layer formed on a surface of the substrate with a plurality of phases created within the CCD. A deposited silicon layer is placed on the surface of the CCD and a mask is used to cover areas other than the first set of electrodes. Etching takes places leaving the mask areas to the deposited silicon and a set of side walls to the remaining deposited silicon are then oxidized. A first set of electrodes by forming an electrode layer placed over the CCD. CMP is employed to remove remaining deposited silicon layer as well as portions of the electrode layer such that the side walls remain vertical portions to electrode layer remaining in the side walls. The process is then repeated by placing another electrode material layer and another CMP process leaving two sets of adjacent U-shaped gates.

Abstract: A semiconductor device having a silicon-on-insulator (SOI) structure includes a field-effect transistor having amorphized source and drain regions formed by implanting silicon or germanium ions into a silicon layer formed over a buried insulator. The fully amorphized source and drain regions ultimately result in permanent crystalline defects that cause p-n junction leakage which allows charge in the body of the device to dissipate, thereby improving the overall efficiency and performance of the device. The source and drain regions are amorphized throughout their entire thickness to prevent single crystal re-crystallization from occurring during annealing and other subsequent processing steps that can degrade the quality of the p-n leakage junctions.

Abstract: In a charge transfer device of the two-layer electrode, two-phase drive type, an N−− semiconductor region 108 and a first insulator film 103 are formed on a P-type semiconductor substrate 101 in the named order. Then, first transfer electrodes 104A are formed on the first insulator film 103, and a second insulator film 105 is formed on the surface of the N−− semiconductor region 108 and a third insulator film 105 is formed on a top surface and a side surface of each first transfer electrode 104A. Phosphorus is ion-implanted with an incident angle of 0 degree, so that an N-type semiconductor region 102A is formed in N−− semiconductor region 108 between the first transfer electrodes 104A in self-alignment. Second transfer electrodes 109A are formed, and an interlayer insulator 110 is formed on the whole, and metal interconnections 111-1A and 111-2A are formed.

Abstract: A method of fabricating a stripe photodiode element, for an image sensor cell, has been developed. The stripe photodiode element is comprised of a narrow width, serpentine shaped, lightly doped N type region, in a P well region. The use of the serpentine shaped region results in increased photon collection area, when compared to counterparts fabricated using non-serpentine shaped patterns. In addition the use of the serpentine shaped N type regions allow both vertical, as well as horizontal depletion regions, to result, thus increasing the quantum efficiency of the photodiode element. The combination of narrow width, and a reduced dopant level, for the N type serpentine shaped region, result in a fully depleted photodiode element.

Abstract: A method of manufacturing a charge-coupled image sensor, wherein a silicon slice (1) is provided at its surface with semiconductor zones (8, 12, 16) formed by implantation of ions of dopants and subsequent heat treatments. The surface (2) is provided with a gate dielectric (3, 4) comprising a layer of silicon oxide (3) and a layer of silicon nitride (4) deposited on said layer of silicon oxide (3). A system of electrodes (17, 20) is formed on the gate dielectric layer (3, 4). In this method, the semiconductor zones (8, 12, 16) are not formed in the silicon slice (1) until after the gate dielectric layer (3, 4) has been formed, the ions being implanted through the gate dielectric layer (3, 4). An image sensor thus formed has a very small dark current, a very low fixed pattern noise, and images formed by means of the sensor are practically free of white spots.

Abstract: This invention provides a manufacturing process for a charge transfer device comprising an N-type well formed in a P-type well on a semiconductor substrate for transferring a signal charge, an N+ region formed on both sides along the charge transfer direction of the N-type well and containing a dopant in a higher concentration than that in the N-type well, a P-type region formed around the N+ region, and a gate electrode covering the N+ region and the N-type well and formed via a gate insulator, comprising ion-implanting an N-type dopant into the region to be the N-type well and the N+ region using the first mask and ion-implanting a P-type dopant into the region to be the N-type well using the second mask. Thus, there can be provided a charge transfer device which has a structure where there is an N+ region on both sides of the N-type well, a large maximum transferable charge and a compact CCD with a width up to 3 times the minimum design dimension.

Abstract: A barrier area is located adjacent a horizontal transfer area and spaced from a field insulating area. The barrier area includes an insulating layer and a conductor extending from the horizontal transfer layer over the surface of a semiconductor substrate, a barrier layer of a second conductivity type formed under the surface of the semiconductor substrate and adjacent a first impurity layer of a first conductivity type of the horizontal transfer area, and a second impurity layer extending from the horizontal transfer area and formed under the barrier layer. A discharge area is located between the barrier area and the field insulating area.

Abstract: A charge coupled device has an n- type charge accumulating layer equal to or less than 5 micron in width, and the unit cells suffer from reduction of signal charge accumulated therein and an increased pulse height of a pulse signal for a substrate shutter, wherein at least one p- type local impurity region is formed in such a manner as to form a p-n junction together with the n- type charge accumulating layer and the n- type semiconductor substrate, thereby increasing the amount of signal charge accumulated in each unit cell without sacrifice of the pulse height of the pulse signal for the substrate shutter.

Abstract: A method and apparatus of making high energy implanted photodiode that is self aligned with the transfer gate, the high energy implant is defined by providing a substrate, or well, of a first conductivity type, defining a charge coupled device within the substrate, or well, such that gate electrode layers are allowed to exist over areas to contain photodiodes during construction of the charge coupled device, patterning a masking layer to block high energy implants such that openings in the masking layer are formed over the areas of the photodiodes, anisotropically etching down through the gate electrode over the photodiodes to the gate dielectric material, implanting photodiodes with high-energy ions of a second conductivity type opposite the first conductivity type and creating a pinned photodiode by employing a shallow implant of the first conductivity type. The apparatus made by this method yields a photodiode employing high energy ions to form the P/N junction that is self aligned with the transfer gate.

Abstract: The method for making a virtual phase charge coupled device with multi-directional charge transfer capabilities includes: forming a semiconductor region 48 of a first conductivity type; forming first gate regions 32 and 36 overlying and separated from the semiconductor region 48; forming second gate regions 34 and 38 adjacent to the first gate regions 32 and 36 and electrically separated from the first gate regions 32 and 36; forming virtual gate regions 24, 26, and 28 of a second conductivity type in the semiconductor region 48 and aligned to the gate regions 32, 34, 36, and 38.