Abstract: A preparation method of a semiconductor device comprising a substrate having formed thereon plural semiconductor elements formed in a matrix form and plural pixel electrodes each connected to each semiconductor element and a liquid crystal layer held on the substrate, comprisinga step of forming the plural pixel electrodes on an interlayer dielectric,a step of heat-treating the plural electrodes to form hillocks and whiskers on the surfaces of the electrodes, anda step of removing the hillocks and the whiskers to flatten the electrode surfaces.The semiconductor device is suitably used for, for example, a reflection type LCD apparatus with pixel electrodes having a good light reflectance and a high anti-brittleness.

Abstract: A wafer includes levels elevated above the wafer substrate or base substrate which includes separated substrates suitable for circuit device element formation. In one embodiment, a first level dielectric is formed over circuit devices having elements formed in the wafer substrate. Contacts from the circuit elements may extend to the surface of the first level dielectric. A second dielectric is formed on the first level dielectric and etched to create separated openings with some openings exposing contacts. The openings are filled with substrate material, thus forming elevated substrates and local interconnects where exposed contact top surfaces are present. The substrate material is suitable for circuit device fabrication. Additional levels of elevated substrates and concurrently formed local interconnects may be subsequently fabricated.

Abstract: Disclosed is a semiconductor device having a silicon on insulator structure capable of achieving a high integration, and a manufacturing method of the same. The semiconductor device includes a semiconductor substrate having a silicon on insulator structure, in which a insulating layer and a semiconductor layer are formed on a semiconductor wafer in sequence. A gate insulating film and a gate are formed on the semiconductor layer. A first impurity diffusion region and a second impurity diffusion region are formed in the semiconductor layer at both sides of the gate. A intermediate insulating layer having a first contact hole for exposing a predetermined portion of the first impurity diffusion region and a second contact hole for exposing a predetermined portion of the second impurity diffusion region and a predetermined portion of the water, is formed on an overall surface of the substrate.

Abstract: An improved field effect transistor (FET) structure is disclosed. It comprises a first insulator layer containing at least one primary level stud extending through the layer; an undoped cap oxide layer disposed over the insulator layer and abutting the upper region of each stud; a primary level thin film transistor (TFT) disposed over the undoped cap oxide layer; and a planarized oxide layer disposed over the TFT. Multiple TFT's can be stacked vertically, and connected to other levels of studs and metal interconnection layers. Another embodiment of the invention includes the use of a protective interfacial cap over the surface of tungsten-type studs. The FET structure can serve as a component of a static random access memory (SRAM) cell. Related processes are also disclosed.

Abstract: A process for planarizing a passivation layer in order to maintain a uniform gap between the passivation layer of a bottom substrate and the top substrate of a LCD integrated circuit device is described. Semiconductor device structures in and on a semiconductor substrate wherein the semiconductor device structures are covered by an insulating layer. A metal layer is deposited and patterned to form metal lines wherein there is a gap between two of the metal lines. A passivation layer is deposited overlying the metal lines wherein the gap is not filled by the passivation layer. A layer of high density plasma oxide is deposited overlying the passivation layer and polished to leave the high density plasma oxide within the gap and to leave a planarized passivation layer surface. This will also a precise gap to be maintained in which to build the liquid crystal display material between the top substrate and the passivation layer of the bottom substrate.

Abstract: A process for integrating a vertical power device, such as an IGBT device, with suitable control circuitry, such as circuitry that provides self-protection from over-temperature (OT), over-voltage (OV) and over-current (OC) conditions. The process yields a vertical power device that is monolithically integrated with, and dielectrically isolated from, its control circuitry with the use of wafer-bonded silicon-on-insulator (SOI) material that yields a buried oxide layer. The process includes simultaneous fabrication of the power device below the buried oxide layer and its control circuitry above the buried oxide layer, in the SOI layer.

Abstract: An EEPROM semiconductor structure is produced with a resistor, a thin-film transistor, a capacitor, and a transistor. The individual implantation steps are utilized to create various structures and, as a result, the production process is substantially simplified.

Abstract: Method of fabricating semiconductor devices such as thin-film transistors by annealing a substantially amorphous silicon film at a temperature either lower than normal crystallization temperature of amorphous silicon or lower than the glass transition point of the substrate so as to crystallize the silicon film. Islands, stripes, lines, or dots of nickel, iron, cobalt, or platinum, silicide, acetate, or nitrate of nickel, iron, cobalt, or platinum, film containing various salts, particles, or clusters containing at least one of nickel, iron, cobalt, and platinum are used as starting materials for crystallization. These materials are formed on or under the amorphous silicon film.

Abstract: A dual level transistor and a fabrication technique for making the transistor. The dual level transistor is an integrated circuit in which a first transistor is formed on an upper surface of a global dielectric and a second transistor is formed on an upper surface of a first local substrate such that the second transistor is vertically displaced from the first transistor. The first local substrate is formed upon a first inter-substrate dielectric. By vertically displacing the first and second transistors, the lateral separation required to isolate first and second transistors in a typical single plane process is eliminated. The integrated circuit includes a semiconductor global substrate. The integrated circuit further includes a first transistor. The first transistor includes a first gate dielectric formed on an upper surface of the global substrate and a first conductive gate structure formed on an upper surface of the first dielectric.

Abstract: Disclosed is a semiconductor device having a silicon on insulator structure capable of achieving a high integration, and a manufacturing method of the same. The semiconductor device includes a semiconductor substrate having a silicon on insulator structure, in which a insulating layer and a semiconductor layer are formed on a semiconductor wafer in sequence. A gate insulating film and a gate are formed on the semiconductor layer. A first impurity diffusion region and a second impurity diffusion region are formed in the semiconductor layer at both sides of the gate. A intermediate insulating layer having a first contact hole for exposing a predetermined portion of the first impurity diffusion region and a second contact hole for exposing a predetermined portion of the second impurity diffusion region and a predetermined portion of the wafer, is formed on an overall surface of the substrate.

Abstract: A method is provided for forming a transistor in which the gate is coupled to a second substrate dielectrically spaced above a first substrate. According to an embodiment, a polysilicon layer is formed across an interposing dielectric layer which is disposed across a single crystalline silicon substrate. The polysilicon layer is doped, making it the second semiconductor substrate. Trench isolation structures may be formed within the second substrate between ensuing active areas. A gate oxide is formed across the second substrate, and an opening is etched through the gate oxide down to the second substrate. A conductive material is formed within the opening, and polysilicon is deposited across the gate oxide. The polysilicon may be etched to form a gate conductor above the gate oxide. LDD implant areas are formed within the second substrate between the gate conductor and adjacent isolation structures.

Abstract: A CMOS device includes a first conductivity type semiconductor substrate having an active region, the active region including two second conductivity type of impurity regions and a first channel region between the two second conductivity type impurity regions, a field insulation region on the semiconductor substrate for electrical isolation of the active region from other adjacent active regions, a second conductivity type semiconductor layer on the field insulation layer, the semiconductor layer including two first conductivity type impurity regions and a second channel region between the two first conductivity type impurity regions, and a gate electrode over the first channel region in the active region and the second channel region in the semiconductor layer.

Abstract: Methods of forming floating-gate ferroelectric random-access-memory (FFRAM) devices include the steps of forming vertically integrated FFRAM unit cells having floating-gate transistors and access transistors positioned at different levels on a semiconductor substrate to increase the density at which the unit cells may be integrated. Preferred methods include the steps of forming a first transistor having opposing floating and control gate electrodes, at a surface of a semiconductor substrate, and then forming a first insulating layer having a first contact hole therein, on the first transistor. The first transistor comprises a layer of ferroelectric material between the floating and control gate electrodes, which can be polarized in respective first and second states to retain logic 1 and logic 0 data. Steps are then performed to form a first electrical interconnect (e.g., conductive plug) in the first contact hole and electrically coupled to the control gate electrode.

Abstract: A manufacturing method applicable for forming a via connection to the thin film transistor in a SRAM unit which resolves the problems arising from a conventional method for forming a via for linking up the drain of a load transistor with the gate of a driver transistor in a SRAM unit by changing the processing sequence and also by forming a plug instead of a via.

Abstract: A diffused resistor and a method for making the diffused resistor are disclosed. The diffused resistor is formed in a substantially pure portion of the thin semiconductor layer that is formed on an insulating substrate. The thin semiconductor layer has low a number of defects and mid-band gap states. This portion may be located in an electrically isolated region of the thin semiconductor layer. A resistive region is used to provide the resistance of the diff-used resistor. Contact regions are provided continguous with the the resistive region. The diff-used resistor can be formed by themselves or in conjunction with other circuit elements, such as a MOSFET, for example. Accordingly, also disclosed is a method for making the diffused resitor in conjunction with a MOSFET. The diffused resistor and the MOSFET are formed in electrically isolated semiconductor islands. The electrically isolated semiconductor islands are formed from the high quality thin semiconductor layer.

Abstract: An integrated circuit fabrication process is provided in which an elevated doped polysilicon structure may be formed. The elevated structure may serve as a junction area of a transistor formed entirely within and upon the elevated polysilicon. The elevated structure frees up space within the lower level substrate for additional transistors and/or lateral interconnect, a benefit of which is to promote higher packing density within the integrated circuit. A transistor is provided which includes a gate conductor spaced between a pair of junctions. A primary interlevel dielectric is deposited across the transistor. A polysilicon structure is formed within a select portion of the upper surface of the primary interlevel dielectric. The polysilicon structure is a spaced distance above and a lateral distance from the transistor. A dopant is implanted into the polysilicon structure. A secondary interlevel dielectric is deposited across the primary interlevel dielectric and the doped polysilicon structure.

Abstract: There is provided a semiconductor memory device including a semiconductor substrate, a pair of transfer transistors formed on the substrate, a pair of driver transistors formed on the substrate, first and second thin film load transistors formed above the transfer transistors and the driver transistors with an interlayer insulative film sandwiched therebetween, a drain region of the first thin film load transistor having at least one portion over which a gate electrode of the second thin film load transistor partially lies. The portion is heavily doped with impurities. The above mentioned semiconductor memory device prevents reduction in ON-state current in thin film transistors, and hence improves stability in operation of SRAM cell having a top gate type thin film transistor.

Abstract: A semiconductor process in which a trench transistor is formed between a pair of planar transistors such that the source/drain regions of the trench transistor are shared with the source/drain regions of the planar transistors. A substrate is provided and first and second planar transistors are formed upon the upper surface of the substrate. The gate dielectric of the trench transistor is vertically displaced below the upper surface of the substrate. The trench transistor shares a first shared source/drain structure with the first planar transistor and a second shared source/drain structure with the second planar transistor. The formation of the trench transistor preferably includes the steps of etching a trench into the substrate, thermally oxidizing a floor of the trench to form a trench gate dielectric, and filling the trench with a conductive material to form a trench gate structure. The trench floor is vertically displaced below the upper surface of the substrate by a trench depth.

Abstract: A multi-dimensional transistor structure is fabricated which includes a base transistor substrate upon which transistors are formed. An elevated substrate is formed overlying the base transistor and having an oxide isolation formed in localized regions beneath the elevated substrate but overlying the base transistor substrate. A plurality of transistors are formed on a substrate wafer to form a base-level transistor formation. An intralevel dielectric (ILD) layer is deposited overlying the base-level transistor formation. Overlying the ILD layer, a "sandwich" structure is formed with the deposition of a first polysilicon layer, deposition of an oxide isolation layer, and deposition of a second polysilicon layer.

Abstract: An elevated transistor formation includes a plurality of planes upon which transistors are formed. The plurality of transistor planes are formed at multiple relative elevations overlying a substrate wafer using deposited polysilicon to form a substrate between the layers. The polysilicon is deposited in a multiple-grain form to achieve an advantageous balance between deposition rate and substrate quality. In particular, columnar polysilicon is deposited at a temperature of approximately 620.degree. C. and above to achieve a high deposition rate directly overlying a lower-elevation transistor plane. High quality polysilicon is then deposited overlying the columnar polysilicon layer at a temperature of approximately 580.degree. C. or below. The deposition rate for high quality polysilicon is substantially lower than the deposition rate for columnar polysilicon. The highest quality substrate, upon which transistors in an elevated transistor plane are formed, is amorphous polysilicon.

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect achieves lower resistivity and capacitance by forming a single gate conductor which is shared by an upper level transistor and a lower level transistor. The shared gate conductor is interposed between a pair of gate dielectrics and each gate dielectric is configured between the single gate conductor and a respective substrate.

Abstract: The present invention pertains to methods of forming integrated circuitry, methods of forming SRAM cells, and methods of reducing alpha particle inflicted damage to SRAM cells. Additionally, the present invention pertains to integrated circuitry. In one aspect, the invention includes a method which includes: a) forming at least one second conductivity type diffusion region beneath at least one of an SRAM cell pull-down device drain of a first conductivity type and an SRAM cell access device source of the first conductivity type; and b) not forming a second conductivity type diffusion region beneath at least one of a source of the SRAM cell pull-down device and a drain of the SRAM cell access device.

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density, but does so with emphasis placed on high performance interconnection between devices on separate levels. The interconnect configuration is made as short as possible between features within one transistor level to features within another transistor level. This interconnect scheme lowers resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of lower level transistor. Alternatively, the gate conductors can be a single conductive entity. In order to abut the gate conductors together, or form a single gate conductor, the upper level transistor is inverted relative to the lower level transistor.

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect achieves lower resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of a lower level transistor. In order to abut the gate conductors together, the upper level transistor is inverted relative to the lower level transistor.

Abstract: The invention is directed to a thin film transistor (TFT) wherein HF precleaning of a gate oxide layer is eliminated, thus avoiding surface degradation and maintaining the smoothness of the gate oxide layer. This results in a TFT that has low Ioff, low stand-by power, and high Ion/Ioff ratio. The invention forms a TFT by depositing a smooth surfaced TFT oxide layer over the TFT gate poly layer. The TFT gate poly layer includes a gate and a drain connection to the drain of a driver. No via hole is patterned over the TFT gate oxide before the TFT body film deposition. Therefore, no HF precleaning step is used. The TFT body layer is then deposited over the gate layer. Source and drain regions are formed in the TFT body layer. In order to connect to drain region of the TFT body layer with the drain connection in the TFT gate layer, a via is formed through the TFT drain and TFT oxide layer.

Abstract: A fabrication method of a semiconductor device that enables to produce a thin film of a refractory-metal silicide at a semiconductor active film without raising any defects such as agglomeration, cracks and voids. A semiconductor active film with a thickness of at most 500 .ANG. is formed on an insulating substructure. A gate insulator film and a gate electrode are formed on the active film. An impurity is selectively doped into the active film to form source and drain regions. The remaining semiconductor active film between the source and drain regions constitutes a channel region. A refractory-metal film is formed to cover the gate electrode and the source and drain regions and is heat-treated, producing first and second silicide films through silicidation reaction of the semiconductor active film with the refractory-metal film as parts of the source and drain regions. Preferably, the refractory-metal film has a thickness of (1/2) to (1/5) times as much as that of the semiconductor active film.

Abstract: The invention is directed to a thin film transistor (TFT) fabricated by using a planarized poly plug as the bottom gate for use in any integrated circuit and in particular a static random access memory (SRAM). The TFT is used in an SRAM device to form a planarized SRAM cell comprising: a pulldown transistor having a control gate and source/drain terminals; a planarized insulating layer having grooves therein, each groove providing access to an underlying conductive material; a planarized conductive plug residing inside each groove, whereby a first conductive plug forms a thin film transistor gate connecting to an to an adjacent inverter and a second conductive plug provides connection to the gate of the pulldown device; a gate dielectric overlying the first planarized conductive plug; and a patterned semiconductive layer doped such that a channel region aligns to each thin film transistor gate and a source/drain region aligns to each side of the channel region is formed.

Abstract: A semiconductor memory and device comprising a plurality of N-channel and P-channel transistor regions, a first and a second field shield region, and an oxide isolation region. The first field shield region is disposed so as to isolate the N-channel transistor regions from one another, and the second field shield region is provided to isolate the P-channel transistor regions from one another. The oxide isolation region is furnished to isolate the N-channel transistor regions from the P-channel transistor regions. The isolation effected by the field shield regions and the isolation provided by the oxide isolation region combine to suppress latch-up, fix the potential in the body regions of the MOS transistors making up the memory or device, and minimize the layout area of the memory or device.

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect employs a via routed directly between the drain region of an upper level transistor to the gate of a lower level transistor so as to effect a direct coupling between the output of one transistor to the input of another. Direct coupling in this fashion affords a lower propagation delay and therefore achieves the benefit of a higher performance, faster switching circuit.

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect employs a via routed directly between a well of an upper level transistor to a well of a lower transistor so as to effect direct coupling between the wells of the respective transistors. Direct coupling in this fashion affords consistent operation of transistors arranged on separate elevation levels.

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect employs a via routed directly between a junction of an upper level transistor to a junction of a lower level transistor so as to effect direct coupling between series or parallel-coupled transistor pairs. Direct coupling in this fashion affords lower parasitic resistance and thereby achieves the benefit of a higher performance, faster switching circuit.

Abstract: Improved field effect transistor (FET) structures are described. They include a thin film transistor (TFT), wherein a contact layer directly connects a diffusion region of the TFT to an active site of another device, e.g., another transistor. This invention is especially suitable for TFT's which are built on one or more conductive studs. Static random access memory (SRAM) cells incorporating one or more of the TFT's are also described.Moreover, this invention is directed to methods for preventing or alleviating the problems associated with gouging during formation of contact layers.

Abstract: To produce a three-dimensional circuit arrangement, a first substrate (1) is thinned, stacked onto a second substrate (2) and fixedly connected to the latter. The first substrate (1) and the second substrate (2) in this case each comprise circuit structures (12, 22) and metallization planes (13, 23). At least one first contact hole (16) and one second contact hole (4) are opened, which reach the metallization plane (13, 23) in the first substrate (1) and second substrate (2), respectively, the second contact hole (4) passing through the first substrate (1). The metallization planes (13, 23) of the two substrates (1, 2) are electrically connected to one another via a conductive layer (7).

Abstract: A dynamic random access memory. The memory includes a write transistor N3 and a read transistor N2. In a preferred embodiment the write transistor has a threshold level higher than the read transistor. A sense amplifier senses and amplifies a difference in voltage between a bit line and a sense node that is developed when the read transistor permits or does-not permit current to flow between ground an a bit line. Associated semiconductor device structures and fabrication techniques are also disclosed.

Abstract: A silicon layer in a lower layer and an interconnection layer arranged in an upper layer are electrically connected through an opening for contact. A silicon plug layer having the same conductivity type as that of the silicon layer is embedded in the opening. The silicon plug layer is embedded in the opening by an etch back method after deposited using a CVD method. The interconnection layer in the upper layer has conductivity type different from that of the silicon plug layer. A refractory metal silicide layer is formed between the upper interconnection layer and the silicon plug layer. The refractory metal silicide layer prevents pn junction from being formed between the upper interconnection layer and the silicon plug layer.

Abstract: A deep trench DRAM cell is formed on a silicon on isolator (SOI) substrate, with a buried strap formed by outdiffusion of dopant in associated trench node material, for providing an electrical connection between the trench node and the active area of a MOS transfer gate formed in the substrate adjacent the trench in an uppermost portion of the substrate.

Abstract: A new method of connecting three-dimensional integrated circuit chips using trench technology is described. Semiconductor device structures are provided in and on the top side of a semiconductor substrate of a first and a second three-dimensional integrated circuit chip. Deep trenches are etched into the first semiconductor substrate. A conductive material is deposited into the trenches. An insulating material is deposited over the surface of the substrate, polished and planarized. The bottom side of the first semiconductor substrate is ground, polished, and selectively etched so that the deep trenches form protrusions from the bottom surface. A passivation layer and a polyimide layer are deposited on the bottom surface of the first semiconductor substrate and etched away around the protrusions. A passivation layer and a polyimide layer are deposited over the top surface of the second semiconductor substrate.