Complementary Field Effect Transistors Patents (Class 438/154)
  • Patent number: 10770561
    Abstract: An annular device is provided. The annular device includes a first transistor including a first input terminal and a second transistor including a second input terminal. The first input terminal and the second input terminal extend radially outward from the annular device, and wherein the first input terminal is aligned with the second input terminal.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: September 8, 2020
    Assignee: SPIN MEMORY, INC.
    Inventors: Gian Sharma, Amitay Levi, Kuk-Hwan Kim
  • Patent number: 10333295
    Abstract: An electrostatic protection circuit includes a first transistor connected to an external terminal, a second transistor that is connected in series to the first transistor and that is in a normally OFF state. The electrostatic protection circuit includes a third transistor that is connected between a power source line and a gate of the first transistor, and a fourth transistor that is connected between the power source line and the gate of the first transistor in the opposite direction to the third transistor.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: June 25, 2019
    Assignee: SOCIONEXT INC.
    Inventor: Masahito Arakawa
  • Patent number: 10297665
    Abstract: An n-doped field effect transistor (nFET) section of an integrated device logic region is provided. The nFET section includes a semiconductor substrate, a layer at least partially formed of silicon germanium (SiGe) disposed on the semiconductor substrate and fin formations. The fin formations are formed on the layer. Each fin formation includes a first fin portion that is at least partially formed of silicon (Si) and a second fin portion that is at least partially formed of hard mask material. The layer is etched to include free surfaces that facilitate elastic relaxation of SiGe therein and a corresponding application of tension in Si of the first fin portion of each of the fin formations.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: May 21, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Nicolas J. Loubet, Devendra K. Sadana
  • Patent number: 9991357
    Abstract: A semiconductor device includes a semiconductor substrate including multiple active regions having a common conductivity type and separate, respective gate electrodes on the separate active regions. Different high-k dielectric layers may be between the separate active regions and the respective gate electrodes on the active regions. Different quantities of high-k dielectric layers may be between the separate active regions and the respective gate electrodes on the active regions. The different high-k dielectric layers may include different work-function adjusting materials.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: June 5, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaeyeol Song, Wandon Kim, Hoonjoo Na, Suyoung Bae, Hyeok-Jun Son, Sangjin Hyun
  • Patent number: 9793296
    Abstract: A method for fabricating substrate of a semiconductor device includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: October 17, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Yin Weng, Cheng-Tung Huang, Ya-Ru Yang, Yi-Ting Wu, Yu-Ming Lin, Jen-Yu Wang
  • Patent number: 9691896
    Abstract: A semiconductor device includes a fin-shaped silicon layer on a silicon substrate surface. The fin-shaped silicon layer has a longitudinal axis extending in a first direction parallel to the surface and a first insulating film is around the fin-shaped silicon layer. A pillar-shaped silicon layer is on the fin-shaped silicon layer, and a pillar diameter of the bottom of the pillar-shaped silicon layer is equal to a fin width of the top of the fin-shaped silicon layer. The pillar diameter and the fin width are parallel to the surface. A gate insulating film is around the pillar-shaped silicon layer and a metal gate electrode is around the gate insulating film. A metal gate wiring is connected to the metal gate electrode and has a longitudinal axis extending in a second direction parallel to the surface and perpendicular to the first direction of the longitudinal axis of the fin-shaped silicon layer.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: June 27, 2017
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9515103
    Abstract: A method of forming an LTPS TFT substrate includes: Step 1: providing a substrate (1) and depositing a buffer layer (2); Step 2: depositing an a-Si layer (3); Step 3: depositing and patterning a silicon oxide layer (4); Step 4: taking the silicon oxide layer (4) as a photomask and annealing the a-Si layer (3) with excimer laser, so that the a-Si layer crystallizes and turns into a poly-Si layer; Step 5: forming a first poly-Si region (31) and a second poly-Si region (32); Step 6: defining a heavily N-doped area and a lightly N-doped area on the first and second poly-Si regions (31) and (32), and forming an LDD area; Step 7: depositing and patterning a gate insulating layer (5); Step 8: forming a first gate (61) and a second gate (62); Step 9: forming via holes (70); and Step 10: forming a first source/drain (81) and a second source/drain (82).
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: December 6, 2016
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Gaiping Lu
  • Patent number: 9484367
    Abstract: A method of forming an integrated photonic semiconductor structure having a photodetector device and a CMOS device may include depositing a dielectric stack over the photodetector device such that the dielectric stack encapsulates the photodetector. An opening is etched into the dielectric stack down to an upper surface of a region of an active area of the photodetector. A first metal layer is deposited directly onto the upper surface of the region of the active area via the opening such that the first metal layer may cover the region of the active area. Within the same mask level, a plurality of contacts including a second metal layer are located on the first metal layer and on the CMOS device. The first metal layer isolates the active area from the occurrence of metal intermixing between the second metal layer and the active area of the photodetector.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: November 1, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Solomon Assefa, Jeffrey P. Gambino, Steven M. Shank
  • Patent number: 9465264
    Abstract: An array substrate and a manufacturing method thereof and a display device are provided, and the array substrate comprises: a substrate (1); a thin film transistor, a passivation layer (5) and a transparent electrode (6), sequentially formed on the substrate, wherein a groove (51) is formed in an upper surface of the passivation layer (5), and the transparent electrode (6) is provided in the groove (51).
    Type: Grant
    Filed: October 12, 2013
    Date of Patent: October 11, 2016
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Seungjin Choi, Seongyeol Yoo, Youngsuk Song
  • Patent number: 9449994
    Abstract: There is provided a TFT backplane having at least one TFT with oxide active layer and at least one TFT with poly-silicon active layer. In the embodiments of the present disclosure, at least one of the TFTs implementing the circuit of pixels in the active area is an oxide TFT (i.e., TFT with oxide semiconductor) while at least one of the TFTs implementing the driving circuit next to the active area is a LTPS TFT (i.e., TFT with poly-Si semiconductor).
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: September 20, 2016
    Assignee: LG Display Co., Ltd.
    Inventors: Hoiyong Kwon, MiReum Lee, Hyoung-Su Kim
  • Patent number: 9431303
    Abstract: Contact liners for integrated circuits and fabrication methods thereof are presented. The methods include: fabricating an integrated circuit structure having a first transistor having at least one of a p-type source region or a p-type drain region and a second transistor having at least one of an n-type source region or an n-type drain region, and the fabricating including: forming a contact liner at least partially over both the first transistor and the second transistor, the contact liner including a first contact liner material and a second contact liner material, wherein the first contact liner material is selected to facilitate electrical connection to the at least one p-type source region or p-type drain region of the first transistor, and the second contact liner material is selected to facilitate electrical connection to the at least one n-type source region or n-type drain region of the second transistor.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: August 30, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Hui Zang
  • Patent number: 9373723
    Abstract: The present invention provides a semiconductor device which suppresses a short circuit and a leakage current between a semiconductor film and a gate electrode generated by a break or thin thickness of a gate insulating film in an end portion of a channel region of the semiconductor film, and the manufacturing method of the semiconductor device. Plural thin film transistors which each have semiconductor film provided over a substrate continuously, conductive films provided over the semiconductor film through a gate insulating film, source and drain regions provided in the semiconductor film which are not overlapped with the conductive films, and channel regions provided in the semiconductor film existing under the conductive films and between the source and drain regions. And impurity regions provided in the semiconductor film which is not overlapped with the conductive film and provided adjacent to the source and drain regions.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: June 21, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Tamae Takano, Atsuo Isobe
  • Patent number: 9349835
    Abstract: A semiconductor device includes gates and a low-k spacer. The low-k spacer includes low-k spacer portions formed upon the gate sidewalls and a low-k spacer portion formed upon a top surface of an underlying substrate adjacent to the gates. When a structure has previously undergone a gate processing fabrication stage, the gates and at least a portion of the top surface of the substrate may be exposed thereby allowing the formation of the low-k spacer. This exposure may include removing any original gate spacers, removing an original liner formed upon the original spacers, and removing any original fill material formed upon the liner.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: May 24, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Charan Veera Venkata Satya Surisetty
  • Patent number: 9287380
    Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: March 15, 2016
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Mark L. Doczy, Suman Datta, Justin K. Brask, Matthew V. Metz
  • Patent number: 9263517
    Abstract: Various aspects include extremely thin semiconductor-on-insulator (ETSOI) layers. In one embodiment, an ETSOI layer includes a plurality of shallow trench isolations (STI) defining a plurality of distinct semiconductor-on-insulator (SOI) regions, the distinct SOI regions having at least three different thicknesses; at least one recess located within the distinct SOI regions; and an oxide cap over the at least one recess.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 16, 2016
    Assignee: GLOBALFOUNDRIES. INC.
    Inventors: Wagdi W. Abadeer, Kiran V. Chatty, Jason E. Cummings, Toshiharu Furukawa, Robert J. Gauthier, Jed H. Rankin, Robert R. Robison, William R. Tonti
  • Patent number: 9257344
    Abstract: An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions. The structure further includes a second semiconductor strip, wherein the first and the second semiconductor strips are formed of the same semiconductor material. Second isolation regions are on opposite sides of the second semiconductor strip. A second epitaxy strip overlaps the second semiconductor strip. A top portion of the second epitaxy strip is over a second top surface of the second isolation regions. The first epitaxy strip and the second epitaxy strip are formed of different semiconductor materials. A bottom surface of the first epitaxy strip is lower than a bottom surface of the second epitaxy strip.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Wei-Jen Lai, Feng Yuan, Tsung-Lin Lee, Chih Chieh Yeh
  • Patent number: 9219187
    Abstract: A solar-powered autonomous CMOS circuit structure is fabricated with monolithically integrated photovoltaic solar cells. The structure includes a device layer including an integrated circuit and a solar cell layer. Solar cell structures in the solar cell layer can be series connected during metallization of the device layer or subsequently. The device layer and the solar cell layer are formed using a silicon-on-insulator substrate. Subsequent spalling of the silicon-on-insulator substrate through the handle substrate thereof facilitates production of a relatively thin solar cell layer that can be subjected to a selective etching process to isolate the solar cell structures.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: December 22, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 9213137
    Abstract: Semiconductor devices and methods for fabricating semiconductor devices are provided. In one example, a method for fabricating a semiconductor device includes etching a waveguide layer in a detector region of a semiconductor substrate to form a recessed waveguide layer section. A ridge structure germanium (Ge) photodetector is formed overlying a portion of the recessed waveguide layer section.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: December 15, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Purakh Raj Verma, Kah-Wee Ang
  • Patent number: 9196613
    Abstract: A method of forming a semiconductor structure includes forming a first plurality of fins in a first region of a semiconductor substrate and a second plurality of fins in a second region of a semiconductor substrate. A gate structure is formed covering a first portion of the first and second plurality of fins. The gate structure does not cover a second portion of the first and second plurality of fins. A first epitaxial layer is grown surrounding the second portion of the first plurality of fins and a second epitaxial layer is grown surrounding the second portion of the second plurality of fins. An ILD layer is deposited and partially etched to expose the first epitaxial layer and a top portion of the second epitaxial layer. A metal layer is deposited around the first epitaxial layer and above the top portion of the second epitaxial layer.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: November 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Charles W. Koburger, III
  • Patent number: 9142545
    Abstract: The electrostatic discharge protection structure includes an N-well disposed on a substrate, a P-well disposed on the substrate and adjacent to the N-well, a first doped region of N-type conductivity disposed in the N-well, a second doped region of N-type conductivity disposed in the N-well, a third doped region of P-type conductivity disposed in the N-well, a fifth doped region of P-type conductivity disposed in the P-well, a fourth doped region of N-type conductivity disposed between the third doped region and the fifth doped region in the P-well, an anode electrically connected to the first doped region and the second doped region, and a cathode electrically connected to the fourth doped region and the fifth doped region.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: September 22, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Chun Chen, Li-Cih Wang, Lu-An Chen, Tien-Hao Tang
  • Patent number: 9136109
    Abstract: A semiconductor device includes a silicon-based substrate, a gate structure and a laminated sacrificial oxide layer. The gate structure is on the silicon-based substrate. The laminated sacrificial oxide layer has a first portion on the silicon-based substrate and a second portion conformal to the gate structure, in which a first thickness of the first portion is substantially the same as a second thickness of the second portion. The laminated sacrificial oxide layer includes a native oxide layer and a silicon oxy-nitride layer. The native oxide layer is on the silicon-based substrate and conformal to the gate structure. The silicon oxy-nitride layer is conformal to the native oxide layer.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: September 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Wei Chiu, Hsin-Yi Tsai, Tzu-Chan Weng, Li-Te Hsu
  • Patent number: 9064889
    Abstract: To improve performance of a semiconductor device. Over a semiconductor substrate, a gate electrode is formed via a first insulating film for a gate insulating film, and a second insulating film extends from over a side wall of the gate electrode to over the semiconductor substrate. Over the semiconductor substrate in a part exposed from the second insulating film, a semiconductor layer, which is an epitaxial layer for source/drain, is formed. The second insulating film has a part extending over the side wall of the gate electrode and a part extending over the semiconductor substrate, and a part of the semiconductor layer lies over the second insulating film in the part extending over the semiconductor substrate.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: June 23, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kenichi Yamamoto, Hiromi Sasaki, Tomotake Morita, Masashige Moritoki
  • Patent number: 9053980
    Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices with at least a portion of each of the wafers bonded together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: June 9, 2015
    Assignee: Luxtera, Inc.
    Inventors: Thierry Pinguet, Steffen Gloeckner, Peter De Dobbelaere, Sherif Abdalla, Daniel Kucharski, Gianlorenzo Masini, Kosei Yokoyama, Guckenberger John, Attila Mekis
  • Publication number: 20150147853
    Abstract: An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material.
    Type: Application
    Filed: January 29, 2015
    Publication date: May 28, 2015
    Inventors: Kangguo Cheng, Bruce B. Doris, Balasubramanian S. Haran, Ali Khakifirooz
  • Publication number: 20150145048
    Abstract: Embodiments of the present invention provide an improved structure and method for forming CMOS field effect transistors. In embodiments, silicon germanium (SiGe) is formed on a PFET side of a semiconductor structure, while silicon is disposed on an NFET side of a semiconductor structure. A narrow isolation region is formed between the PFET and NFET. The NFET fins are comprised of silicon and the PFET fins are comprised of silicon germanium.
    Type: Application
    Filed: November 22, 2013
    Publication date: May 28, 2015
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Steven J. Holmes, Ali Khakifirooz
  • Publication number: 20150140744
    Abstract: An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material.
    Type: Application
    Filed: January 29, 2015
    Publication date: May 21, 2015
    Inventors: Kangguo Cheng, Bruce B. Doris, Balasubramanian S. Haran, Ali Khakifirooz
  • Publication number: 20150140743
    Abstract: An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material.
    Type: Application
    Filed: January 29, 2015
    Publication date: May 21, 2015
    Inventors: Kangguo Cheng, Bruce B. Doris, Balasubramanian S. Haran, Ali Khakifirooz
  • Publication number: 20150137247
    Abstract: A semiconductor device includes a p-type metal oxide semiconductor device (PMOS) and an n-type metal oxide semiconductor device (NMOS) disposed over a substrate. The PMOS has a first gate structure located on the substrate, a carbon doped n-type well disposed under the first gate structure, a first channel region disposed in the carbon doped n-type well, and activated first source/drain regions disposed on opposite sides of the first channel region. The NMOS has a second gate structure located on the substrate, a carbon doped p-type well disposed under the second gate structure, a second channel region disposed in the carbon doped p-type well, and activated second source/drain regions disposed on opposite sides of the second channel region.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 21, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-CHIH CHEN, YING-LANG WANG, CHIH-MU HUANG, YING-HAO CHEN, WEN-CHANG KUO, JUNG-CHI JENG
  • Patent number: 9034705
    Abstract: A method of forming a semiconductor device is disclosed. At least one gate structure is provided on a substrate, wherein the gate structure includes a first spacer formed on a sidewall of a gate. A first disposable spacer material layer is deposited on the substrate covering the gate structure. The first disposable spacer material layer is etched to form a first disposable spacer on the first spacer. A second disposable spacer material layer is deposited on the substrate covering the gate structure. The second disposable spacer material layer is etched to form a second disposable spacer on the first disposable spacer. A portion of the substrate is removed, by using the first and second disposable spacers as a mask, so as to form two recesses in the substrate beside the gate structure. A stress-inducing layer is formed in the recesses.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: May 19, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Tsai-Yu Wen, Tsuo-Wen Lu, Yu-Ren Wang, Chin-Cheng Chien, Tien-Wei Yu, Hsin-Kuo Hsu, Yu-Shu Lin, Szu-Hao Lai, Ming-Hua Chang
  • Publication number: 20150129967
    Abstract: Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (FD-SOI) technology. Lowering the threshold voltages of the transistors can be accomplished through dynamic secondary gate control in which a back-biasing technique is used to operate the dual gate FD-SOI transistors with enhanced switching performance. Consequently, such transistors can operate at very low core voltage supply levels, down to as low as about 0.4 V, which allows the transistors to respond quickly and to switch at higher speeds. Performance improvements are shown in circuit simulations of an inverter, an amplifier, a level shifter, and a voltage detection circuit module.
    Type: Application
    Filed: March 31, 2014
    Publication date: May 14, 2015
    Applicant: STMicroelectronics International N.V.
    Inventors: Anand Kumar, Ankit Agrawal
  • Publication number: 20150123202
    Abstract: A multilayer semiconductor device structure comprising a first buried oxide and a first semiconductor device layer fabricated above the first buried oxide is provided. The first semiconductor device layer comprises a patterned top surface. The patterned surface comprises insulator material and conductor material. The surface density of the insulator material is greater than 40 percent. The multilayer semiconductor device structure further comprises a second buried oxide bonded to the patterned surface of the first semiconductor device layer and a second semiconductor device layer fabricated above the second buried oxide.
    Type: Application
    Filed: November 5, 2013
    Publication date: May 7, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: YI-TANG LIN, CHUN-HSIUNG TSAI, Clement HSINGJEN WANN
  • Publication number: 20150123203
    Abstract: A semiconductor structure having multiple semiconductor-device layers is provided. The semiconductor structure comprises a first buried oxide and a first semiconductor device layer fabricated above the first buried oxide. The first semiconductor device layer comprises a patterned top surface. A blanket layer comprising insulator material is fabricated over the patterned surface. The semiconductor structure further comprises a second buried oxide bonded to the blanket layer and a second semiconductor device layer fabricated above the second buried oxide.
    Type: Application
    Filed: November 6, 2013
    Publication date: May 7, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: YI-TANG LIN, CHUN-HSIUNG TSAI, Clement HSINGJEN WANN
  • Publication number: 20150108576
    Abstract: An integrated circuit includes an NMOS transistor and a PMOS transistor on different regions of an SOT substrate. Each transistor includes a gate region, multilayer lateral insulating regions against the sides of the gate region while also on the substrate. Each multilayer lateral insulating region includes an inclined portion sloping away from the substrate. Source and drain regions are on the substrate and are separated from the sides of the gate region by the corresponding multilayer lateral insulating region. The source and drain regions have an inclined portion resting against the inclined portion of the the lateral insulating region.
    Type: Application
    Filed: September 30, 2014
    Publication date: April 23, 2015
    Inventors: David BARGE, Philippe GARNIER, Yves CAMPIDELLI
  • Publication number: 20150108572
    Abstract: A silicon germanium alloy layer is formed on a semiconductor material layer by epitaxy. An oxygen impermeable layer is formed on the silicon germanium alloy layer. The oxygen impermeable layer and the silicon germanium alloy layer are patterned to form stacks of a silicon germanium alloy fin and an oxygen impermeable cap. A shallow trench isolation structure is formed by deposition, planarization, and recessing or an oxygen permeable dielectric material. An oxygen impermeable spacer is formed around each stack of a silicon germanium alloy fin and an oxygen impermeable cap. A thermal oxidation process is performed to convert a lower portion of each silicon germanium alloy fin into a silicon germanium oxide. During the thermal oxidation process, germanium atoms diffuse into unoxidized portions of the silicon germanium alloy fins to increase the germanium concentration therein.
    Type: Application
    Filed: October 21, 2013
    Publication date: April 23, 2015
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Hong He, Chiahsun Tseng, Yunpeng Yin
  • Patent number: 9006049
    Abstract: Disclosed are process enhancements to fully integrate the processing of a photonics device into a CMOS manufacturing process flow. A CMOS wafer may be divided into different portions. One of the portions is for the CMOS devices and one or more other portions are for the photonics devices. The photonics devices include a ridged waveguide and a germanium photodetector. The germanium photodetector may utilize a seeded crystallization from melt process so there is more flexibility in the processing of the germanium photodetector.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Solomon Assefa, William M. J. Green, Yurii A. Vlasov, Min Yang
  • Patent number: 9006048
    Abstract: Disclosed are process enhancements to fully integrate the processing of a photonics device into a CMOS manufacturing process flow. A CMOS wafer may be divided into different portions. One of the portions is for the CMOS devices and one or more other portions are for the photonics devices. The photonics devices include a ridged waveguide. One or more process steps may be performed simultaneously on the CMOS devices and the photonics devices.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Solomon Assefa, William M. J. Green, Yurii A. Vlasov, Min Yang
  • Patent number: 9006789
    Abstract: A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension III-V semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain. A source region and a drain region are present on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Publication number: 20150097244
    Abstract: A method for making a semiconductor device includes forming a buried oxide stack on a semiconductor wafer. The buried oxide stack includes a first oxide layer, a nitride layer on the first oxide layer, and a second oxide layer on the nitride layer. A semiconductor layer is formed on the second oxide layer. First and second channel regions are formed in the semiconductor layer.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 9, 2015
    Applicant: STMicroelectronics, Inc.
    Inventors: QING LIU, Nicolas Loubet
  • Publication number: 20150093861
    Abstract: An SOI substrate includes first and second active regions separated by STI structures and including gate stacks. A spacer layer conformally deposited over the first and second regions including the gate stacks is directionally etched to define sidewall spacers along the sides of the gate stacks. An oxide layer and nitride layer are then deposited. Using a mask, the nitride layer over the first active region is removed, and the mask and oxide layer are removed to expose the SOI substrate in the first active region. Raised source-drain structures are then epitaxially grown adjacent the gate stacks in the first active region and a protective nitride layer is deposited. The masking, nitride layer removal, and oxide layer removal steps are then repeated to expose the SOI in the second active region. Raised source-drain structures are then epitaxially grown adjacent the gate stacks in the second active region.
    Type: Application
    Filed: October 1, 2013
    Publication date: April 2, 2015
    Applicant: STMICROELECTRONICS, INC.
    Inventors: Nicolas Loubet, Qing Liu, Prasanna Khare
  • Patent number: 8994112
    Abstract: A Fin FET whose fin (12) has an upper portion (30) doped with a first conductivity type and a lower portion (32) doped with a second conductivity type, wherein the junction (34) between the upper portion (30) and the lower portion (32) acts as a diode; and the FinFET further comprises: at least one layer (26, 28) of high-k dielectric material (for example Si3N4) adjacent at least one side of the fin (12) for redistributing a potential drop more evenly over the diode, compared to if the at least one layer of high-k dielectric material were not present, when the upper portion (30) is connected to a first potential and the lower portion (32) is connected to a second potential thereby providing the potential drop across the junction (34). Examples of the k value for the high-k dielectric material are k?5, k?7.5, and k?20.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gerben Doornbos, Robert Lander
  • Patent number: 8987071
    Abstract: A thin-film transistor comprises a semiconductor panel, a dielectric layer, a semiconductor film layer, a conduct layer, a source and a drain. The semiconductor panel comprises a base, an intra-dielectric layer, at least one metal wire layer and at least one via layer. The dielectric layer is stacked on the semiconductor panel. The semiconductor film layer is stacked on the dielectric layer. The conduct layer is formed on the semiconductor film layer. The source is formed on the via of the vias that is adjacent to and connects to the gate via. The drain is formed on another via of the vias that is adjacent to and connects to the gate via. A fabricating method for a thin-film transistor with metal-gates and nano-wires is also disclosed.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: March 24, 2015
    Assignee: National Applied Research Laboratories
    Inventors: Min-Cheng Chen, Chang-Hsien Lin, Chia-Yi Lin, Tung-Yen Lai, Chia-Hua Ho
  • Patent number: 8987072
    Abstract: The present disclosure discloses a method of manufacturing the LTPS array substrate, comprising: depositing a polysilicon layer and an amorphous silicon layer on the substrate successively and crystallizing the amorphous silicon layer to form the polysilicon layer by laser annealing; coating a photoresist layer covering the PMOS area, NMOS area and TFT area of the polysilicon layer; forming a polysilicon pattern and a channel by dry etching the polysilicon layer, then removing the regions of the photoresist layer which are thinner and covering the NMOS area and the TFT area by ashing, the region of the photoresist layer covering the PMOS area is remained. The present disclosure saves the cost of the equipment, improves the yield, reduces the design defect and the process difficulty of the conventional process using 8 photomasks.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: March 24, 2015
    Assignee: EverDisplay Optronics (Shanghai) Limited
    Inventors: Li Tan, ChihMing Lin, HsinAn Lin
  • Patent number: 8987141
    Abstract: A method can include: growing a Ge layer on a Si substrate; growing a low-temperature nucleation GaAs layer, a high-temperature GaAs layer, a semi-insulating InGaP layer and a GaAs cap layer sequentially on the Ge layer after a first annealing, forming a sample; polishing the sample's GaAs cap layer, and growing an nMOSFET structure after a second annealing on the sample; performing selective ICP etching on a surface of the nMOSFET structure to form a groove, and growing a SiO2 layer in the groove and the surface of the nMOSFET structure using PECVD; performing the ICP etching again to etch the SiO2 layer till the Ge layer, forming a trench; cleaning the sample and growing a Ge nucleation layer and a Ge top layer in the trench by UHVCVD; polishing the Ge top layer and removing a part of the SiO2 layer on the nMOSFET structure; performing a CMOS process.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: March 24, 2015
    Assignee: Institute of Semiconductors, Chinese Academy of Sciences
    Inventors: Xuliang Zhou, Hongyan Yu, Shiyan Li, Jiaoqing Pan, Wei Wang
  • Patent number: 8987120
    Abstract: The present invention relates to a flat panel display device comprising a polysilicon thin film transistor and a method of manufacturing the same. Grain sizes of polysilicon grains formed in active channel regions of thin film transistors of a driving circuit portion and a pixel portion of the flat panel display device are different from each other. Further, the flat panel display device comprising P-type and N-type thin film transistors having different particle shapes from each other.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: March 24, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ji-Yong Park, Jae-Bon Koo, Hye-Hyang Park, Ki-Yong Lee, Ul-Ho Lee
  • Patent number: 8987080
    Abstract: Provided are methods for making metal gates suitable for FinFET structures. The methods described herein generally involve forming a high-k dielectric material on a semiconductor substrate; depositing a high-k dielectric cap layer over the high-k dielectric material; depositing a PMOS work function layer having a positive work function value; depositing an NMOS work function layer; depositing an NMOS work function cap layer over the NMOS work function layer; removing at least a portion of the PMOS work function layer or at least a portion of the NMOS work function layer; and depositing a fill layer. Depositing a high-k dielectric cap layer, depositing a PMOS work function layer or depositing a NMOS work function cap layer may comprise atomic layer deposition of TiN, TiSiN, or TiAlN. Either PMOS or NMOS may be deposited first.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: March 24, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Xinliang Lu, Seshadri Ganguli, Atif Noori, Maitreyee Mahajani, Shih Chung Chen, Yu Lei, Xinyu Fu, Wei Tang, Srinivas Gandikota
  • Patent number: 8980733
    Abstract: The semiconductor device has a semiconductor layer, a gate electrode which covers an end portion of the semiconductor layer, and an insulating layer for insulating the semiconductor layer and the gate electrode. The film thickness of the insulating layer which insulates a region where an end portion of the semiconductor layer and the gate electrode overlap each other is thicker than the film thickness of the insulating layer which covers the central portion of the semiconductor layer.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: March 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yukie Suzuki, Yasuyuki Arai, Yoshitaka Moriya, Kazuko Ikeda, Yoshifumi Tanada, Shuhei Takahashi
  • Patent number: 8980702
    Abstract: A method for manufacturing a transistor includes forming a stack of semiconductor on insulator type layers including at least one substrate, surmounted by a first insulating layer and an active layer to form a channel for the transistor; forming a gate stack on the active layer; producing a source and a drain including forming, on either side of the gate stack, cavities by at least one step of etching the active layer, the first insulating layer, and part of the substrate selectively to the gate stack to remove the active layer, the first insulating layer, and a portion of the substrate outside regions situated below the gate stack; forming a second insulating layer on the bared surfaces of the substrate, to form a continuous insulating layer with the first insulating layer; baring of the lateral ends of the channel; and the filling of the cavities by epitaxy.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: March 17, 2015
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Heimanu Niebojewski, Yves Morand, Maud Vinet
  • Patent number: 8975124
    Abstract: One or more embodiments of the disclosed technology provide a thin film transistor, an array substrate and a method for preparing the same. The thin film transistor comprises a base substrate, and a gate electrode, a gate insulating layer, an active layer, an ohmic contact layer, a source electrode, a drain electrode and a passivation layer prepared on the base substrate in this order. The active layer is formed of microcrystalline silicon, and the active layer comprises an active layer lower portion and an active layer upper portion, and the active layer lower portion is microcrystalline silicon obtained by using hydrogen plasma to treat at least two layers of amorphous silicon thin film prepared in a layer-by-layer manner.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: March 10, 2015
    Assignees: Boe Technology Group Co., Ltd., Beijing Asahi Glass Electronics Co., Ltd.
    Inventors: Xueyan Tian, Chunping Long, Jiangfeng Yao
  • Publication number: 20150061006
    Abstract: In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region.
    Type: Application
    Filed: August 14, 2014
    Publication date: March 5, 2015
    Inventors: Hirofumi SHINOHARA, Hidekazu ODA, Toshiaki IWAMATSU
  • Patent number: 8962399
    Abstract: A method is provided for producing a semiconductor layer having at least two different thicknesses from a stack of the semiconductor on insulator type including at least one substrate on which an insulating layer and a first semiconductor layer are successively disposed, the method including etching the first layer so that said layer is continuous and includes at least one first region having a thickness less than that of at least one second region; oxidizing the first layer to form an electrically insulating oxide film on a surface thereof so that, in the first region, the oxide film extends as far as the insulating layer; partly removing the oxide film to bare the first layer outside the first region; forming a second semiconductor layer on the stack, to form, with the first layer, a third continuous semiconductor layer having a different thickness than that of the first and second regions.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: February 24, 2015
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Maud Vinet, Yves Morand, Heimanu Niebojewski