Abstract: Short channel, horizontal gate-all-around (GAA) nanostructure (e.g., nanosheet, nanowire, or the like) transistors, methods of manufacturing and devices formed with the GAA transistors are disclosed herein. According to some methods, the GAA transistors are formed with a guard band for preventing diffusion of APT doping into the channel region, with shallow source/drain depths, and/or with epitaxial growth of the device channel regions after well and APT implantation in the substrate. As such, the GAA transistors are formed to mitigate issues such as bottom sheet voltage threshold (Vt) shift, junction leakage, APT dopant out-diffusion, well proximity effect, APT implant contamination that may be induced by anti-punch through (APT) doping diffusion during fabrication of gate all-around (GAA) transistors. The GAA transistors and methods of manufacturing, however, may be utilized in a wide variety of ways, and may be integrated into a wide variety of devices and technologies.

Abstract: The present disclosure provides a nitride-based bidirectional switching device with substrate potential management capability. The device has a control node, a first power/load node, a second power/load node and a main substrate, and comprises: a nitride-based bilateral transistor and a substrate potential management circuit configured for managing a potential of the main substrate. By implementing the substrate potential management circuit, the substrate potential can be stabilized to a lower one of the potentials of the first source/drain and the second source/drain of the bilateral transistor no matter in which directions the bidirectional switching device is operated. Therefore, the bilateral transistor can be operated with a stable substrate potential for conducting current in both directions.

Abstract: The present disclosure provides a nitride-based bidirectional switching device with substrate potential management capability. The device has a control node, a first power/load node, a second power/load node and a main substrate, and comprises: a nitride-based bilateral transistor and a substrate potential management circuit configured for managing a potential of the main substrate. By implementing the substrate potential management circuit, the substrate potential can be stabilized to a lower one of the potentials of the first source/drain and the second source/drain of the bilateral transistor no matter in which directions the bidirectional switching device is operated. Therefore, the bilateral transistor can be operated with a stable substrate potential for conducting current in both directions.

Abstract: The present disclosure provides a nitride-based bidirectional switching device with substrate potential management capability. The device has a control node, a first power/load node, a second power/load node and a main substrate, and comprises: a nitride-based bilateral transistor and a substrate potential management circuit configured for managing a potential of the main substrate. By implementing the substrate potential management circuit, the substrate potential can be stabilized to a lower one of the potentials of the first source/drain and the second source/drain of the bilateral transistor no matter in which directions the bidirectional switching device is operated. Therefore, the bilateral transistor can be operated with a stable substrate potential for conducting current in both directions.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, a transistor, at least one isolation and at least one non-doped region. The substrate includes a lower portion. The transistor is disposed on the lower portion. The at least one isolation is adjacent to the transistor, and disposed on the lower portion. The at least one non-doped region is disposed between and adjacent to the isolation and the lower portion.

Abstract: A method includes forming a fin structure over a substrate; forming a gate structure over the substrate and crossing the fin structure, wherein the gate structures comprises a gate electrode and a hard mask layer over the gate electrode; forming gate spacers on opposite sidewalls of the gate structure; performing an ion implantation process to form doped regions in the hard mask layers of the gate structure and in the gate spacers, wherein the ion implantation process is performed at a tilt angle; etching portions of the fin structure exposed by the gate structure and the gate spacers to form recesses in the fin structure; and forming source/drain epitaxial structures in the recesses.

Abstract: A display device includes a display panel including a data driver that converts input data into a data signal and supplies the data signal to an output line, a pixel unit including pixels that display an image based on the data signal, a demultiplexer including transistors electrically connected to the output line in the display panel, and transmitting the data signal from the output line to data lines electrically connected to the pixels, and a timing controller that supplies control signals to control a supply timing of the data signal. A number of the transistors are electrically connected in series, and others of the transistors are electrically connected in parallel.

Abstract: Multiple non-silicon semiconductor material layers may be stacked within a fin structure. The multiple non-silicon semiconductor material layers may include one or more layers that are suitable for P-type transistors. The multiple non-silicon semiconductor material layers may further include one or more one or more layers that are suited for N-type transistors. The multiple non-silicon semiconductor material layers may further include one or more intervening layers separating the N-type from the P-type layers. The intervening layers may be at least partially sacrificial, for example to allow one or more of a gate, source, or drain to wrap completely around a channel region of one or more of the N-type and P-type transistors.

Abstract: A method of forming a semiconductor device includes: forming, in a first device region of the semiconductor device, first nanostructures over a first fin that protrudes above a substrate; forming, in a second device region of the semiconductor device, second nanostructures over a second fin that protrudes above the substrate, where the first and the second nanostructures include a semiconductor material and extend parallel to an upper surface of the substrate; forming a dielectric material around the first and the second nanostructures; forming a first hard mask layer in the first device region around the first nanostructures and in the second device region around the second nanostructures; removing the first hard mask layer from the second device region after forming the first hard mask layer; and after removing the first hard mask layer, increasing a first thickness of the dielectric material around the second nanostructures by performing an oxidization process.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure may include a logic device disposed, at a first side of the logic device, on a carrier wafer of the semiconductor structure. The semiconductor structure may include a dielectric structure disposed on a second side of the logic device, the second side being opposite the first side. The semiconductor structure may include a memory device formed on the dielectric structure.

Abstract: A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the gate structure crossing the channel region, source/drain regions on the insulating layer, the source/drain regions being spaced apart from each other with the gate structure interposed therebetween, the channel region connecting the source/drain regions to each other, and contact plugs connected to the source/drain regions, respectively. The channel region includes a plurality of semiconductor patterns that are vertically spaced apart from each other on the insulating layer, the insulating layer includes first recess regions that are adjacent to the source/drain regions, respectively, and the contact plugs include lower portions provided into the first recess regions, respectively.

Abstract: A method of designing a circuit is provided. The method includes: providing a circuit; selecting a first NMOS fin field-effect transistor (FinFET) in the circuit; and replacing the first NMOS FinFET having a first fin number with a second NMOS FinFET having a second fin number and a third NMOS FinFET having a third fin number, wherein the sum of the second fin number and the third fin number is equal to the first fin number.

Abstract: In one aspect, a method of forming a semiconductor device can comprise forming a first transistor structure and a second transistor structure separated by a first trench which comprises a first dielectric wall protruding above a top surface of the transistor structures. The first and the second transistor structures each can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. The method further can comprise depositing a contact material over the transistor structures and the first dielectric wall, thereby filling the first trench and contacting a first source/drain portion of the first transistor structure and a first source/drain portion of the second transistor structure.

Abstract: In one aspect, a method of forming a semiconductor device, can comprise forming a first transistor structure and a second transistor structure separated by a trench. The first and the second transistor structures can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. A first and a second spacer can beformed in the trench at sidewalls of the transistor structures, both protruding above a top surface of the transistor structures. The method can comprise applying a first mask layer including an opening exposing the first spacer at a first source/drain portion of the first transistor structure and covering the second spacer, partially etching the exposed first spacer through the opening, exposing at least parts of a sidewall of the first source/drain portion of the first transistor structure, and removing the mask layer.

Abstract: Aspects of the present disclosure provide 3D semiconductor apparatus and a method for fabricating the same. The 3D semiconductor apparatus can include a first semiconductor device including first S/D regions, a first gate region sandwiched by the first S/D regions, and a first channel surrounded by the first S/D regions and the first gate region; a second semiconductor device stacked on the first semiconductor device that includes second S/D regions, a second gate region sandwiched by the second S/D regions, and a second channel surrounded by the second S/D regions and the second gate region and formed vertically in-situ on the first channel; and silicide formed between the first and second semiconductor devices where the first and second channels interface and coupled to an upper one of the first S/D regions of the first semiconductor device and a lower one of the second S/D regions of the second semiconductor device.

Abstract: Multiple non-silicon semiconductor material layers may be stacked within a fin structure. The multiple non-silicon semiconductor material layers may include one or more layers that are suitable for P-type transistors. The multiple non-silicon semiconductor material layers may further include one or more one or more layers that are suited for N-type transistors. The multiple non-silicon semiconductor material layers may further include one or more intervening layers separating the N-type from the P-type layers. The intervening layers may be at least partially sacrificial, for example to allow one or more of a gate, source, or drain to wrap completely around a channel region of one or more of the N-type and P-type transistors.

Abstract: A method for forming a semiconductor device, the method including: providing a substrate with at least one fin or nanowire; forming a dummy gate; providing spacers on the at least one fin or nanowire and the dummy gate; performing a first RMG module wherein high-k material is provided on at least one fin or nanowire, between the spacers; one or more annealing steps; providing a sacrificial plug between the spacers; epitaxially growing a source and drain in the at least one fin or nanowire; removing the sacrificial plug; performing a second RMG module wherein a WFM is deposited between at least part of the spacers such that the WFM is covering the high-k material of the at least one fin or nanowire.

Abstract: An array substrate for a digital X-ray detector, a digital X-ray detector including the same, and a method for manufacturing the same are disclosed. The array substrate reduces a step difference of a PIN diode, removes a bent part from a lower part to reduce characteristic deterioration of the PIN diode, and increases the size of a formation region of the PIN diode to increase a fill factor. To this end, the array substrate allows a source region of an active layer included in a thin film transistor to be in surface contact with a lower electrode of the PIN diode, and disposes the lower electrode over a planarized source region or a base substrate, such that a step difference of the PIN diode is reduced and fill factor is improved.

Abstract: Generally, the present disclosure provides example embodiments relating to tuning threshold voltages in transistor devices and the transistor devices formed thereby. Various examples implementing various mechanisms for tuning threshold voltages are described. In an example method, a gate dielectric layer is deposited over an active area in a device region of a substrate. A dipole layer is deposited over the gate dielectric layer in the device region. A dipole dopant species is diffused from the dipole layer into the gate dielectric layer in the device region.

Abstract: A semiconductor structure includes a first P-well, a first P-type diffusion region, a first N-type diffusion region, a second P-type diffusion region, and a first poly-silicon layer. The first P-type diffusion region is deposited in the first P-well and coupled to a first electrode. The first N-well is adjacent to the P-well. The first N-type diffusion region is deposited in the first N-well. The second P-type diffusion region is deposited between the first P-type diffusion region and the first N-type diffusion region, which is deposited in the first N-well. The second P-type diffusion region and the first N-type diffusion region are coupled to a second electrode. The first poly-silicon layer is deposited on the first P-type diffusion region.

Abstract: A method for fabricating a semiconductor structure includes forming a fin structure and a gate structure; and forming a source/drain trench in the fin structure on each side of the gate structure. The source/drain trench includes a bottom region and a top region located above the bottom region. Along an extension direction of the fin structure, the dimension of the top region of the source/drain trench is larger than the dimension of the bottom region of the source/drain trench. Along the extension direction of the fin structure, the shortest distance from a sidewall surface of the top region of the source/drain trench to a sidewall surface of the gate structure is smaller than the shortest distance from a sidewall surface of the bottom region of the source/drain trench to the sidewall surface of the gate structure. The method further includes forming a source/drain doped layer in the source/drain trench.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion break device and methods of manufacture. The structure includes a single diffusion break structure with a fill material between sidewall spacers of the single diffusion break structure and a channel oxidation below the fill material.

Abstract: A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

Abstract: A semiconductor device includes a first plurality of stacked nanowire structures extending in a first direction disposed over a first region of a semiconductor substrate. Each nanowire structure of the first plurality of stacked nanowire structures includes a plurality of nanowires arranged in a second direction substantially perpendicular to the first direction. A nanowire stack insulating layer is between the substrate and a nanowire closest to the substrate of each nanowire structure of the first plurality of stacked nanowire structures. At least one second stacked nanowire structure is disposed over a second region of the semiconductor substrate, and a shallow trench isolation layer is between the first region and the second region of the semiconductor substrate.

Abstract: A 3-dimensional vertical memory string array includes high-speed ferroelectric field-effect transistor (FET) cells that are low-cost, low-power, or high-density and suitable for SCM applications. The memory circuits of the present invention provide random-access capabilities. The memory string may be formed above a planar surface of substrate and include a vertical gate electrode extending lengthwise along a vertical direction relative to the planar surface and may include (i) a ferroelectric layer over the gate electrode, (ii) a gate oxide layer; (iii) a channel layer provided over the gate oxide layer; and (iv) conductive semiconductor regions embedded in and isolated from each other by an oxide layer, wherein the gate electrode, the ferroelectric layer, the gate oxide layer, the channel layer and each adjacent pair of semiconductor regions from a storage transistor of the memory string, and wherein the adjacent pair of semiconductor regions serve as source and drain regions of the storage transistor.

Abstract: An annular device is provided. The annular device includes a first transistor including a first input terminal and a second transistor including a second input terminal. The first input terminal and the second input terminal extend radially outward from the annular device, and wherein the first input terminal is aligned with the second input terminal.

Abstract: An electrostatic protection circuit includes a first transistor connected to an external terminal, a second transistor that is connected in series to the first transistor and that is in a normally OFF state. The electrostatic protection circuit includes a third transistor that is connected between a power source line and a gate of the first transistor, and a fourth transistor that is connected between the power source line and the gate of the first transistor in the opposite direction to the third transistor.

Abstract: An n-doped field effect transistor (nFET) section of an integrated device logic region is provided. The nFET section includes a semiconductor substrate, a layer at least partially formed of silicon germanium (SiGe) disposed on the semiconductor substrate and fin formations. The fin formations are formed on the layer. Each fin formation includes a first fin portion that is at least partially formed of silicon (Si) and a second fin portion that is at least partially formed of hard mask material. The layer is etched to include free surfaces that facilitate elastic relaxation of SiGe therein and a corresponding application of tension in Si of the first fin portion of each of the fin formations.

Abstract: A semiconductor device includes a semiconductor substrate including multiple active regions having a common conductivity type and separate, respective gate electrodes on the separate active regions. Different high-k dielectric layers may be between the separate active regions and the respective gate electrodes on the active regions. Different quantities of high-k dielectric layers may be between the separate active regions and the respective gate electrodes on the active regions. The different high-k dielectric layers may include different work-function adjusting materials.

Abstract: A method for fabricating substrate of a semiconductor device includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.

Abstract: A semiconductor device includes a fin-shaped silicon layer on a silicon substrate surface. The fin-shaped silicon layer has a longitudinal axis extending in a first direction parallel to the surface and a first insulating film is around the fin-shaped silicon layer. A pillar-shaped silicon layer is on the fin-shaped silicon layer, and a pillar diameter of the bottom of the pillar-shaped silicon layer is equal to a fin width of the top of the fin-shaped silicon layer. The pillar diameter and the fin width are parallel to the surface. A gate insulating film is around the pillar-shaped silicon layer and a metal gate electrode is around the gate insulating film. A metal gate wiring is connected to the metal gate electrode and has a longitudinal axis extending in a second direction parallel to the surface and perpendicular to the first direction of the longitudinal axis of the fin-shaped silicon layer.

Abstract: A method of forming an LTPS TFT substrate includes: Step 1: providing a substrate (1) and depositing a buffer layer (2); Step 2: depositing an a-Si layer (3); Step 3: depositing and patterning a silicon oxide layer (4); Step 4: taking the silicon oxide layer (4) as a photomask and annealing the a-Si layer (3) with excimer laser, so that the a-Si layer crystallizes and turns into a poly-Si layer; Step 5: forming a first poly-Si region (31) and a second poly-Si region (32); Step 6: defining a heavily N-doped area and a lightly N-doped area on the first and second poly-Si regions (31) and (32), and forming an LDD area; Step 7: depositing and patterning a gate insulating layer (5); Step 8: forming a first gate (61) and a second gate (62); Step 9: forming via holes (70); and Step 10: forming a first source/drain (81) and a second source/drain (82).

Abstract: A method of forming an integrated photonic semiconductor structure having a photodetector device and a CMOS device may include depositing a dielectric stack over the photodetector device such that the dielectric stack encapsulates the photodetector. An opening is etched into the dielectric stack down to an upper surface of a region of an active area of the photodetector. A first metal layer is deposited directly onto the upper surface of the region of the active area via the opening such that the first metal layer may cover the region of the active area. Within the same mask level, a plurality of contacts including a second metal layer are located on the first metal layer and on the CMOS device. The first metal layer isolates the active area from the occurrence of metal intermixing between the second metal layer and the active area of the photodetector.

Abstract: An array substrate and a manufacturing method thereof and a display device are provided, and the array substrate comprises: a substrate (1); a thin film transistor, a passivation layer (5) and a transparent electrode (6), sequentially formed on the substrate, wherein a groove (51) is formed in an upper surface of the passivation layer (5), and the transparent electrode (6) is provided in the groove (51).

Abstract: There is provided a TFT backplane having at least one TFT with oxide active layer and at least one TFT with poly-silicon active layer. In the embodiments of the present disclosure, at least one of the TFTs implementing the circuit of pixels in the active area is an oxide TFT (i.e., TFT with oxide semiconductor) while at least one of the TFTs implementing the driving circuit next to the active area is a LTPS TFT (i.e., TFT with poly-Si semiconductor).

Abstract: Contact liners for integrated circuits and fabrication methods thereof are presented. The methods include: fabricating an integrated circuit structure having a first transistor having at least one of a p-type source region or a p-type drain region and a second transistor having at least one of an n-type source region or an n-type drain region, and the fabricating including: forming a contact liner at least partially over both the first transistor and the second transistor, the contact liner including a first contact liner material and a second contact liner material, wherein the first contact liner material is selected to facilitate electrical connection to the at least one p-type source region or p-type drain region of the first transistor, and the second contact liner material is selected to facilitate electrical connection to the at least one n-type source region or n-type drain region of the second transistor.

Abstract: The present invention provides a semiconductor device which suppresses a short circuit and a leakage current between a semiconductor film and a gate electrode generated by a break or thin thickness of a gate insulating film in an end portion of a channel region of the semiconductor film, and the manufacturing method of the semiconductor device. Plural thin film transistors which each have semiconductor film provided over a substrate continuously, conductive films provided over the semiconductor film through a gate insulating film, source and drain regions provided in the semiconductor film which are not overlapped with the conductive films, and channel regions provided in the semiconductor film existing under the conductive films and between the source and drain regions. And impurity regions provided in the semiconductor film which is not overlapped with the conductive film and provided adjacent to the source and drain regions.

Abstract: A semiconductor device includes gates and a low-k spacer. The low-k spacer includes low-k spacer portions formed upon the gate sidewalls and a low-k spacer portion formed upon a top surface of an underlying substrate adjacent to the gates. When a structure has previously undergone a gate processing fabrication stage, the gates and at least a portion of the top surface of the substrate may be exposed thereby allowing the formation of the low-k spacer. This exposure may include removing any original gate spacers, removing an original liner formed upon the original spacers, and removing any original fill material formed upon the liner.

Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.

Abstract: Various aspects include extremely thin semiconductor-on-insulator (ETSOI) layers. In one embodiment, an ETSOI layer includes a plurality of shallow trench isolations (STI) defining a plurality of distinct semiconductor-on-insulator (SOI) regions, the distinct SOI regions having at least three different thicknesses; at least one recess located within the distinct SOI regions; and an oxide cap over the at least one recess.

Abstract: An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions. The structure further includes a second semiconductor strip, wherein the first and the second semiconductor strips are formed of the same semiconductor material. Second isolation regions are on opposite sides of the second semiconductor strip. A second epitaxy strip overlaps the second semiconductor strip. A top portion of the second epitaxy strip is over a second top surface of the second isolation regions. The first epitaxy strip and the second epitaxy strip are formed of different semiconductor materials. A bottom surface of the first epitaxy strip is lower than a bottom surface of the second epitaxy strip.

Abstract: A solar-powered autonomous CMOS circuit structure is fabricated with monolithically integrated photovoltaic solar cells. The structure includes a device layer including an integrated circuit and a solar cell layer. Solar cell structures in the solar cell layer can be series connected during metallization of the device layer or subsequently. The device layer and the solar cell layer are formed using a silicon-on-insulator substrate. Subsequent spalling of the silicon-on-insulator substrate through the handle substrate thereof facilitates production of a relatively thin solar cell layer that can be subjected to a selective etching process to isolate the solar cell structures.

Abstract: Semiconductor devices and methods for fabricating semiconductor devices are provided. In one example, a method for fabricating a semiconductor device includes etching a waveguide layer in a detector region of a semiconductor substrate to form a recessed waveguide layer section. A ridge structure germanium (Ge) photodetector is formed overlying a portion of the recessed waveguide layer section.

Abstract: A method of forming a semiconductor structure includes forming a first plurality of fins in a first region of a semiconductor substrate and a second plurality of fins in a second region of a semiconductor substrate. A gate structure is formed covering a first portion of the first and second plurality of fins. The gate structure does not cover a second portion of the first and second plurality of fins. A first epitaxial layer is grown surrounding the second portion of the first plurality of fins and a second epitaxial layer is grown surrounding the second portion of the second plurality of fins. An ILD layer is deposited and partially etched to expose the first epitaxial layer and a top portion of the second epitaxial layer. A metal layer is deposited around the first epitaxial layer and above the top portion of the second epitaxial layer.

Abstract: The electrostatic discharge protection structure includes an N-well disposed on a substrate, a P-well disposed on the substrate and adjacent to the N-well, a first doped region of N-type conductivity disposed in the N-well, a second doped region of N-type conductivity disposed in the N-well, a third doped region of P-type conductivity disposed in the N-well, a fifth doped region of P-type conductivity disposed in the P-well, a fourth doped region of N-type conductivity disposed between the third doped region and the fifth doped region in the P-well, an anode electrically connected to the first doped region and the second doped region, and a cathode electrically connected to the fourth doped region and the fifth doped region.

Abstract: A semiconductor device includes a silicon-based substrate, a gate structure and a laminated sacrificial oxide layer. The gate structure is on the silicon-based substrate. The laminated sacrificial oxide layer has a first portion on the silicon-based substrate and a second portion conformal to the gate structure, in which a first thickness of the first portion is substantially the same as a second thickness of the second portion. The laminated sacrificial oxide layer includes a native oxide layer and a silicon oxy-nitride layer. The native oxide layer is on the silicon-based substrate and conformal to the gate structure. The silicon oxy-nitride layer is conformal to the native oxide layer.

Abstract: To improve performance of a semiconductor device. Over a semiconductor substrate, a gate electrode is formed via a first insulating film for a gate insulating film, and a second insulating film extends from over a side wall of the gate electrode to over the semiconductor substrate. Over the semiconductor substrate in a part exposed from the second insulating film, a semiconductor layer, which is an epitaxial layer for source/drain, is formed. The second insulating film has a part extending over the side wall of the gate electrode and a part extending over the semiconductor substrate, and a part of the semiconductor layer lies over the second insulating film in the part extending over the semiconductor substrate.

Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices with at least a portion of each of the wafers bonded together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.

Abstract: An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material.

Abstract: Embodiments of the present invention provide an improved structure and method for forming CMOS field effect transistors. In embodiments, silicon germanium (SiGe) is formed on a PFET side of a semiconductor structure, while silicon is disposed on an NFET side of a semiconductor structure. A narrow isolation region is formed between the PFET and NFET. The NFET fins are comprised of silicon and the PFET fins are comprised of silicon germanium.