Abstract: Classification of spatial patterns on wafer maps is generally described. In one example, a method includes applying K-means type clustering to wafer maps comprising one or more spatial patterns to group one or more clusters comprising wafer maps having similar spatial patterns and producing a dendrogram using a clustering process to display the one or more clusters.

Abstract: A semiconductor device has a first insulation layer formed over a sacrificial substrate. A first conductive layer is formed over the first insulating layer. Conductive pillars are formed over the first conductive layer. A pre-fabricated IPD is disposed between the conductive pillars. An encapsulant is formed around the IPD and conductive pillars. A second insulation layer is formed over the encapsulant. The conductive pillars are electrically connected to the first and second conductive layers. The first and second conductive layers each include an inductor. Semiconductor devices are mounted over the first and second insulating layer and electrically connected to the first and second conductive layers, respectively. An interconnect structure is formed over the first and second insulating layers, respectively, and electrically connected to the first and second conductive layers. The sacrificial substrate is removed.

Abstract: A device and method are provided for detecting stress migration properties of a semiconductor module mounted in a housing. A stress migration test (SMT) structure is formed in the semiconductor module. An integrated heating (IH) device is formed within or in direct proximity to the SMT structure. The SMT structure includes a first interconnect region in a first interconnect layer, a second interconnect region in a second interconnect layer, and a connecting region electrically connecting the interconnect regions through a first insulating layer. The IH device includes a heating interconnect region through which a heating current flows. The heating interconnect region is within or outside the first or second interconnect region or connecting region. When the heating current is applied, a measurement voltage is applied to the SMT structure, and a current through the SMT structure is measured to detect stress migration properties of the semiconductor module.

Abstract: A method of manufacturing a semiconductor device includes preparing two package substrates, electrically coupling a semiconductor wafer to a measuring apparatus, inspecting the wafer, dicing the semiconductor wafer into semiconductor elements and packaging the semiconductor element over the prepared package substrates.

Abstract: A method for manufacturing and for testing an integrated circuit, including the steps of forming, on the upper portion of the integrated circuit, a passivation layer including openings at the level of metal tracks of the last interconnect stack of the integrated circuit; forming, in the openings, first pads connected to second pads formed on the passivation layer by conductive track sections, the first pads being intended for the connection of the integrated circuit; testing the integrated circuit by bringing test tips in contact with the second pads; and eliminating at least a portion of at least one of the conductive track sections.

Abstract: A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted to one or more second integrated circuit chips to physically and electrically connect the integrated circuit chips to one another.

Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit, having a device through via and a device interconnect, over a substrate with the device through via traversing the integrated circuit and the device interconnect attached to the device through via; attaching a conductive support over the substrate with the conductive support adjacent to the integrated circuit; providing a pre-formed interposer, having an interposer through via and a pre-attached interconnect, with the pre-attached interconnect attached to the interposer through via; mounting the pre-formed interposer over the integrated circuit and the conductive support with the pre-attached interconnect over the device through via; and forming an encapsulation over the substrate covering the integrated circuit, the conductive support, and partially covering the pre-formed interposer.

Abstract: A method of fabricating an electronic device having stacked chips is provided. The method includes forming a plurality of chips arranged in a row direction and at least one chip arranged in a column direction. A molding layer is formed between the chips. Grooves are formed in the molding layer between the chips arranged in the row direction. Conductive interconnections are formed on the substrate having the grooves. The substrate is sawn along an odd- or even-numbered one of the grooves to be separated into a plurality of unit substrates. At least one of the separated unit substrates is folded along an unsawn groove of the grooves.

Abstract: A semiconductor device fabrication method can improve yield of semiconductor devices and decrease (or prevent) waste of non-defective semiconductor chips. This fabrication method has a step of performing characteristic inspection after packaging a semiconductor chip every time a semiconductor chip layer is formed. The fabrication method makes another semiconductor chip layer on this semiconductor chip layer only when the inspection indicates that the semiconductor chip is a non-defective product.

Abstract: A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip.

Abstract: A layered chip package includes a plurality of layer portions that are stacked, each of the layer portions including a semiconductor chip. The plurality of layer portions include at least one first-type layer portion and at least one second-type layer portion. The semiconductor chip has a circuit, a plurality of electrode pads electrically connected to the circuit, and a plurality of through electrodes. In every vertically adjacent two of the layer portions, the plurality of through electrodes of the semiconductor chip of one of the two layer portions are electrically connected to the respective corresponding through electrodes of the semiconductor chip of the other of the two layer portions. The first-type layer portion includes a plurality of wires for electrically connecting the plurality of through electrodes to the respective corresponding electrode pads, whereas the second-type layer portion does not include the wires.

Abstract: Methods for the addition polymerization of cycloolefins using a cationic Group 10 metal complex and a weakly coordinating anion of the formula: [(R?)zM(L?)x(L?)y]b[WCA]d wherein [(R?)zM(L?)x(L?)y] is a cation complex where M represents a Group 10 transition metal; R? represents an anionic hydrocarbyl containing ligand; L? represents a Group 15 neutral electron donor ligand; L? represents a labile neutral electron donor ligand; x is 1 or 2; and y is 0, 1, 2, or 3; and z is 0 or 1, wherein the sum of x, y, and z is 4; and [WCA] represents a weakly coordinating counteranion complex; and b and d are numbers representing the number of times the cation complex and weakly coordinating counteranion complex are taken to balance the electronic charge on the overall catalyst complex.

Abstract: A method and apparatus for manufacturing an integrated circuit (IC) device (90) is disclosed. A wafer (10) is first provided having a first or top surface and a second or bottom surface. The wafer may be a blank polished or unpolished silicon wafer or the like. High aspect ratio micro-structures (16) that are specifically designed to provide a die level interconnect configuration and mapping, are provided on the first blank surface (12) of the wafer. The wafer with preformed conductive interconnect microstructures (16) are further processed for device fabrication, for example, at the wafer fabrication facilities. Once the front side (12) devices are fabricated, the silicon material (20) is then removed from a second side (14) of the device wafer (10), opposite the first side, to expose the high temperature conductive interconnect microstructures (16). Contacts are formed on the second side of the device wafer using conductive metal.

Abstract: A process of forming three-dimensional (3D) die. A plurality of wafers are tested for die that pass (good die) or fail (bad die) predetermined test criteria. Two tested wafers are placed in proximity to each other. The wafers are aligned in such a manner so as to maximize the number of good die aligned between the two wafers. The two wafers are then bonded together and diced into individual stacks of bonded good die.

Abstract: Disclosed is a carrier assembly for and a method of manufacturing an optical device. The method comprises providing a silicon substrate; attaching a number of optical dies on the silicon substrate to form an optical device carrier assembly; providing a corresponding number of through holes in the silicon substrate to permit the passage of light therethrough and further providing guide holes in the silicon substrate to present means for passive alignment of an external optical connection; and dicing the optical device carrier assembly to form individual optical devices. Preferably, the step of attaching a number of optical dies comprises using self-alignment of solder bumps using gaseous flux, the through holes are dry etched into the silicon substrate, and/or the volume between the optical die and silicon substrate is filled with a transparent polymer. Preferably, the transparent polymer is silicone rubber or epoxy.

Abstract: Structures, methods, and systems for assessing bonding of electrodes in FCB packaging are disclosed. In one embodiment, a method comprises mounting a semiconductor chip with a plurality of first electrodes of a first shape to a mounted portion with a second electrode of a second shape, wherein the second shape is different from the first shape, bonding a respective on of the plurality of first electrodes and the second electrode using a first solder bump, generating an X-ray image of the first solder bump, and determining an acceptability of the bonding of the respective one of the plurality of first electrodes and the second electrode based on the X-ray image of the first solder bump.

Abstract: Various methods for forming an integrated circuit micro-module are described. In one aspect of the invention, layers of an epoxy are sequentially deposited over a substrate to form planarized layers of epoxy over the substrate. The epoxy layers are deposited using spin coating. At least some of the layers are photolithographically patterned after they are deposited and before the next epoxy layer is deposited. Openings are formed in at least some of the patterned epoxy layers after they are patterned and before the next epoxy layer is deposited. An integrated circuit is placed within one of the openings. At least one of the epoxy layers is deposited after the placement of the integrated circuit to cover the integrated circuit. At least one conductive interconnect layer is formed over an associated epoxy layer. Multiple external package contacts are formed.

Abstract: In constructing a multi-die semiconductor device, a plurality of semiconductor die are provided. Each die is probe tested when it is part of a wafer. Flat contacts are connected to each die when it is part of a wafer. After wafer sawing, each die is tested in a test socket, using the contacts connected thereto. The die are then packaged in stacked relation to form the multi-die semiconductor device.

Abstract: A resin application apparatus includes: an optical property measurement unit measuring an optical property of light emitted from a light emitting diode (LED) chip which is mounted on a package body and to which transparent resin is not applied; and a resin application unit applying light conversion material-containing transparent resin to the LED chip in accordance with a resin application amount which is decided depending on the optical property measured by the optical measurement unit.

Abstract: A method of forming integrated circuits includes providing a wafer that includes a plurality of dies; aligning a first top die to a first bottom die in the wafer; recording a first destination position of the first top die after the first top die is aligned to the first bottom die; bonding the first top die onto the first bottom die; calculating a second destination position of a second top die using the first destination position; moving the second top die to the second destination position; and bonding the second top die onto a second bottom die without any additional alignment action.

Abstract: A semiconductor device and a fabrication method thereof are provided. A semiconductor device which is packaged as it includes a semiconductor in which an electronic circuit is disposed, the semiconductor device including: a substrate; a semiconductor chip which has a semiconductor main body having the electronic circuit formed thereon, a pad electrode formed on the semiconductor main body and a projected electrode that is connected to the pad electrode and projected from a surface of the semiconductor main body, wherein the semiconductor chip is mounted on the substrate from the back side of the surface to form the projected electrode thereon; and an insulating layer which is formed as the semiconductor chip buried therein and is polished from a top surface of the insulating layer to a height at which a top of the projected electrode is exposed.

Abstract: Techniques for modular chip fabrication are provided. In one aspect, a modular chip structure is provided. The modular chip structure comprises a substrate; a carrier platform attached to the substrate, the carrier platform comprising a plurality of conductive vias extending through the carrier platform; and a wiring layer on the carrier platform in contact with one or more of the conductive vias, wherein the wiring layer comprises one or more wiring levels and is configured to divide the carrier platform into a plurality of voltage islands; and chips, chip macros or at least one chip in combination with at least one chip macro assembled on the carrier platform.

Abstract: A wafer-level chip-scale packaging feature for a semiconductor device is disclosed which has a substrate, a plurality of nail-shaped conducting posts extending from a surface of the substrate, and a plurality of solder balls, where each of the solder balls is connected to one of the nail-shaped conducting posts. When a different-sized solder ball is desired for use, the device can be re-processed by only removing and replacing the cross-members of the nail-shaped conducting posts, which cuts down on the re-processing expense.

Abstract: In one or more embodiments, a method comprising applying thermo compression to a package assembly including a lid, a die, and a package substrate to assemble the package assembly is disclosed. The method may include assembling the package assembly without coupling a biasing mechanism to the lid. Heat may be applied to a bond head coupled with a pick and place tool. Heat may be applied to a bond stage coupled to a carrier for holding the package assembly during processing. An adhesive applied to the lid or package substrate may be allowed to at least partially cure. The method may further include, in an oven, reflowing a thermal interface material (TIM) coupled to the lid and the die, curing the TIM, and/or curing the adhesive, without using clips.

Abstract: An image sensor module includes a semiconductor chip, a transparent substrate, and metal lines. The semiconductor chip includes image sensors disposed in an image sensor region, pads electrically connected to the image sensors and disposed in a peripheral region defined along a periphery of the image sensor region, and through-electrodes electrically connected to the pads. The transparent substrate has a groove defined by a surface covering the image sensors and the pads of the semiconductor chip. The metal lines are disposed on a lower surface of the semiconductor chip and are electrically connected to the through-electrodes.

Abstract: A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The polymer layer can be formed using a film assisted molding process including the steps of: forming a mold film on tip portions of the bonding members, molding the polymer layer, and then removing the mold film to expose the tip portions of the bonding members. The through wire interconnect provides a multi level interconnect having contacts on opposing sides of the semiconductor substrate.

Abstract: A layout method that enables a high power switch mode voltage regulator integrated circuit to generate a large output current and achieve substantially low switching loss is disclosed. The layout method includes forming an array of switching elements on a semiconductor die, each switching element including a plurality of discrete transistors configured to have a substantially reduced ON resistance; and forming a plurality of gate driver circuits on the same die among the switching elements, all using a single metal process. Each gate driver circuit placed substantially close to and dedicated to drive only one switching element so that the gate coupling capacitance resistance product is substantially reduced.

Abstract: A method for manufacturing a light emitting device includes: measuring at least one of each wavelength of the emitted light of the light emitting element, each optical output of the emitted light of the light emitting element, and each chromaticity of the mixed light emitted through the mixed resin in a manufacturing process of the light emitting device; and adjusting chromaticity for each light emitting device by performing a prescribed chromaticity adjustment with regard to the mixed resin, on basis of a result obtained in the measuring, so that the chromaticity of the mixed light falls within a preset prescribed range.

Abstract: A method for manufacturing a light emitting diode (LED) assembly comprises the steps of: preparing a chip carrier comprising a carrier substrate, a P type electrode and an N type electrode, and arranging an LED chip onto the carrier substrate to electrically connect the LED chip with the P type electrode and the N type electrode; packaging the LED chip with a light-transmissible packaging gel and making the P type electrode and the N type electrode exposed to form a molded LED chip cell; preparing an arrangement carrier comprising a arrangement carrier substrate, a P type electrode plate and an N type electrode plate; forming an arrangement recess on the arrangement carrier substrate; and arranging the molded LED chip cell into the arrangement recess to make the P type electrode and the N type electrode electrically connect to the P type electrode plate and the N type electrode plate respectively.

Abstract: Aspects of the present invention relate to the arrangement of points of interconnection of integrated circuit die to the package in which they are enclosed. More specifically, aspects of the present invention pertain to an arrangement of bond pads over the active circuitry of an integrated circuit die, in order to permit a reduction in size of the die. An embodiment of the present invention may place a first bond pad over the active area of an integrated circuit, wherein the first bond pad is electrically coupled to a second bond pad outside of the active area of the integrated circuit. Production and delivery of the integrated circuit may proceed using the second bond pad during packaging, in parallel with the testing of packaging using the first bond pad. When processes related to the use of the first bond pad have been proven successful and sustainable, the second bond pad may be eliminated, resulting in a reduction of the size of the integrated circuit device.

Abstract: A structure to be plated includes a body to be plated 11 on which plating is formed, and plated film thickness determining member 16 opposed to and electrically isolated from the body to be plated 11 through a slit portion 12. The plated film thickness determining member 16 has an islands-shape and is conductive. It is possible to instantly determine whether or not the plating formed on the body to be plated 11 has been formed to a thickness larger than the width W of the slit portion 12 on the spot by determining whether or not plating has grown from the surface of the body to be plated 11 to the plated film thickness determining member 16 through the slit portion 21.

Abstract: There are provided a plurality of semiconductor apparatuses judged as good items in electrical and functional inspections while having internal connection terminals disposed on electrode pads of semiconductor chips, resin layers which are disposed on surfaces of the semiconductor chips in which the electrode pads are formed and expose the internal connection terminals, and wiring patterns which are disposed on the resin layers and are connected to the internal connection terminals, a wiring substrate on which the plurality of semiconductor apparatuses are stepwise stacked, the wiring substrate electrically connected to the plurality of semiconductor apparatuses, and a sealing resin with which the plurality of semiconductor apparatuses are sealed.

Abstract: An inspection method includes performing an inspection by applying a probe to pads of a contact check pattern located, together with a chip pattern, on a wafer, and performing an inspection by applying the probe to pads of the chip pattern if a result of the inspection using the contact check pattern is within a predetermined range. A pattern having the same size as that of the chip pattern, differing in external appearance from the chip pattern, and having the same pads as those of the chip pattern is used as the contact check pattern.

Abstract: A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted to one or more second integrated circuit chips to physically and electrically connect the integrated circuit chips to one another.

Abstract: A testing method for a silicon interposer employs a test probe and an electrically conductive glass handler. The silicon interposer includes multiple interconnects that extend between the opposed major surfaces of the interposer, namely from a test side of the interposer to a conductive glass handler side of the interposer. On the glass handler side, the interposer includes a layer of patterned insulative resist with open regions at some interconnects on the glass handler side and remaining resist regions at other interconnects on the glass handler side. The interposer may include a conductive adhesive layer that couples together interconnects at the open regions on the glass handler side. In this manner, a probe may send a test signal from a first interconnect at one location on the test side of the interposer, through the first interconnect, through the conductive adhesive, through a second interconnect to another probe on the test side of the interposer.

Abstract: An image sensor includes: a light source that irradiates a light on an object; a lens body that converges a reflection of the light from the object; a plurality of IC chips that receive the reflection passed through the lens body; and a transparent member provided between the IC chips and the lens body. The transparent member includes a refractive index changing region provided at a portion opposite to a gap between adjacent IC chips. A refractive index in the refractive index changing region increases continuously or stepwise toward an inner portion of the transparent member from a surface of the transparent member on an IC chips side so that the refractive index changing region refracts a part of the reflection to be incident into the gap to the IC chips.

Abstract: This sheet production apparatus comprises a vessel defining a channel configured to hold a melt. The melt is configured to flow from a first point to a second point of the channel. A cooling plate is disposed proximate the melt and is configured to form a sheet on the melt. A spillway is disposed at the second point of the channel. This spillway is configured to separate the sheet from the melt.

Abstract: A method is disclosed for controlling the sheet resistance of copper trenches formed on semiconductor wafers. The method includes forming a plurality of copper-filled trenches on a wafer, measuring the sheet resistance of each of the plurality of copper-filled trenches, and comparing the measured sheet resistance values to a predetermined sheet resistance value. Photolithography steps performed on subsequent wafers are adjusted according to a difference between the measured sheet resistance values and the predetermined value. In one embodiment, this adjustment takes the form of adjusting a photolithographic extension exposure energy to thereby adjust the cross-section of the resulting trenches.

Abstract: A rerouting element for a semiconductor device includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The conductive vias are positioned at locations that correspond to the locations of bond pads of a semiconductor device with which the rerouting element is to be used. The conductive elements, which communicate with corresponding conductive vias, reroute the bond pad locations to corresponding contact pad locations adjacent to one peripheral edge or two adjacent peripheral edges of the rerouted semiconductor device. The rerouting element is particularly useful for rerouting centrally located bond pads of a semiconductor device, as well as for rerouting the peripheral locations of bond pads of a semiconductor device to one or two adjacent peripheral edges thereof. Methods for designing and using the rerouting element are also disclosed, as are semiconductor device assemblies including one or more rerouting elements.

Abstract: A metallic electrode forming method includes: forming a bed electrode on a substrate; forming a protective film with an opening on the bed electrode to expose the bed electrode from the opening; forming a metallic film covering the protective film and the opening; mounting the substrate on an adsorption stage, and measuring a surface shape of the metallic film by a surface shape measuring means; deforming the substrate by a deforming means so that a difference between the principal surface and a cutting surface is within a predetermined range; measuring a surface shape of the principal surface, and determining whether the difference is within a predetermined range; and cutting the substrate along with the cutting surface so that the metallic film is patterned to be a metallic electrode.

Abstract: A writing data processing control apparatus includes an assignment part configured to assign processing of a plurality of pieces of writing data of predetermined divided writing regions, stored in a storage device, one by one to one of a plurality of processing apparatuses in which processing is performed in parallel, and a separation part configured, when a processing error occurred as a result of processing of writing data read from the storage device by a first processing apparatus assigned, to separate the first processing apparatus in which the processing error occurred from assigning targets of subsequent writing data processing, wherein the assignment part reassigns the processing of the writing data in which the processing error occurred to a second processing apparatus being different from the first processing apparatus.

Abstract: Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a wafer level method for packaging micro-systems. A substrate prefabricated with metal vias can be provided. The substrate can also be made by forming holes in a substrate and electroplating an electrically conductive material into the holes to form the vias. Multiple microsystems are formed on a top surface of the substrate. Each microsystem is formed to include multiple layers of planarizing, photo-imageable epoxy, one or more interconnect layers and an integrated circuit. Each interconnect layer is embedded in an associated epoxy layer. The integrated circuit is positioned within at least an associated epoxy layer. The interconnect layers of the microsystems are formed such that at least some of the interconnect layers are electrically coupled with one or more of the metal vias in the substrate.

Abstract: A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.

Abstract: A system for making small modifications to the pattern in standard processed semiconductor devices. The modifications are made to create a small variable part of the pattern against a large constant part of the same pattern. In a preferred embodiment the exposure of the variable and constant parts are done with the same wavelength in the same combined stepper and code-writer. The invention devices a way of writing variable parts of the chip that is automatic, inexpensive and risk-free. A system for automatic design and production of die-unique patterns is also shown.

Abstract: The present invention discloses an electronic device package and a method of the package. In particular, an electronic device package and a method of the package suitable for a bumpless electronic device package with enhanced electrical performance and heat-dissipation efficiency are disclosed. The method comprises: providing a substrate having a plurality of vias and a plurality of electronic devices; forming a gluing layer on a surface of the substrate and fixing the electronic devices on the gluing layer, wherein the electronic devices have I/O units aligned with the vias respectively; forming a plurality of fixing layers in the gaps between the electronic devices; trenching a plurality of openings aligned with the vias respectively in the fixing layer; forming a plurality of metallic conductive units in the vias, the openings and part of the surface of the substrate; and forming a passivation layer over the other surface of the substrate.

Abstract: A hardwired switch of a die stack including eight landing pads is provided. A first, a second, a third, and a fourth landing pads are disposed on a first surface of a die. The second and the fourth landing pads are electrically connected to the first and the third landing pads respectively. A fifth, a sixth, a seventh, and an eighth landing pads are disposed on a second surface of the die. The seventh and the eighth landing pads are electrically connected to the sixth and the fifth landing pads respectively. In a vertical direction of the die, the first, the second, the third, and the fourth landing pads overlap partially or fully with the fifth, the sixth, the seventh, and the eighth landing pads respectively. In addition, an operating method of a hardwired switch is also provided.

Abstract: A method for inspecting a semiconductor device includes carrying out a first test for inspecting characteristics of semiconductor devices under a shielded (dark) condition to discriminate non-defective devices; and carrying out a second test on the semiconductor devices which have passed the first test as non-defective devices, for inspecting characteristics of the semiconductor devices. The second test is carried out while a predetermined color of light is applied to the semiconductor devices.

Abstract: The present invention generally provides an apparatus and a method for automatically calibrating the placement of fragile substrates into a substrate carrier. Embodiments of the present invention also provide an apparatus and a method for inspecting the fragile substrates prior to processing to prevent damaged substrates from being further processed or broken in subsequent transferring steps. Embodiments of the invention also generally provide an apparatus and a method for determining the alignment and orientation substrates that are to be delivered into or removed from a substrate carrier. Embodiments of the invention further provide an apparatus and method for accurately positioning the substrate carrier for substrate loading. The substrate carriers are generally used to support a batch of substrates that are to be processed in a batch processing chamber.

Abstract: A technique is provided which can exactly recognize a chip to be picked up when picking up the chip from a wafer sheet in a process of die bonding a thin chip. A camera is coupled to one end of a lens barrel, an objective lens is attached to an opposite end of the lens barrel, and an image of a main surface of a chip is photographed through the objective lens. A surface-emitting lighting unit, a diffusing plate and a half mirror are internally provided between the lens barrel and the chip. Further, another lens barrel having a coaxial drop lighting function of radiating light to the main surface of the chip along the same optical axis as that of the camera is disposed.

Abstract: A decapsulation apparatus 100 has a laser 8 that removes plastic encapsulant from a device 24. Chamber 20 is sealed. Exhaust port 9 removes debris and fumes. The device 24 is positioned and scanned using an X, Y table 2. A hinged end 4 rotates the device to an acute angle of incidence with respect to a laser 8. Endpoint detector 10 senses the exposed integrated circuit and moves or shuts down the laser 8.