Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a substrate; mounting a base integrated circuit on the substrate; forming a leadframe interposer, over the base integrated circuit, by: providing a metal sheet, mounting an integrated circuit die on the metal sheet, injecting a molded package body on the integrated circuit die and the metal sheet, and forming a ball pad, a bond finger, or a combination thereof from the metal sheet that is not protected by the molded package body; coupling a circuit package on the ball pad; and forming a component package on the substrate, the base integrated circuit, and the leadframe interposer.

Abstract: Various computer-implemented methods are provided. One method for sorting defects in a design pattern of a reticle includes searching for defects of interest in inspection data using priority information associated with individual defects in combination with one or more characteristics of a region proximate the individual defects. The priority information corresponds to modulation levels associated with the individual defects. The inspection data is generated by comparing images of the reticle generated for different values of a lithographic variable. The images include at least one reference image and at least one modulated image. A composite reference image can be generated from two or more reference images. The method also includes assigning one or more identifiers to the defects of interest. The identifier(s) may include, for example, a defect classification and/or an indicator identifying if the defects of interest are to be used for further processing.

Abstract: A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chips or chip stacks.

Abstract: The present invention relates to a dicing tape-integrated film for semiconductor back surface, which includes: a dicing tape including a base material having an asperities-formed surface, and a pressure-sensitive adhesive layer laminated on the base material, and a film for semiconductor back surface laminated on the pressure-sensitive adhesive layer of the dicing tape, in which the dicing tape has a haze of at most 45%.

Abstract: A semiconductor device includes a lead frame, a semiconductor element mounted on the lead frame, and a frame-like member formed on the lead frame, surrounding the semiconductor element, and covering a side surface of the lead frame and exposing a lower surface of the lead frame. The frame-like member has at least one concave portion in a side surface thereof. The concave portion has a ceiling portion located at the same height as or lower than an upper surface of the lead frame, and a bottom portion located higher than the lower surface of the lead frame.

Abstract: An sensor includes a substrate with a magnetic field sensor mounted on the substrate. The magnetic field sensor has a first surface defining a plane. A magnetic flux conducting member has a second surface that is not parallel to the first surface. A non-magnetic member is situated between the magnetic field sensor and the magnetic flux conducting member.

Abstract: A method for LED-module assembly comprising the steps of providing a base portion with a base inner surface and a cover with a cover inner surface which together define a module interior, the cover having at least one opening therethrough; putting a sealing member into the module interior; positioning an LED lens into the cover opening; aligning an LED emitter and the LED lens within the module interior; sealing the module interior by securing the base portion with respect to the cover. The LED emitter is powered for imaging of the LED module to test light-output characteristics. A specific type of the LED lens is selected and its type and orientation are verified. The step of vacuum testing checks for water-air/tightness of the sealing of LED-module interior. A central database provides assembly and testing parameters to automated tool(s) performing each particular step.

Abstract: A dicing method, integrated circuit chip testing method, substrate holding apparatus, and adhesive film are disclosed. A first adhesive film 22 in which the adhesion is reduced by ultraviolet radiation is stretched inside a ring-like frame 21 larger than a wafer size, and a wafer W is adhered on the first adhesion film 22. A second adhesive film 4 in which the adhesion of the two surfaces is reduced by heating is adhered on a plate-like jig 3. After the first film is adhered on the second film, dicing is performed. Since the wafer is adhered to the jig, the relative positions of chips do not shift from each other. This makes it possible to load the wafer together with the jig into a testing apparatus and align electrode pads of the chips with a probe. This allows, e.g., collective testing of a plurality of chips.

Abstract: Provided is a mounting method making it possible to, when an object such as an element, or more particularly, a microscopic object is mounted on a substrate, achieve mounting readily and reliably with high positional precision by: forming an element holding layer 12, which is made of a material whose viscosity can be controlled, on a substrate 11; controlling the viscosity of a first part 12a of the element holding layer 12, which includes a mounting region for an element, into a viscosity making the element naturally movable, and controlling the viscosity of a second part 12b of the element holding layer 12 outside the first part 12a into a viscosity making the element naturally immovable; and after mounting one element 13 in the first part 12a, controlling the viscosity of the first part 12a into the viscosity making the element 13 naturally immovable.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: A semiconductor device fabrication method can improve yield of semiconductor devices and decrease (or prevent) waste of non-defective semiconductor chips. This fabrication method has a step of performing characteristic inspection after packaging a semiconductor chip every time a semiconductor chip layer is formed. The fabrication method makes another semiconductor chip layer on this semiconductor chip layer only when the inspection indicates that the semiconductor chip is a non-defective product.

Abstract: A method for providing access to a feature on a device wafer, and located outside an encapsulation region is described. The method includes forming a cavity in the lid wafer, aligning the lid wafer with the device wafer so that the cavity is located substantially above the feature, and removing material substantially uniformly from the bottom surface of the lid wafer, until an aperture is formed at the cavity, over the feature on the device wafer. By removing material from the lid wafer in a substantially uniform manner, difficulties with the prior art procedure of saw cutting, such as alignment and debris generation, are avoided.

Abstract: Provided is a mounting apparatus which mounts a chip component on a circuit pattern on a circuit board having a plurality of circuit patterns formed thereon. The mounting apparatus is provided with a plurality of bonding tools each of which mounts the chip component on each of the circuit patterns on the circuit board. Each bonding tool is provided with, within a region on the circuit board where the chip component is to be mounted, an exclusive mounting region where only each bonding tool can mount the chip component, and a common mounting region where both the bonding tool and the adjacent bonding tool can mount the chip component. A mounting method is also provided. The mounting tact time of the chip components can be shortened even in case where a plurality of circuit patterns are formed on the circuit board and a failure circuit pattern is included among the circuit patterns which have been formed.

Abstract: A method and apparatus (20) for testing the mounting of an integrated circuit (16) on a printed circuit board (12) using a ball grid array comprises measuring the change in height, or drop, of the integrated circuit (16) relative to the printed circuit board (12) following soldering of the ball grid array and comparing the measured drop with a predetermined range. The integrated circuit is deemed to have been successfully mounted to the printed circuit board if the change in height falls within the predetermined range.

Abstract: A flexible, high density decal and the use thereof methods of forming detachable electrical interconnections between a flexible chip carrier and a printed wiring board. The flexible decal has fine-pitch pads on a first surface and pads of a pitch wider than the fine pitch on a second surface, the fine-pitch pads on the first surface designed to electrically connect to a semiconductor device, and the wider-pitch pads on the second surface designed to electrically connect to a printed wiring board or the like. The pads on the first surface are conductively wired to the pads on the second surface through one or more insulating levels in the flexible decal.

Abstract: A semiconductor module having an integrated structure is manufactured by mounting a semiconductor chip on the side of a surface of a cooling plate via an insulating material, and by molding the semiconductor chip and the cooling plate by a resin-molded member. This method includes the steps of: (a) forming a sprayed insulating film as the insulating material on a surface of the cooling plate; (b) forming a sprayed conductive film on a face of the sprayed insulating film opposite to a face where the cooling plate is provided; (c) checking whether the sprayed conductive film is insulated from the cooling plate by using the sprayed conductive film and the cooling plate as electrodes and applying voltage therebetween; and (d) mounting the semiconductor chip on the upper side of the sprayed conductive film when the sprayed conductive film is insulated, and then resin-molding the semiconductor chip and the cooling plate.

Abstract: A microelectronic package includes a first substrate (120) having a first surface area (125) and a second substrate (130) having a second surface area (135). The first substrate includes a first set of interconnects (126) having a first pitch (127) at a first surface (121) and a second set of interconnects (128) having a second pitch (129) at a second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes a third set of interconnects (236) having a third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with a microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

Abstract: Improved techniques to produce integrated circuit products are disclosed. The improved techniques permit smaller and less costly production of integrated circuit products. One aspect of the invention concerns covering test contacts (e.g., test pins) provided with the integrated circuit products using printed ink. Once covered with the ink, the test contacts are no longer electrically exposed. Hence, the integrated circuit products are not susceptible to accidental access or electrostatic discharge. Moreover, the integrated circuit products can be efficiently produced in a small form factor without any need for additional packaging or labels to electrically isolate the test contacts.

Abstract: A semiconductor device and manufacturing method thereof improving moisture resistance of a FeRAM. After a probe test using a pad, a metal film is formed to cover the pad in an opening of a protective film and a region from the pad to an opening outer periphery of the protective film. On the metal film, a metal bump is formed. The metal film is formed to have a two-layer structure of the first and second metal films. Materials of the lower and upper layers are selected mainly in consideration of adhesion to the protective film and adhesion to the metal bump, respectively. Film formation conditions thereof are set to provide metal films with a desired quality and thickness. Thus, penetration of moisture from the pad or the periphery into a ferroelectric capacitor can be prevented and therefore, occurrence of potential inversion abnormalities due to penetrated moisture can be effectively suppressed.

Abstract: A module substrate may include a substrate body on which a plurality of chip mounting regions having connection pads are defined. Repair structures may be respectively formed, or placed, in the chip mounting regions. Each repair structure includes conductive layer patterns formed over the connection pads in each chip mounting region, an insulation layer pattern formed over the substrate body in each chip mounting region in such a way as to expose the conductive layer patterns, plastic conductive members formed between the connection pads and the conductive layer patterns, and a plastic insulation member formed between the substrate body and the insulation layer pattern in each chip mounting region.

Abstract: Various embodiments of the present invention include a semiconductor device and a fabrication method therefor, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefor, in which downsizing and cost reduction can be realized.

Abstract: A method of placing a die includes providing an embedded plane. The embedded plane has a openings, grid lines, and protruding portions. Each of the plurality of openings are surrounding by a subset of the plurality of grid lines. At least one of the protruding portions extends into one of the openings. A die is placed into one of the openings and at least one of the protruding portions bends during such placement so that it is in contact with at least a portion of a minor surface of the die.

Abstract: A method for controlling mask fabrication is provided, wherein the method uses statistical process control analysis. A manufacturing model is defined. A process run of a mask is performed as defined by the manufacturing model. A fault detection analysis is performed to reduce a bias in the manufacturing model. A fine-tuning signal is generated in response to a result of the fault detection analysis. The process run operation is adjusted according to the fine-tuning signal.

Abstract: A method of manufacturing a sensor module includes providing a substrate comprising a magnetically sensitive sensor element. The sensor element and the substrate are encapsulated with at least one mold material that is configured to apply a bias magnetic field to the sensor element.

Abstract: An object is to prevent a breakage of a membrane probe and a wafer to be tested in a probe testing using a membrane probe with styluses formed by a manufacturing technology for a semiconductor integrated circuit device. Measures are: obtaining an image of a region PCA within the surface of a wafer including a region OGA pressed by a pressing member, at the center of which a chip just after probe-tested is located, by an imaging means such as a camera; comparing an image of a normal chip obtained in advance and an image of all the chips within the region PCA; and judging thereby whether an abnormal shape is caused or not in all the chips within the region PCA.

Abstract: Bonding pad structures and integrated circuits having the same are provided. An exemplary embodiment of a bond pad structure comprises a bond pad layer. A passivation layer partially covers the bond pad layer from edges thereof and exposes a bonding surface, wherein the passivation layer is formed with a recess on at least one edge of the bonding surface to thereby define a probe needle contact area for probe needle testing and a wire bonding area for wire bonding on the bonding surface, and the probe needle contact area and the wire bonding area have a non-overlapping relationship.

Abstract: In a packaging method of semiconductor device, firstly, a wafer including a number of dies is provided. The wafer has an active surface and a back surface. The active surface adheres to a carrier. Subsequently, a number of openings are formed in each of the dies. Then, an insulating layer is formed on the back surface and on the side walls of the openings. A metal layer is formed to cover the insulating layer and the bottoms of the openings. A pattern protective layer is formed to cover the metal layer and to expose the metal layer outside the openings. Afterwards, the carrier is removed and the wafer is sawed. Later, a transparent substrate having a number of package units is provided. A spacer is formed at peripheral of each of the package units. A number of good dies are choose from the dies and disposed on the spacer.

Abstract: The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.

Abstract: A method including forming an intermediate product, the intermediate product being configured to include a wiring substrate including a plurality of first electrodes, a plurality of second electrodes and a plurality of test electrodes, a first semiconductor chip mounted over the wiring substrate and including a plurality of first pads electrically connected respectively to the first electrodes, and a second semiconductor chip stacked over the first semiconductor chip and including a plurality of second pads electrically connected respectively to the second electrodes; encapsulating the first and second semiconductor chips; and performing electrical tests on the first and second semiconductor chips by use of the test electrodes, after the encapsulating of the first and second semiconductor chips.

Abstract: A method for fabricating a flip-chip semiconductor package. The method comprises processing a semiconductor device, for example a semiconductor chip and processing a device carrier, for example a substrate. The semiconductor device comprises bump structures formed on a surface thereof. The substrate comprises bond pads formed on a surface thereof. Processing of the semiconductor chip results in heating of the semiconductor chip to a chip process temperature. The chip process temperature melts solder portions on the bump structures Processing of the substrate results in heating of the substrate to a substrate process temperature. The method comprises spatially aligning the semiconductor chip in relation to the substrate to correspondingly align the bump structures in relation to the bump pads. The semiconductor chip is then displaced towards the substrate for abutting the bump structures of the semiconductor chip with the bond pads of the substrate to thereby form bonds therebetween.

Abstract: A method of enabling a circuit board analysis is disclosed. The method comprising removing a portion of the circuit board on a first side of the circuit board opposite a second side of the circuit board having an integrated circuit package; removing the circuit board from the integrated circuit package; performing a dye mapping to analyze bonds between the integrated circuit package and the circuit board; and performing an analysis of the integrated circuit package.

Abstract: A sheet measurement apparatus has a sheet disposed in a melt. The measurement system uses a beam to determine a dimension of the sheet. This dimension may be, for example, height or width. The beam may be, for example, collimated light, a laser, x-rays, or gamma rays. The production of the sheet may be altered based on the measurements.

Abstract: One aspect of the present invention is a method of mounting a semiconductor chip having: a step of forming a resin coating on a surface of a path connecting a bonding pad on a surface of a semiconductor chip and an electrode pad formed on a surface of an insulating base material; a step of forming, by laser beam machining, a wiring gutter having a depth that is equal to or greater than a thickness of the resin coating along the path for connecting the bonding pad and the electrode pad; a step of depositing a plating catalyst on a surface of the wiring gutter; a step of removing the resin coating; and a step of forming an electroless plating coating only at a site where the plating catalyst remains.

Abstract: Exemplary semiconductor device packaging structure and packaging method are provided. The packaging method uses an adhesive layer to bond multiple wafer pieces onto a first surface of a carrier substrate, each adjacent two of the wafer pieces having a gap formed therebetween for exposing a part of the adhesive layer. A packaging layer is filled in each of the gaps. At least one through silicon via is formed each of the wafer pieces to expose a bonding pad formed on an active surface of the wafer pieces. Redistribution circuit layers are formed on back surfaces of the respective wafer pieces and filled into the through silicon vias for electrical connection with the bonding pads. A sawing process is performed to saw starting from each of the packaging layers to a second surface of the carrier substrate, and thereby multiple semiconductor device packaging structures are obtained.

Abstract: A pressure-sensitive adhesive sheet according to the present invention is a pressure-sensitive adhesive sheet in which a pressure-sensitive adhesive layer is provided on a base film, in which the base film contains conductive fibers, and in which an electrically conductive path is formed between the pressure-sensitive adhesive layer and the base film. With this structure, an electrical continuity test can be performed even in a condition where a semiconductor wafer or a semiconductor chip formed by dicing the semiconductor wafer is applied, and deformation (warping) and damage of the semiconductor wafer and generation of flaws and scratches on the backside can be prevented in the test.

Abstract: A method of fabricating a thin wafer die includes creating circuits and front-end-of-line wiring on a silicon wafer, drilling holes in a topside of the wafer, depositing an insulator on the drilled holes surface to provide a dielectric insulator, removing any excess surface deposition from the surface, putting a metal fill into the holes to form through-silicon-vias (TSV), creating back-end-of-line wiring and pads on the top surface for interconnection, thinning down the wafer to expose the insulator in from the TSVs to adapt the TSVs to be contacted from a backside of the wafer, depositing an insulating layer which contacts the TSV dielectric, thinning down the backside of the wafer, opening through the dielectric to expose the conductor of the TSV to provide a dielectric insulation about exposed backside silicon, and depositing ball limiting metallurgy pads and solder bumps on the backside of the wafer to form an integrated circuit.

Abstract: A method of making an IC device includes providing a stack of leadframe sheets each including a plurality of leadframes and an interleaf member interposed between adjacent ones of the leadframe sheets. The interleaf members include indicia that identifies the leadframes sheets. The stack of leadframe sheets is loaded onto an assembly machine. A first interleaf member is removed from the first leadframe sheet. The first leadframe sheet is transferred onto a mounting surface of the assembly machine. Semiconductor die are attached to leadframes on the first leadframe sheet. The method can include reading the indicia from the first interleaf member to determine a part number and lead finish for the first leadframe sheet, verifying the part number for the first leadframe sheet by comparing to a build list, and transferring the first leadframe sheet onto a mounting surface of the assembly machine only if the part number is verified.

Abstract: Provided are a socket, a semiconductor package, a test device and a method of manufacturing a semiconductor package. A socket to test a semiconductor package comprising a housing, a trench receiving a semiconductor package in the housing, at least one probe connected to the semiconductor package at a bottom of the trench, and at least one connector electrically connecting a plurality of contact points exposed at a side of the semiconductor package when the semiconductor package is inserted into the trench. A semiconductor package with contacts exposed from a side of a package substrate, and a method of manufacturing such a semiconductor package are also disclosed.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a rounded interconnect on a package carrier having an integrated circuit attached thereto; placing a mold chase having a protrusion over the rounded interconnect; forming an encapsulation over the package carrier, the encapsulation having a recess under the protrusion; removing the mold chase to expose the encapsulation; and removing the encapsulation under the recess for exposing the rounded interconnect.

Abstract: A semiconductor device is made by forming a first conductive layer over a sacrificial carrier. A conductive pillar is formed over the first conductive layer. An active surface of a semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the conductive pillar. The carrier and adhesive layer are removed. A stress relief insulating layer is formed over the active surface of the semiconductor die and a first surface of the encapsulant. The stress relief insulating layer has a first thickness over the semiconductor die and a second thickness less than the first thickness over the encapsulant. A first interconnect structure is formed over the stress relief insulating layer. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillar.

Abstract: A semiconductor chip may include at least one power supply pad for receiving an external power voltage, at least one input/output pad, an internal function block that may be configured to operate based on a power voltage to at least one of receive and transmit a signal through the input/output pad, and a mode set circuit that may enable or disable the power voltage by a mode set signal in an individual chip test mode.

Abstract: An over-molded leadframe (e.g., a Quad Flat No-lead (QFN)) package capable of operating at frequencies in the range of about five gigahertz (GHz) to about 300 GHz and a method of making the over-molded leadframe package are disclosed. The over-molded leadframe package includes a capacitance lead configured to substantially reduce and/or offset the inductance created by one or more wirebonds used to connect an integrated circuit (IC) chip on the package to an input/output (I/O) lead. The IC chip is connected to the capacitance lead via one or more wirebonds, and the capacitance lead is then connected to the I/O lead via at least a second wirebond. Thus, inductance created by the one or more wirebonds on the package is substantially reduced and/or offset by the capacitance lead prior to a signal being output by the package and/or received by the IC chip.

Abstract: A method for inspection of defects on a substrate includes positioning a probe of a scanning probe microscopy (SPM) over and spaced apart from a substrate, includes scanning the substrate by changing a relative position of the probe with respect to the substrate on a plane spaced apart from and parallel to the substrate, and includes measuring a value of an induced current generated via the probe in at least two different regions of the substrate. The value of the induced current is variable according to at least a shape and a material of the substrate. The method further includes determining whether a defect exists by comparing the values of the induced currents measured in the at least two different regions of the substrate.

Abstract: Apparatuses including pre-forming conductive bumps on bonding pads for probing and wire-bonding connections and methods for making the same are disclosed. A method may include providing a microelectronic die including a conductive bump formed on a bonding pad, and an insulating layer formed on at least a portion of a surface of the conductive bump, and probing the conductive bump to test the microelectronic die. Other embodiments are also described.

Abstract: A method of manufacturing a semiconductor device comprises: determining whether or not the viscosity of a sealing resin at a first temperature lower than the melting temperature of the sealing resin is less than or equal to a first reference value which prevents poor sealing from occurring at the first temperature, for each lot in which the corresponding sealing resin is manufactured; selecting the sealing resin of the lot when the viscosity of the sealing resin at the first temperature is less than or equal to the first reference value; introducing the sealing resin selected in selecting the sealing resin into a mold of a compression molding apparatus; and sealing a semiconductor chip mounted over a substrate with the sealing resin by compression molding using the mold heated at a second temperature higher than the first temperature after introducing the sealing resin.

Abstract: A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a rounded interconnect on a package carrier having an integrated circuit attached thereto, the rounded interconnect having an actual center; forming an encapsulation over the package carrier covering the rounded interconnect; removing a portion of the encapsulation over the rounded interconnect with an ablation tool; calculating an estimated center of the rounded interconnect; aligning the ablation tool over the estimated center; and exposing a surface area of the rounded interconnect with the ablation tool.

Abstract: A method for profiling a bead of encapsulant extending along an edge of a die mounted to a supporting structure, by depositing a bead of encapsulant onto wire bonds along the edge of the die, positioning a profiling surface over the die at a predetermined spacing from the die, moving the profiling surface across the bead before the bead of encapsulant has cured to reshape the bead profile and, curing the bead of encapsulant. The invention has found that the encapsulant can be effectively shaped by a profiling surface without stripping the encapsulant from the wire bonds. The normally convex-shaped upper surface of the encapsulant bead can be pushed to one side of the bead with the profiling surface. With a lower encapsulant bead, the active surface can be brought into closer proximity with another surface without making contact. For example, the nozzle array on a printhead IC can be 300 microns to 400 microns from the paper path.

Abstract: According to one embodiment, a solid-state imaging device includes a multilayer wiring layer, a semiconductor substrate, an impurity diffusion region of a second conductivity type, an anti-reflection film, a color filter, and a metallic layer. The semiconductor substrate is provided on the multilayer wiring layer and includes a first conductivity type layer. The impurity diffusion region of the second conductivity type partitions the first conductivity type layer into a plurality of regions. The anti-reflection film is provided on the semiconductor substrate. The color filter is provided on the anti-reflection film for each of the partitioned regions. The metallic layer is formed in a region of a lower surface of the semiconductor substrate except the partitioned regions. The anti-reflection film is not provided in a region immediately above the metallic layer.

Abstract: The present invention provides systems and methods for assembling an electronic assembly using an anisotropic conducting membrane (ACM) as a component interconnect and a substrate embossed with placement cavities or a positional fixture to facilitate component placement on the substrate in the electronic assembly. The fixture may comprise multiple layers of interconnects to improve routing density for the electronic assembly enclosed in a housing. An alignment chain may be used to monitor positional and contact integrity of the ACM interfaced components in a complex assembly. The systems and methods allow components to be detached for reuse. Interconnection elements or conduction pathways at the components can be used to interconnect a plurality of neighboring substrates over the ACM layers into a stacked electronic assembly.