Abstract: Methods, systems, and apparatuses are described for improved integrated circuit packages. An integrated circuit package includes a semiconductor substrate and a semiconductor die. The semiconductor substrate has opposing first and second surfaces, a plurality of vias through the semiconductor substrate, and routing one or both surfaces of the semiconductor substrate. The die is mounted to the first surface of the semiconductor substrate. An encapsulating material encapsulates the die on the first surface of the semiconductor substrate.

Abstract: A method for manufacturing an electronic device is disclosed. A design description of the electronic device is generated using one or more computer aided design tools. Physical device data are generated that represent a physical description of the electronic device, which includes data determining connection points for connecting the electronic device to one or more external circuits. A physical embodiment of the electronic device is produced in accordance with the physical device data. Physical test member data is determined that represents conductors and contact points of a test member for testing the electronic device. The test member is produced in accordance with the test member data. The electronic device is tested with the test member.

Abstract: Such a device is disclosed that includes: a row redundancy circuit and a column redundancy circuit for replacing defective sub word lines and defective bit lines included in a memory cell array, respectively; first and second electrical fuse circuits that store the addresses of the defective sub word lines and the defective bit lines, respectively; and a fuse select circuit that selects, in a first operation mode, either one of the first and second electrical fuse circuits based on an address signal supplied when a determination signal is activated, and selects, in a second operation mode, the other of the first and second electrical fuse circuits based on the address signal supplied when the determination signal is activated. According to the present invention, it is possible to flexibly switch between replacement using redundant word lines and replacement using redundant bit lines.

Abstract: A photoelectric conversion module includes a circuit board including a plurality of first board-side electrodes and a plurality of second board-side electrodes that are alternately arranged on a mounting surface of the circuit board in an array direction and each extend into strips in a direction orthogonal to the array direction, a photoelectric conversion array element mounted on the circuit board and including, on a surface facing the mounting surface, a plurality of light receiving/emitting portions, first element-side electrodes connected to the first board-side electrodes and second element-side electrodes connected to the second board-side electrodes, and an IC chip mounted on the circuit board. The circuit board further includes, on the mounting surface, a connecting portion for connecting the first board-side electrodes to each other and a first electrode land portion connected to the first board-side electrode or the connecting portion to contact with a first test electrode probe.

Abstract: Consistent with an example embodiment, there is surface-mountable non-leaded chip carrier for a semiconductor device. The device comprises a first contact. A second contact is relative to the first contact; the second contact has a split therein to provide first and second portions of the second contact arranged relative to one another to lessen tilting of a soldering condition involving attachment of the chip carrier to a printed circuit board.

Abstract: A probe card includes a main circuit board electrically connected to a tester in order to test a plurality of unpackaged sets of chips, a frame provided on the main circuit board and including a plurality of sockets for respectively receiving the unpackaged sets of chips, probe blocks respectively provided in the sockets and including a plurality of probes electrically connected to input/output terminals of the unpackaged sets of chips, and a cover plate positioned over the frame and including a plurality of pressure members for pressurizing the unpackaged sets of chips in the sockets.

Abstract: An active matrix organic electroluminescent device includes a thin-film transistor, an organic electroluminescent device, and a spacer layer deposited between the thin-film transistor and the organic electroluminescent device, wherein the spacer layer is made of adhesive for a dual curing system selected from the group consisting of ultraviolet curing-thermal curing, ultraviolet curing-microwave curing, ultraviolet curing-anaerobic curing, and ultraviolet curing-electron beam curing system. The present invention solves the poor adhesiveness between the thin-film transistor and the organic electroluminescent device, and improves the moisture and oxygen proof ability. The preparation method is simple, effective, and able to lower the cost and difficulty, and greatly improve the yield rate of the device.

Abstract: A method for characterizing the electronic properties of a solar cell to be used in a photovoltaic module comprises the steps of performing a room temperature IV curve measurement of the solar cell and classifying the solar cell based on this IV curve measurement. In order to take stress-related effects into account, the solar cells are reclassified depending on the result of an additional measurement conducted on the solar cells under stress. This stress-related measurement may be gained from light induced thermography (LIT) yielding information on diode shunt areas within the solar cell.

Abstract: An object is to provide a method for manufacturing a lighting device, in which a problem of a short circuit between an upper electrode and a lower electrode of a light-emitting element is solved without reducing a light-emitting property of a normal portion of the light-emitting element to the utmost. In a light-emitting element including an upper electrode, an electroluminescent layer, and a lower electrode, a short-circuited portion that is undesirably formed between the upper electrode and the lower electrode is irradiated with a laser beam, whereby a region where the short-circuited portion is removed is formed, and then the region is filled with an insulating resin having a light-transmitting property. Thus, the problem of the short circuit between the upper electrode and the lower electrode is solved and yield of a lighting device is improved.

Abstract: A method and a system for providing fusing after packaging of semiconductor devices are disclosed. In one embodiment, a semiconductor device is provided comprising a substrate comprising a fuse area, at least one fuse disposed in the fuse area, and at least one layer disposed over the substrate, wherein the at least one layer comprises at least one opening exposing the at least one fuse.

Abstract: A solar device is provided, comprising a substrate structure having a surface region, a flexible and conformal material comprising a polymer material affixing the surface region, and one or more solar cells spatially provided by one or more films of materials characterized by a thickness dimension of 25 microns and less and mechanically coupled to the flexible and conformal material. The one or more solar cells have a flexible characteristic. The flexible characteristic maintains each of the solar cells substantially free from any damage or breakage thereto when the one or more films of materials is subjected to bending.

Abstract: A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SIP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device.

Abstract: A manufacturing method of the MEMS device disposes a conductive circuit to maintain various elements of the MEMS equi-potential thereby preventing electrostatic damages to various elements of the MEMS during the manufacturing process.

Abstract: In a method of testing an object, a first test pattern for testing a first device in the object may be set in a tester. A second test pattern for testing a second device in the object may be set in a test head electrically connected between the tester and the object. The first test pattern may be provided to the first device through the test head and the second test pattern may be provided to the second device by the test head to simultaneously test the first device and the second device. Thus, the first device and the second device different from each other may be simultaneously tested without changing test conditions in the tester, so that a time for testing the object may be reduced.

Abstract: In the fabrication of a semiconductor integrated circuit device, a 2D-3D inspection technique for solder printed on a substrate is provided which permits easy preparation of data and easy visual confirmation of a defective portion. In a substrate inspecting step, first, a 3D inspection is performed, followed by execution of 2D inspection, whereby a 2D picked-up image of the portion of a pad determined to be defective can be displayed on a larger scale simultaneously with the end of inspection, thereby providing an environment for efficient visual confirmation of the defect. Further, by subjecting a raw substrate to measurement at the time of preparing inspection data, a relation between an original height measurement reference generated automatically by the inspection system and the height of a pad upper surface is checked, whereby it is possible to measure the height and volume of printed solder based on the pad upper surface.

Abstract: An integrated circuit device having a multi-layer substrate coupled to receive an integrated circuit die and enabling fixed voltage reference signals of a power distribution network and input/output signals to be routed in the integrated circuit device. The multi-layer substrate comprises a first metal layer comprising a reference signal plane of coupling a first fixed voltage reference signal; a dielectric layer positioned on the first metal layer; and a second metal layer having a plurality of conductive traces, wherein the plurality of conductive traces comprise conductive traces for coupling a second fixed reference signal and input/output signals. The plurality of conductive traces may be in a predetermined pattern having reference signal traces and input/output signal traces. A method of enabling different signals comprising reference signals and input/output signals to be routed in a multi-layer substrate adapted to receive a die in an integrated circuit is also disclosed.

Abstract: A semiconductor chip includes: a first substrate having a first surface and a second surface facing away from the first surface; a first test through silicon via (TSV) passing through the first substrate from the first surface to the second surface; and a conductive protrusion coupled to the first test TSV and protruding from the second surface.

Abstract: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.

Abstract: A method of performing a function on a three-dimensional semiconductor chip package as well as on individual chips in the package is disclosed. That method involves the creation of an operative relationship between a function performer and an edge feature on the chip or chips wherein the edge feature consists of one or more of an electrically conductive pad, thermally conductive pad, a probe pad, a fuse, a resistor, a capacitor, an inductor, an optical emitter, an optical receiver, a test pad, a bond pad, a contact pin, a heat dissipator, an alignment marker, a metrology feature and a function performer may be any one or more of a test probe, the laser, a programming device, an interrogation device, a loading device or a tuning device. In addition, a chip per se with edge features is disclosed along with a three-dimensional stack of such chips in either of several different configurations.

Abstract: One aspect of the present invention relates to an integrated circuit package that includes multiple layers of a planarizing, photo-imageable epoxy that are formed over a substrate. In some designs, the substrate is a silicon wafer. An integrated circuit is embedded in the epoxy. An antenna, which is electrically coupled to the active face of the integrated circuit through an interconnect layer, is formed over one of the epoxy layers. In various embodiments, at least some of the epoxy layers are positioned between the substrate and the antenna such that there is a distance of at least approximately 100 microns between the substrate and the antenna.

Abstract: A plurality of chip stack devices having different external sizes can be tested accurately and efficiently with low cost. The present invention provides a chip stack device testing method testing a chip stack device configured by stacking a plurality of chips separated by dicing a substrate under test tested in a testing unit. A tray for chip stack devices having equal shape and external dimension to those of the undiced substrate under test is used, one or a plurality of the chip stack devices are attached and supported to an adhesive layer of the tray for chip stack devices to align the chip stack devices with positions of the respective chips of the undiced substrate under test, the tray for chip stack devices is installed in the testing unit in a similar manner to that in a test of the substrate under test, and the respective chip stack devices are tested.

Abstract: A method for manufacturing a semiconductor chip stack device is provided. The method includes forming a first connecting element array on a surface of a first semiconductor chip; forming a second connecting element array on a surface of a second semiconductor chip, the second array comprising more connecting elements than the first array and the pitch of the first array being a multiple of the pitch of the second array; applying the first chip against the second chip; and setting up test signals between the first and second chips to determine the matching between the connecting elements of the first array and the connecting elements of the second array.

Abstract: A method of packaging a semiconductor die. The method comprises mounting a semiconductor die to a die attach pad on a carrier and electrically coupling an electrode of the semiconductor die and a contact pad on the carrier with a clip carried by a sacrificial substrate. The method further comprises removing the sacrificial substrate to release the clip. The method may be extended to accommodate a carrier having multiple device regions each with a die attach pad and a contact pad for mounting multiple semiconductor die.

Abstract: The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.

Abstract: A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.

Abstract: An apparatus for manufacturing an light emitting diode (LED) package, includes: a heating unit heating an LED package array in a lead frame state in which a plurality of LED packages are installed to be set in an array on a lead frame; a testing unit testing an operational state of each of the LED packages in the LED package array by applying a voltage or a current to the LED package array heated by the heating unit; and a cutting unit cutting only an LED package determined to be a functional product or an LED package determined to be a defective product from the lead frame to remove the same according to the testing results of the testing unit.

Abstract: A test chip comprises at least one level having an array of regions. Each region is capable of including at least one test structure. At least some of the regions include respective test structures. The level has a plurality of driver lines that provide input signals to the test structures. The level has a plurality of receiver lines that receive output signals from the test structures. The level has a plurality of devices for controlling current flow. Each test structure is connected to at least one of the driver lines with a first one of the devices in between. Each test structure is connected to at least one of the receiver lines with a second one of the devices in between, so that each of the test structures can be individually addressed for testing using the driver lines and receiver lines.

Abstract: A method of performing a wafer level burn-in test for a plurality of surface-emitting laser devices formed on a wafer includes causing a plurality of contact electrodes arranged in a same plane with a pitch same as that of the surface-emitting laser devices being electrically connected to each other to have contact with pad electrodes of the surface-emitting laser devices, respectively, and applying a current to second electrodes of the surface-emitting laser devices and the contact electrodes. The wafer level burn-in test is performed while heating the wafer at a predetermined temperature. Laser lights emitted from the surface-emitting laser devices are monitored during the wafer level burn-in test.

Abstract: A semiconductor device is obtained, in which excellent characteristics are achieved, the reliability is improved, and an SiC wafer can also be used for the fabrication. A plurality of Schottky-barrier-diode units 10 is formed on an SiC chip 9, and each of the units 10 has an external output electrode 4 independently of each other. Bumps 11 (the diameter is from several tens to several hundreds of ?m) are formed only on the external output electrodes 4 of non-defective units among the units 10 formed on the SiC chip 9, meanwhile bumps are not formed on the external output electrodes 4 of defective units in which the withstand voltage is too low, or the leakage current is too much.

Abstract: An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices are attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.

Abstract: A manufacturing method of electronic components includes forming a first insulation layer on a substrate, forming a plurality of passive elements on the first insulation layer, forming a second insulation layer on the passive elements, forming a plurality of conductor layers electrically connected to the respective passive elements, on the outer side of the second insulation layer to be exposed to an upper surface of each electronic component, and forming grooves between the electronic components including the respective passive elements to expose side surfaces of each electronic component and parts of the conductor layers from the side surfaces of each electronic component. The manufacturing method further including plating a plurality of external electrodes on the respective conductor layers exposed to the upper surface and the side surfaces of each electronic component, and cutting the substrate to completely separate into individual electronic components.

Abstract: In one or more embodiments, a method comprising applying thermo compression to a package assembly including a lid, a die, and a package substrate to assemble the package assembly is disclosed. The method may include assembling the package assembly without coupling a biasing mechanism to the lid. Heat may be applied to a bond head coupled with a pick and place tool. Heat may be applied to a bond stage coupled to a carrier for holding the package assembly during processing. An adhesive applied to the lid or package substrate may be allowed to at least partially cure. The method may further include, in an oven, reflowing a thermal interface material (TIM) coupled to the lid and the die, curing the TIM, and/or curing the adhesive, without using clips.

Abstract: A method of producing an electronic connection device, including: a) formation, in a plane of a support substrate, of at least one first contact element and, in a direction approximately perpendicular to the plane, of at least one second contact element having a first end in electrical contact with the first contact element or elements and a second end, the second contact element or elements including one or more metal tracks standing up along the direction perpendicular to the surface of the substrate; b) then positioning at least one electrical or electronic component in contact with the first contact element or elements; and c) encapsulation of the component(s) and of the first and second contact elements, at least the second end or ends of the second contact element or elements being flush with the surface of the encapsulating material.

Abstract: A method for aligning a wafer stack includes providing a wafer stack including a top wafer with a top mark and a bottom wafer with a bottom mark in particular the top mark and the bottom mark capable of corresponding to each other; adjusting a relative position between the top wafer and the bottom wafer so that the top mark and the bottom mark are in contact with each other; applying an electrical signal on the top mark to obtain an electrical reading and optimizing the electrical reading to substantially align the wafer stack.

Abstract: A method for manufacturing a light emitting device includes forming a plurality of light emitting elements on a light emitting element substrate. an identification portion is formed on each of the light emitting elements to allow a pertinent light emitting element to be distinguishable from other light emitting elements. The light emitting elements are separated to form a plurality of light emitting devices. The identification portion may have an external appearance allowing each of the light emitting elements to be distinguishable from the other light emitting elements.

Abstract: Solid state lighting (SSL) devices with good color uniformity and methods of manufacturing are disclosed herein. In one embodiment, an SSL device includes a support structure, an SSL die in the support structure, and a converter material at least partially encapsulating the SSL die. The converter material is configured to emit under excitation. The converter material has a surface facing away from the SSL die, and the surface of the converter material has a generally convex shape.

Abstract: A method for fabricating an integrated circuit (IC) product and IC product formed thereby. The method includes designing an IC package having a plurality of IC connection sets, each configured to be connected to a corresponding IC selected from among a plurality of ICs, each having different functionality. Various IC products can be produced depending upon which selected IC is connected to its corresponding connection set, and the IC package can be cut during design to exclude IC connection sets corresponding to ICs that are not selected. By testing the complete IC package, a portion of the complete IC package can be fabricated, cut from the complete IC package, with significantly reduced design and testing requirements.

Abstract: A Light-Emitting Diode (LED) is formed on a sapphire substrate that is removed from the LED by grinding and then etching the sapphire substrate. The sapphire substrate is ground first to a first specified thickness using a single abrasive or multiple abrasives. The remaining sapphire substrate is removed by dry etching or wet etching.

Abstract: A chip on film (COF) package and a method for manufacturing same are provided. The COF package comprises a base film, a semiconductor chip mounted on the base film, a signal-inputting portion mounted on the base film, a first passive element mounted on the base film and comprising first and second terminals and a first signal line formed on the base film and connecting the first passive element to the semiconductor chip, wherein the first signal line comprises a connection pad connected to the first terminal of the first passive element and a first test line connected to the signal-inputting portion.

Abstract: A semiconductor device includes: a first semiconductor chip; and a second semiconductor chip that is stacked on the first semiconductor chip. The first semiconductor chip includes a first wiring portion of which a side surface is exposed at a side portion of the first semiconductor chip. The second semiconductor chip includes a second wiring portion of which a side surface is exposed at a side portion of the second semiconductor chip. The respective side surfaces of the first wiring portion and the second wiring portion, which are exposed at the side portions of the first semiconductor chip and the second semiconductor chip, are covered by a conductive layer, and the first wiring portion and the second wiring portion are electrically connected to each other through the conductive layer.

Abstract: A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move arbitrarily, on which the chip assemblies are placed; a storage unit that stores an estimated extent of change in a position of an electrode at each chip, expected to occur as heat is applied to the chip assemblies placed on the plurality of stages during a stacking process; and a control unit that sets positions of the plurality of stages to be assumed relative to each other during the stacking process based upon the estimated extent of change in the position of the electrode at each chip provided from the storage unit and position information indicating positions of individual chips formed at the chip assemblies and controls at least one of the plurality of stages.

Abstract: A method for detecting the under-fill void of the flip chip ball grid array package structure is provided, which includes providing a substrate having an interconnect structure and a plurality of interposers therein; providing a chip having an active surface and a back side, and a plurality of first connecting elements on the active surface of the chip; mounting and electrically connecting the active surface of the chip on the substrate; performing at least once IR reflow to fix the plurality of first connecting elements on the substrate; filling an encapsulate material to cover the active surface of the chip and the plurality of first connecting elements; performing a detecting process to detect that void is not formed between the active surface of the chip and the plurality of first elements; and forming a plurality of second connecting elements on the back side of the substrate to obtain a flip chip ball grid array package structure.

Abstract: The present invention is directed to a system that programmably interconnects integrated circuit chips and other components at near-intra-chip density. The system's contact structure allows it to adapt to components with a wide variety of contact spacings and interconnection requirements, the use of releasable attachment means allows component placement to be modified as needed, the system identifies the contacts and the components to facilitate specifying the inter-component connections, and the system provides signal conditioning and retiming to minimize issues with signal integrity and signal skew.

Abstract: An integrated circuit 15 is placed onto a lead frame 101 having lead fingers 109 of substantially constant thickness along their length. Wires are formed from the lead fingers 109 to corresponding electrical contacts the integrated circuit. Following the wire bonding process, the thickness of the tips of the lead fingers 109 is reduced by a laser process, to form tips of reduced thickness desirable for a subsequent moulding operation. Thus, at the time of the wire bonding the tips of the fingers 109 need not have a gap beneath them, so that more secure wire bonds to the lead fingers 109 can be formed.

Abstract: A method of manufacturing is provided that includes applying a thermal interface tape to a side of a semiconductor wafer that includes at least one semiconductor chip. The thermal interface material tape is positioned on the at least one semiconductor chip. The at least one semiconductor chip is singulated from the semiconductor wafer with at least a portion of the thermal interface tape still attached to the semiconductor chip.

Abstract: A method for detecting soft errors in an integrated circuit (IC) due to transient-particle emission, the IC comprising at least one chip and a substrate includes mixing an epoxy with a radioactive source to form a hot underfill (HUF); underfilling the chip with the HUF; sealing the underfilled chip; measuring a radioactivity of the HUF at an edge of the chip; measuring the radioactivity of the HUF on a test coupon; testing the IC for soft errors by determining a current radioactivity of the HUF at the time of testing based on the measured radioactivity; and after the expiration of a radioactive decay period of the radioactive source, using the IC in a computing device by a user.

Abstract: A method and apparatus for dispensing a volume of die attach adhesive onto a surface can include an optical system which images the dispensed volume of die attach adhesive. A two-dimensional area covered by the die attach adhesive and a die attach dispense pressure can be used as a comparison with a reference value to determine whether the volume of die attach adhesive dispensed is sufficient. The reference value can take into account viscosity changes of the die attach adhesive, so that the volume of die attach adhesive dispensed during production can be determined. The volume dispensed can be automatically adjusted in situ during production using a computer system.

Abstract: A method of manufacturing a semiconductor device includes preparing two package substrates, electrically coupling a semiconductor wafer to a measuring apparatus, inspecting the wafer, dicing the semiconductor wafer into semiconductor elements and packaging the semiconductor element over the prepared package substrates.

Abstract: Provided is a method of manufacturing a ceramic probe card. A ceramic laminated body having a plurality of ceramic green sheets and an interlayer circuit including a conductive via and a conductive line formed in the plurality of ceramic green sheets is prepared. Then, at least one probe pin structure connected to the interlayer circuit is formed by selectively removing the plurality of photosensitive ceramic sheets having a ceramic powder and a photosensitive organic component on the ceramic laminated body necessarily, and by filling a metal material in a region from which the plurality of photosensitive ceramic sheets have been removed. Then, a ceramic substrate having the at least one probe pin structure is provided by simultaneously firing the ceramic laminated body and the photosensitive ceramic sheets, and by removing the photosensitive ceramic sheets.

Abstract: The present invention is a method for evaluating a silicon wafer by measuring, after fabricating a MOS capacitor by forming an insulator film and one or more electrodes sequentially on a silicon wafer, a dielectric breakdown characteristic of the insulator film by applying an electric field from the electrodes thus formed to the insulator film, the method in which the silicon wafer is evaluated at least by setting an area occupied by all the electrodes thus formed to 5% or more of an area of a front surface of the silicon wafer when the one or more electrodes are formed. This provides an evaluation method that can detect a defect by a simple method such as the TDDB method with the same high degree of precision as that of the DSOD method.