Abstract: An component mounter including a warning notification apparatus, which includes a warning generating unit which generates a warning for notifying that an action involving human resource is required, by referring to warning generation information, a warning level judging unit which judges a level of the warning indicating difficulty of an action to be taken in response to the warning by referring to warning level judgment information, and a warning notification unit which specifies an operator permitted to perform the action in response to the warning by referring to execution permission authentication information, and outputs the warning notifying the specified operator of the warning.

Abstract: A dislocation-free sheet may be formed from a melt. A sheet of material with a first width is formed on a melt of the material using a cooling plate. This sheet has dislocations. The sheet is transported with respect to the cooling plate and the dislocations migrate to an edge of the sheet. The first width of the sheet is increased to a second width by the cooling plate. The sheet does not have dislocations at the second width. The cooling plate may have a shape with two different widths in one instance. The cooling plate may have segments that operate at different temperatures to increase the width of the sheet in another instance. The sheet may be pulled or flowed with respect to the cooling plate.

Abstract: The invention claimed is a packaged semiconductor device with dual exposed surfaces and a method of manufacturing the device. A thermal clip and one or multiple source pads are exposed on opposite ends of the device through a nonconductive molding material used to package the device. The thermal clip and source pad can be either top or bottom-exposed. The gate, source and drain leads are exposed through the molding material, and all leads are coplanar with the bottom-exposed surface. The device can have multiple semiconductor dies or various sized dies while still having a single, constant footprint. The method of manufacturing requires attaching the semiconductor die to a thermal clip, and then attaching the die with the attached thermal clip to a lead frame. The resulting device is then molded, marked, trimmed and singulated, in this order, creating a packaged semiconductor device with dual exposed surfaces.

Abstract: A method of attaching a pair of chips, each having primary contacts that can be mated to each other, involves forming one or more secondary contacts on each of the two chips of a shape sufficient to prevent an initial attachment material from contacting any of the primary contacts during a preliminary attachment operation, the secondary contacts further having a height that will prevent the primary contacts from touching when the secondary contacts are brought into contact with each other, bringing the secondary contacts into closer and closer aligned proximity to each other at least until the primary contacts touch in a first phase, and heating the primary contacts until material between each of corresponding primary contacts on each of the chips in the pair forms an electrical connection.

Abstract: In a semiconductor device constituted of stacked semiconductor chips, in order to independently test each of the chips, a second chip is disposed to face a first chip, with a second interconnection terminal thereof connected to a first interconnection terminal of the first chip. First and second external terminals of the first and second chips are formed on surfaces of the first and second chips, the surface being on a same side of the first and second chips. Therefore, even after the first chip and the second chip are pasted together, it is possible to test the first chip and the second chip while operating them independently. Further, since test probes or the like can be brought into contact with the external terminals of the first chip and the second chip from the same side, it is possible to simultaneously test the first chip and the second chip.

Abstract: A semiconductor device includes a pair of power chips, an IC chip, a plurality of leads one of which having a die pad on which the power chips are mounted and another one having a die attach portion on which the IC chip is mounted, a resin sheet firmly adhered to one side of the die pad, and a resin casing made by molding operation to encapsulate the power chips, the IC chip and the resin sheet by a resin in such a manner that one surface of the resin sheet opposite the die pad is exposed to the exterior of the resin casing. The resin casing has a groove formed in one surface opposite the exposed surface of the resin sheet, the groove extending parallel to the resin sheet and perpendicular to a runner through which the resin was supplied in the molding operation.

Abstract: The invention concerns a method for preparing a thin layer (28) or a chip to be transferred onto another substrate, this method including the realization, above the surface of said thin layer or said chip, of at least one layer, called adhesive layer (25), and of at least one layer, called first barrier layer (22), the adhesive layer being made of a material of which etching presents selectivity in relation to the material of the barrier layer.

Abstract: A method for wafer-to-wafer bonding of a sensor readout circuitry separately fabricated with a silicon substrate to a photodiode device made of non-silicon materials grown from a separate substrate. In preferred embodiments the non-silicon materials are epitaxially grown on a silicon wafer. The bonding technique of preferred embodiments of the present invention utilizes lithographically pre-fabricated metallic interconnects to connect each of a number of pixel circuits on a readout circuit wafer to each of a corresponding number of pixel photodiodes on a photodiode wafer. The metallic interconnects are extremely small (with widths of about 2 to 4 microns) compared to prior art bump bonds with the solder balls of diameter typically larger than 20 microns. The present invention also provides alignment techniques to assure proper alignment of the interconnects during the bonding step.

Abstract: Methods of fabricating of a light-emitting device are provided, the methods include forming a plurality of light-emitting units on a substrate, measuring light characteristics of the plurality of light-emitting units, respectively, depositing a phosphor layer on the plurality of light-emitting units using a printing method, and cutting the substrate to separate the plurality of light-emitting units into unit by unit. The phosphor layer is adjustably deposited according to the measured light characteristics of the plurality of light-emitting units.

Abstract: A mold structure for packaging LED chips includes a top mold and a bottom mold. The bottom mold is mated with the top mold. The bottom mold has a main flow channel, a plurality of receiving spaces formed beside the main flow channel, a plurality of secondary flow channels for respectively and transversely communicating the receiving spaces with each other, and a plurality of ejection pins penetrating through the bottom mold.

Abstract: An integrated component includes a semiconductor substrate; at least one interconnect applied on the semiconductor substrate; an insulating layer applied on the at least one interconnect; and at least one opening through the insulating layer which interrupts the at least one interconnect into a first section and a second section.

Abstract: A wafer containing a plurality of electro-optical devices, each device being enclosed in chamber that has a translucent cover. An X-Y matrix of pairs of interconnections on the wafer are connected to the circuitry of the electro-optical devices for addressing the electro-optical devices. The pairs of interconnections extend outside of the chambers enclosing the devices to testing areas on the periphery of the wafer. Testing is done by signals applied through the interconnections while simultaneously exposing the devices to light through the translucent covers.

Abstract: A method of manufacturing semiconductor device comprises placing multiple chips onto a carrier. An encapsulation material is applied to the multiple chips and the carrier for forming an encapsulation workpiece. The encapsulation workpiece having a first main face facing the carrier and a second main face opposite to the first main face. Further, marking elements are applied to the encapsulation workpiece relative to the multiple chips, the marking elements being detectable on the first main face and on the second main face.

Abstract: A vacuum package has a chamber in which pressure is reduced to less than the atmospheric pressure, a functional component sealed in the chamber, and a material forming at least a part of the chamber. The material has at least one through hole to evacuate the chamber. In a cross section perpendicular to the material taken along the through hole, an edge portion of the material forming the through hole has an obtuse angle. The through hole is sealed with a sealing material.

Abstract: A semiconductor component and method for producing. The semiconductor component includes a semiconductor device and a leadframe. A package layout is defined and the orientation of electrically conductive members with respect to the semiconductor device and inner contact areas of the leadframe is altered so as to maximize the interfacial bonding area. The constraints of the standard package dimensions and the component assembly method are taken into account.

Abstract: A method of testing a capacitive transducer circuit, for example a MEMS capacitive transducer, by applying a test signal via one or more capacitors provided in the transducer circuit.

Abstract: A semiconductor device system and a method for modifying a semiconductor device is disclosed. In one embodiment, a function provided by a circuit positioned on the semiconductor device is replaced, modified, and/or supplemented by a function provided by a circuit positioned on a further semiconductor device.

Abstract: Provided are a manufacturing method for obtaining a low-cost imaging device, and the low-cost imaging device manufactured by such method. The method for manufacturing the imaging device is provided with a step of integrally forming a plurality of imaging devices by using a plurality of imaging optical systems for guiding photographing object light and a plurality of imaging elements for photoelectrically converting the photographing object light, and a step of dividing the integrally formed imaging devices by cutting into individual imaging devices. In the step of integrally forming the imaging devices, a shape for positioning the integrally formed imaging devices is formed.

Abstract: An optical element mounting method includes: illuminating ultraviolet light onto a polymer optical waveguide device; under the ultraviolet light illumination, capturing, by an image pickup device, the polymer optical waveguide device including a light incident/exiting position of a waveguide core; and judging, from a difference between bright and dark in a captured image, that a portion brighter than other portions or a portion darker than other portions is the light incident/exiting position of the waveguide core.

Abstract: A method of manufacturing a semiconductor module is provided. A semiconductor package is formed, having one or more plate units which are bent by heat. The semiconductor package is aligned on a module substrate, and connection members are disposed between the semiconductor package and the module substrate. Heat is applied to the plate units and the connection members to extend a distance between the module substrate and the semiconductor package, and connection patterns are formed. The height of the connection patterns is larger than that of the connection members.

Abstract: In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not of the first plurality (hereinafter: “second plurality”). The second plurality has a start input and an end output. The start input of the second plurality is connected to the output of one selected input buffer of the input pad of the first plurality and the end output of the second plurality is also connected to the input of one selected output pad of the first plurality. The second plurality of input/output pads are tested through selected input pad and selected output pad of the first plurality without electrical probes making contact during the wafer sort. The present invention also relates to an integrated circuit die so fabricated as to facilitate testing.

Abstract: A method increases a reliability of packaged semiconductor integrated circuit dice by identifying one or more dice on a wafer having failed an electrical test. One or more failed dice are added to a character map. A first tier of buffer dice is added to the initial character map adjacent to each die on the character map. Both the failed dice and the first tier of buffer dice are indicated or marked, such as by inking, thereby indicating dice not requiring packaging. A wafer may include multiple die, with die corresponding to the die in the character map being marked. The marked die thus include die that have failed an electrical test plus die that may be likely to fail in the future due to their proximity to the failed die.

Abstract: Conductive ink is printed onto a wafer held on a vertically movable stage by using a squeegee to force the conductive ink through a stencil. The stencil is supported from below by a supporting member adjacent to the periphery of the stage. After the conductive ink has been printed through the stencil, pneumatic pressure is applied to the stencil from above, and the stage is lowered to separate the wafer from the stencil. The supporting member holds the stencil taut while the stage is being lowered, so that the stencil does not warp downward and the printed conductive ink leaves the stencil at substantially the same time at all points on the wafer surface, preventing the premature escape of air and loss of pneumatic pressure.

Abstract: A method of probing an electrical device using a membrane probing system having an improved contact. A membrane probe forms a contact having a ridge with a pair of inclined surfaces defining an acute angle such that, when pressed into an electrical pad of a device to be tested, the ridge penetrates into the electrical pad, shearing away any oxide on the surface of the pad. The device may then be tested.

Abstract: A three-dimensional (3D) chip is fabricated from components that have been cut out of a two-dimensional (2D) chip to create the layers of the 3D chip. By testing the 2D chip first, the layers of the 3D chip have been pre-tested, thus reducing testing and production costs.

Abstract: A semiconductor package includes a semiconductor die with a plurality of solder bumps formed on bump pads. A substrate has a plurality of contact pads each with an exposed sidewall. A solder resist is disposed opening over at least a portion of each contact pad. The solder bumps are reflowed to metallurgically and electrically connect to the contact pads. Each contact pad is sized according to a design rule defined by SRO+2*SRR?2X, where SRO is the solder resist opening, SRR is a solder registration for the manufacturing process, and X is a function of a thickness of the exposed sidewall of the contact pad. The value of X ranges from 5 to 20 microns. The solder bump wets the exposed sidewall of the contact pad and substantially fills an area adjacent to the exposed sidewall. The contact pad can be made circular, rectangular, or donut-shaped.

Abstract: A method for optimizing a solar cell manufacturing process is described. The method includes determining a reference finger spacing value and a reference bulk lifetime for the solar cell manufacturing process. The method also includes measuring an actual bulk lifetime of a wafer with an in-line measurement tool. The method further includes calculating an optimal finger spacing value with a computer coupled to the in-line measurement tool, the optimal finger spacing value being the product of the reference finger spacing value and a square root of the actual bulk lifetime divided by the square root of the reference bulk lifetime. The method further includes forming a junction on the wafer, and depositing a set of busbars and a set of fingers on the wafer with a metal deposition device, wherein a distance between a first finger and a second finger of the set of fingers is about the optimal finger spacing value.

Abstract: Methods and devices for multi-chip stacks are shown. A method is shown that assembles multiple chips into stacks by stacking wafers prior to dicing into individual chips. Methods shown provide removal of defective chips and their replacement during the assembly process to improve manufacturing yield.

Abstract: A method of producing an electronic connection device, including: a) formation, in a plane of a support substrate, of at least one first contact element and, in a direction approximately perpendicular to the plane, of at least one second contact element having a first end in electrical contact with the first contact element or elements and a second end, the second contact element or elements including one or more metal tracks standing up along the direction perpendicular to the surface of the substrate; b) then positioning at least one electrical or electronic component in contact with the first contact element or elements; and c) encapsulation of the component(s) and of the first and second contact elements, at least the second end or ends of the second contact element or elements being flush with the surface of the encapsulating material.

Abstract: A test device that makes a test of a circuit device including a plurality of modules being substitutable in terms of function for one another, and in which a function change can be made for assignment to each of the modules based on an incoming control signal. The test device includes: a control section that generates the control signal, without changing a function to be assigned to a whole of the modules, to make the function change for assignment to each of the modules at least in a group of the modules; and a determination section that detects whether the circuit device operates differently when the function change is made for assignment to the modules, and based on a detection result, determines whether or not at least the group of the modules includes a defective module.

Abstract: An integrated circuit (IC) includes at least a first complementary MOS (CMOS) circuit, the first CMOS circuit comprising one or more first n-channel MOS (NMOS) transistors and one or more first p-channel MOS (PMOS) transistors, where the first NMOS transistors and the first PMOS transistors are arranged in the first CMOS circuit to drive at least a first common node of the first CMOS circuit. An average of the effective gate channel lengths of the first NMOS transistors (first NMOS average length) is at least 2% greater than an average of the effective gate channel lengths of the first PMOS transistors (first PMOS average length).

Abstract: A method and apparatus for applying a test signal to a node of a signal path of an integrated circuit using a parasitic capacitance of the integrated circuit associated with the node. For example, a parasitic capacitance associated with a bond pad may be used to apply a test signal to a signal path. Alternatively, a parasitic capacitance associated with a shielding element may be used to apply a test signal to the signal path.

Abstract: An integrated circuit having a metal interconnect layer, and also having a conductive line and a boundary defined with a uniform distance from the conductive line that defines a “keep out” distance between the boundary and the conductive line. A set of first fill elements are uniformly arranged along the boundary outside of the “keep out” distance, and a set of second fill elements further from the conductive line than the first fill elements are arranged in a pattern that would be uniform, but for having some fill elements missing from the pattern.

Abstract: A light-emitting diode (LED) module and an LED packaging method. As the LED module is packaged under the consideration of candela distribution, each of the lead frames of the LED chips packaged in the LED module is bended for tilting the LED chips by different angles to exhibit various lighting effects. Meanwhile, in the LED packaging method, a plurality of LED chips can be loaded on board rapidly and aligned by one operation to result in less deviation in the candela distribution curve.

Abstract: A testing method for a silicon interposer employs a test probe and an electrically conductive glass handler. The silicon interposer includes multiple interconnects that extend between the opposed major surfaces of the interposer, namely from a test side of the interposer to a conductive glass handler side of the interposer. On the glass handler side, the interposer includes a layer of patterned insulative resist with open regions at some interconnects on the glass handler side and remaining resist regions at other interconnects on the glass handler side. The interposer may include a conductive adhesive layer that couples together interconnects at the open regions on the glass handler side. In this manner, a probe may send a test signal from a first interconnect at one location on the test side of the interposer, through the first interconnect, through the conductive adhesive, through a second interconnect to another probe on the test side of the interposer.

Abstract: Methods are disclosed including heating an optical element. An optical material is applied to the heated optical element to provide a conformal layer that is cured via the thermal energy in the heated optical element.

Abstract: In some embodiments, a temporary package for at-speed functional test of semiconductor chip, including high power chips, is presented. In this regard, a method is introduced including placing an integrated circuit die on a contactor layer, the contactor layer to electrically couple contacts on the integrated circuit die with contacts on a multi-layer substrate designed to be permanently attached with the integrated circuit die, placing an integrated heat spreader over the integrated circuit die, and bonding the integrated heat spreader with the substrate, the integrated heat spreader holding the integrated circuit die in place to form a temporary package. Other embodiments are also disclosed and claimed.

Abstract: An LED package structure with standby bonding pads for increasing wire-bonding yield includes a substrate unit, a light-emitting unit, a conductive wire unit and a package unit. The substrate unit has a substrate body and a plurality of positive pads and negative pads. The light-emitting unit has a plurality of LED chips. The positive electrode of each LED chip corresponds to at least two of the positive pads, and the negative electrode of each. LED chip corresponds to at least two of the negative pads. Every two wires of the conductive wire unit are respectively electrically connected between the positive electrode of each LED chip and one of the at least two positive pads and between the negative electrode of each LED chip and one of the at least two negative pads. The package unit has a translucent package resin body on the substrate body to cover the LED chips.

Abstract: The process begins with separate device wafers having complimentary chips. Thin metal capture pads, having a preferred thickness of about 10 microns so that substantial pressure may be applied during processing without damaging capture pads, are deposited on both device wafers, which are then tested and mapped for good chip sites. A handle wafer is attached to one device wafer, which can then be thinned to improve via etching and filling. Capture pads are removed and replaced after thinning. The device wafer with handle wafer is diced, and good chips with attached portions of the diced handle wafer are positioned and bonded to the good chip sites of the other device wafer, and the handle wafer portions are removed. The device wafer having known good 3-D chips then undergoes final processing.

Abstract: A semiconductor light emitting device can be configured to maintain high luminance and to suppress the possibility of the occurrence of wire breakage with high quality and reliability. A method for producing such a semiconductor light emitting device with a high process yield is also disclosed. The semiconductor light emitting device can include a sealing member into which a reflective filler can be mixed in such an amount (concentration) range that luminous flux with a predetermined amount can be maintained and the possibility of the occurrence of wire breakage can be lowered. Various sealing members containing a reflective filler with a plurality of concentrations within this range can be prepared in advance.

Abstract: A method of forming integrated circuits includes providing a wafer that includes a plurality of dies; aligning a first top die to a first bottom die in the wafer; recording a first destination position of the first top die after the first top die is aligned to the first bottom die; bonding the first top die onto the first bottom die; calculating a second destination position of a second top die using the first destination position; moving the second top die to the second destination position; and bonding the second top die onto a second bottom die without any additional alignment action.

Abstract: Disclosed are methods of manufacturing a flash memory device. The method can include performing a first test on memory banks of chips on a wafer to record an availability of the banks; performing an inking process on each of the chips according to a number of available banks in the chip; performing a sawing process to divide the chips mounted on the wafer; packaging the divided chips according to the number of available banks in the chip; and performing a verification test on the packaged chips.

Abstract: Typical testing of solder joints, (e.g. joints at printed circuit board pads) has not proven totally predictive of the ultimate performance of such joints. It has been found that this lack of reliability is, at least in part, due to the tendency during testing for these pads to lose adhesion to, or delaminate from, the underlying substrate. In contrast, such occurrence is not typical of phenomena induced during typical device usage. To remove this source of unreliability, a test structure is made together with the manufacturing device lot. The same pad processing is used and the pad size is substantially enlarged in the test structure. The test structure is employed to predict performance of devices in the lot and then the lot is processed accordingly.

Abstract: Various computer-implemented methods are provided. One method for sorting defects in a design pattern of a reticle includes searching for defects of interest in inspection data using priority information associated with individual defects in combination with one or more characteristics of a region proximate the individual defects. The priority information corresponds to modulation levels associated with the individual defects. The inspection data is generated by comparing images of the reticle generated for different values of a lithographic variable. The images include at least one reference image and at least one modulated image. A composite reference image can be generated from two or more reference images. The method also includes assigning one or more identifiers to the defects of interest. The identifier(s) may include, for example, a defect classification and/or an indicator identifying if the defects of interest are to be used for further processing.

Abstract: The reliabilities of a wiring substrate and a semiconductor apparatus are improved by reducing the internal stress caused by the difference of thermal expansion coefficients between a base substrate and a semiconductor chip. A wiring layer (5) is provided on one surface of a silicon base (3). An electrode as the uppermost layer of the wiring layer (5) is provided with an external bonding bump (7). A through-electrode (4) is formed in the base (3) for electrically connecting the wiring layer (5) and an electrode terminal. The electrode terminal on the chip mounting surface is bonded to an electrode terminal of a semiconductor chip (1) by an internal bonding bump (6). The thermal expansion coefficient of the silicon base (3) is equivalent to that of the semiconductor chip (1) and not more than that of the wiring layer (5).

Abstract: In a package mounting structure for mounting a package on a case, wherein the package internally incorporates at least one of a high-frequency transistor, MIC and MMIC used in the microwave to millimeter-wave band, and a base thereof is formed of metal and serves as ground, an electrically conductive sheet having excellent thermal conductivity and exhibiting restorability and having a size identical with that of the base of the package is laid on the case at a package-bearing location, the package and sheet are fastened together by two or more screws, and the sheet is mounted on the case while it is pressed by a pressing force of 10 N/cm2 or greater owing to fastening.

Abstract: Provided is a semiconductor device in which a connection between connection terminals and land of the semiconductor device can be checked with the semiconductor device kept in a sound condition, the connection not being allowed to be checked with a semiconductor chip. The semiconductor device of the present invention includes: a package substrate; a semiconductor chip mounted on the package substrate; a first land formed in a first principal surface of the package substrate; a second land formed in a second principal surface of the package substrate; first connection terminals connected to the second land and having the connection thereto not allowed to be checked with the semiconductor chip; a connection interconnection for connecting the first land and the second land; a second connection terminal formed in the second principal surface of the package substrate; and a branch interconnection for connecting the connection interconnection and the second connection terminal.

Abstract: A light emitting diode module is produced using at least one light emitting diode (LED) and at least two selectable components that form or are part of a light mixing chamber that surrounds the LEDs and includes an output port. A first selectable component has a first type of wavelength converting material with a first wavelength converting characteristic and a second selectable component has a second type of wavelength converting material with a different wavelength converting characteristic. The first and second wavelength converting characteristics alter the spectral power distribution of the light produced by the LED to produce light through the output port that has a color point that is a predetermined tolerance from a predetermined color point. Moreover, a set of LED modules may be produced such that each LED module has the same color point within a predetermined tolerance.

Abstract: A semiconductor package comprising a first semiconductor sub-package (40) having a connection face (44) with un-supported connectors (21) depending therefrom arranged to electrically connect a first semiconductor device contained therein to an external circuit, and at least one second semiconductor sub-package (42) also having a connection face (46) with un-supported connectors (25) depending therefrom arranged to electrically connect a second semiconductor device contained therein to an external circuit, the second semiconductor sub-package (42) also having an attachment face (48), on an opposite side thereof from the connection face (46); wherein the second semiconductor sub-package (42) is mounted on the first semiconductor sub-package (40) such that its attachment face (48) is coupled to the connection face (44) of the first semiconductor sub-package (40).

Abstract: Speed-up of a die bonding process for mounting a semiconductor chip onto a wiring substrate and improvement of a semiconductor package manufacturing yield are to be attained. A paste applicator comprises a drive section and a movable section supported by the drive section. The movable section includes a holder body adapted to move vertically along a main shaft with rotation of a motor in the drive section and a nozzle holder screwed to the holder body. A nozzle secured to a lower end of a syringe is screwed to the nozzle holder. Using a height sensor fixed to a main shaft support portion in the drive section, the paste applicator detects a positional deviation quantity with time of the movable section relative to the drive section and corrects a descent distance of the movable section on the basis of the positional deviation quantity.