Introduction Of Nondopant Into Semiconductor Layer Patents (Class 438/162)
  • Patent number: 5753541
    Abstract: A method for fabricating a silicon-germanium thin film field effect transistor (TFT) with a high carrier mobility and a high on/off ratio. An amorphous silicon layer, an amorphous germanium layer and a gate insulating film are successively layered on an insulating substrate on which a pair of source and drain electrodes are formed. Next, the amorphous silicon layer and the amorphous germanium layer are converted into polycrystalline layers by thermal annealing at a temperature higher than 600.degree. C. or laser annealing. Then, a gate electrode is formed on the gate insulating film.
    Type: Grant
    Filed: April 24, 1996
    Date of Patent: May 19, 1998
    Assignee: NEC Corporation
    Inventor: Kousaku Shimizu
  • Patent number: 5753542
    Abstract: A semiconductor material and a method for forming the same, said semiconductor material having produced by a process comprising melting a noncrystal semiconductor film containing therein carbon, nitrogen, and oxygen each at a concentration of 5.times.10.sup.19 atoms.cm.sup.-3 or lower, preferably 1.times.10.sup.19 atoms.cm.sup.-3 or lower, by irradiating a laser beam or a high intensity light equivalent to a laser beam to said noncrystal semiconductor film, and then recrystallizing the thus molten amorphous silicon film. The present invention provides thin film semiconductors having high mobility at an excellent reproducibility, said semiconductor materials being useful for fabricating thin film semiconductor devices such as thin film transistors improved in device characteristics.
    Type: Grant
    Filed: March 1, 1995
    Date of Patent: May 19, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hongyong Zhang, Naoto Kusumoto, Yasuhiko Takemura
  • Patent number: 5741732
    Abstract: A test apparatus for determining alignment of an implantation mask in the construction of thin film transistors (TFTs), a method for determining the alignment of an implantation mask employed in the construction of TFTs, and a method for constructing TFTs, employing a test implantation mask for the construction of an implantation region for multiple adjacent TFTs, are provided in which the test implantation mask has a sloped or stepped profile such that the masked area increases as the test implantation mask extends from one TFT to another TFT.
    Type: Grant
    Filed: May 3, 1995
    Date of Patent: April 21, 1998
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Victor Tikhonov
  • Patent number: 5736436
    Abstract: A gate electrode, a semiconductor thin film, a channel protecting film and a photoresist are accumulated on the overall surface of a transparent substrate on which a gate electrode and a gate line are formed. Ultraviolet rays are irradiated through the substrate so that the photoresist and the channel protecting film are self-aligned with respect to the gate electrode and the gate line. A mask is formed on the channel protecting film so as to extend in a direction perpendicular to the channel protecting film. The channel protecting film and the semiconductor thin film are etched using the mask. As a result, the semiconductor thin film and the channel protecting film are patterned without positional deviation so as to have the same width W. Therefore, it is possible to reduce the thin film transistor forming region and the number of steps of the manufacturing process.
    Type: Grant
    Filed: November 20, 1995
    Date of Patent: April 7, 1998
    Assignee: Casio Computer Co., Ltd.
    Inventors: Hiroshi Matsumoto, Haruo Wakai, Hiroyasu Joubettou
  • Patent number: 5736438
    Abstract: In a miniaturized complete CMOS SRAM of a TFT load type, a field effect thin-film transistor (TFT) can achieve stable reading and writing operation of a memory cell and can reduce power consumption thereof. The field effect thin-film transistor formed on an insulator includes an active layer and a gate electrode. The gate electrode is formed on a channel region of the active layer with a gate insulating film therebetween. The active layer is formed of a channel region and source/drain regions. The channel region is formed of a monocrystal silicon layer and does not includes a grain boundary. The source/drain regions is formed of a polysilicon layer. The channel region has a density of crystal defects of less than 10.sup.9 pieces/cm.sup.2. The thin film transistor shows an ON current of 0.25 .mu.A/.mu.m per channel width of 1 .mu.m and an OFF current of 15 fA/.mu.m. The thin-film transistor can be applied to a p-channel MOS transistor serving as a load transistor in a memory cell of a CMOS type SRAM.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 7, 1998
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Hisayuki Nishimura, Kazuyuki Sugahara, Shigenobu Maeda, Takashi Ipposhi, Yasuo Inoue, Toshiaki Iwamatsu, Mikio Ikeda, Tatsuya Kunikiyo, Junji Tateishi, Tadaharu Minato
  • Patent number: 5728610
    Abstract: A polycrystalline silicon film formed of an active layer of a thin film transistor is entirely hydrogenated by a low-temperature process, thereby lowering the resistance and relaxing the electric field in the vicinity of the drain to reduce the leakage current. A gate and an insulating film that covers it are formed on a substrate having an insulating surface. A hydrogenated polycrystalline silicon film is formed over the substrate, including the gate, with the insulating film interposed therebetween. A silicon oxide film pattern is formed on the polycrystalline silicon film directly above the gate. Source/drain regions are formed on the polycrystalline silicon film substantially at two external sides of the silicon oxide film pattern. The source/drain regions are formed from a hydrogen-containing amorphous silicon film, a conductive silicon film and a metal film, which are successively stacked on the polycrystalline silicon film.
    Type: Grant
    Filed: June 28, 1996
    Date of Patent: March 17, 1998
    Assignee: Sony Corporation
    Inventors: Dharam Pal Gosain, Jonathan Westwater, Setsuo Usui
  • Patent number: 5665611
    Abstract: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing.
    Type: Grant
    Filed: January 31, 1996
    Date of Patent: September 9, 1997
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Shubneesh Batra, Pierre C. Fazan
  • Patent number: 5661043
    Abstract: A method and apparatus for forming a buried insulator layer, typically a silicon dioxide layer, includes using plasma source ion implantation to uniformly implant ions into exposed regions of a semiconductor wafer. A silicon-on-insulator (SOI) structure is formed by an anneal step before fabricating an integrated circuit into the thin semiconductor layer above the buried insulator layer.
    Type: Grant
    Filed: July 25, 1994
    Date of Patent: August 26, 1997
    Inventors: Paul Rissman, James B. Kruger, J. Leon Shohet
  • Patent number: 5656511
    Abstract: A manufacturing method for a semiconductor device is preferably used for a semiconductor device using SOI (Silicon on Insulation) technology. At minimum, the method includes the following steps: the step of forming a gate electrode on a substrate by using a light-intercepting material; of forming a gate insulating film on the substrate including the gate electrode; of forming a semiconductor layer on the gate insulating film; and of forming a source region and a drain region by virtue of the fact that light, having a wavelength such that the light is absorbed into the semiconductor layer while not being absorbed into the substrate, is irradiated from the back of the substrate, before supplying impurities into the semiconductor layer.
    Type: Grant
    Filed: March 6, 1995
    Date of Patent: August 12, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hitoshi Shindo
  • Patent number: 5654203
    Abstract: In a method for crystallizing an amorphous silicon film by a heat treatment that is effected for a duration of about 4 hours at about 550.degree. C. using a catalyst element for accelerating the crystallization, the quantity of the catalyst element to be introduced into the amorphous silicon is precisely controlled. A resist mask 21 is formed on the surface of an amorphous silicon film 12 provided on a glass substrate 11, and an aqueous solution 14, e.g., an acetate solution, containing a catalyst element such as nickel at a concentration controlled in a range of from 10 to 200 ppm (need to be adjusted) is supplied dropwise thereto. After maintaining the state for a predetermined duration of time, the entire substrate is subjected to spin drying using a spinner 15. A thin film of crystalline silicon is finally obtained by applying heat treatment at 550.degree. C. for a duration of 4 hours.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 5, 1997
    Assignee: Semiconductor Energy Laboratory, Co., Ltd.
    Inventors: Hisashi Ohtani, Hiroki Adachi, Akiharu Miyanaga, Toru Takayama
  • Patent number: 5637515
    Abstract: A highly reliable thin-film transistor (TFT) having excellent characteristics. A silicon film is grown laterally by adding a metal element such as nickel to promote crystallization. A crystal grain boundary is formed parallel to a gate electrode and around the center of the gate electrode. Thus, the grain boundary does not exist around the interface between the drain and the channel formation region. At this interface, a large stress is induced by a large electric field. The concentration of the metal element is low around the interface between the drain and the channel formation region. Therefore, the leakage voltage is small. Also, when a reverse voltage is applied to the gate electrode, the leakage current is small.
    Type: Grant
    Filed: January 3, 1996
    Date of Patent: June 10, 1997
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 5629217
    Abstract: A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.
    Type: Grant
    Filed: October 6, 1994
    Date of Patent: May 13, 1997
    Assignee: Sony Corporation
    Inventors: Hiroyuki Miwa, Takayuki Gomi, Katsuyuki Kato
  • Patent number: 5627086
    Abstract: A thin-film semiconductor crystal is formed by depositing a thin film of amorphous silicon on a substrate, introducing ions selectively into a predetermined region of the thin film of amorphous silicon, and growing a single semiconductor crystal in the thin film of amorphous silicon by way of solid-phase crystal growth. A semiconductor device which employs the thin-film semiconductor crystal has a channel in the region where the ions are selectively introduced.
    Type: Grant
    Filed: May 11, 1995
    Date of Patent: May 6, 1997
    Assignee: Sony Corporation
    Inventor: Takashi Noguchi
  • Patent number: 5627085
    Abstract: The present invention improves a current--voltage characteristic by perfectly eliminating defects in the polycrystal silicon layer of TFT by hydrogenation. In the first process, hydrogen is doped into the polycrystal silicon layer 16 of TFT 1 by the hydrogen plasma doping method to eliminate a greater part of the defects in the polycrystal silicon layer 16. Thereafter, in the second process, after an amorphous silicon nitride film 23 including hydrogen is formed on the polycrystal silicon layer 16 or on the stopper layer 17 provided on the polycrystal silicon layer 16, hydrogen is released from the amorphous silicon nitride film 23 including hydrogen by the annealing process and such released hydrogen is then diffused into the polycrystal silicon layer 16 in order to eliminate remaining defects in the polycrystal silicon layer 16.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: May 6, 1997
    Assignee: Sony Corporation
    Inventors: Dharam P. Gosain, Jonathan Westwater, Setsuo Usui
  • Patent number: 5620906
    Abstract: In producing a semiconductor device such as a thin film transistor (TFT), a silicon semiconductor film is formed on a substrate having an insulating surface, such as a glass substrate, and then a silicon nitride film is formed on the silicon semiconductor film. After that, a hydrogen ion, fluorine ion, or chlorine ion is introduced into the silicon semiconductor film through the silicon nitride film, and then the silicon semiconductor film into which an ion is introduced is heated in an atmosphere containing hydrogen, fluorine, chlorine or these mixture, to neutralize dangling bonds in the silicon semiconductor film and reduce levels in the silicon semiconductor film.
    Type: Grant
    Filed: February 28, 1995
    Date of Patent: April 15, 1997
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Naoaki Yamaguchi, Hongyong Zhang, Satoshi Teramoto, Hideto Ohnuma