Abstract: In a semiconductor device and method for manufacturing the same, a buried insulating layer is formed on a semiconductor substrate, multiple depletion regions of a first conductivity type are formed on the buried insulating layer and separated from one another, a field oxide layer is formed among the depletion regions of the buried insulating layer, a gate oxide layer is formed on the depletion regions, a gate is formed on the gate oxide layer, impurity regions that are heavily doped with impurities of a second conductivity type is formed in the depletion regions on both sides of the gate to define a source and drain, and a counter doping layer that is lightly doped with impurities of the second conductivity type is formed under the channel defined by a portion of the depletion regions positioned between the impurity regions.

Abstract: A method of fabricating a thin film transistor with a silicon film crystallized by sequential lateral solidification including depositing an amorphous silicon film on an insulating substrate, selectively doping the amorphous silicon film with impuities, crystalizing the amorphous silicon film doped selectively with the impurities by sequential lateral solidification, forming an active layer of which doped portions become source and drain regions by patterning the silicon film crystalized by sequential lateral solidification, and forming a gate insulating layer and a gate electrode on the active layer.

Abstract: A method for manufacturing a semiconductor device such as a thin film transistor using a crystal silicon film is provided. The crystal silicon film is obtained by selectively forming films, particles or clusters containing nickel, iron, cobalt, ruthenium, rhodium, parad.ium, osmium, iridium, platinum, scandium, titanium, vanadium, chrome, manganese, copper, zinc, gold, silver or silicide thereof in a form of island, line, stripe, dot or film on or under an amorphous silicon film and using them as a starting point, by advancing its crystallization by annealing at a temperature lower than a normal crystallization temperature of an amorphous silicon. A transistor whose leak current is low and a transistor in which a mobility is high are obtained in the same time in structuring a dynamic circuit having a thin film transistor by selectively forming a cover film on a semiconductor layer which is to become an active layer of the transistor and by thermally crystallizing it thereafter.

Abstract: The object of the present invention is to form a low-concentration impurity region with good accuracy in a top gate type TFT. Phosphorus is added to a semiconductor layer by using a pattern made of a conductive film as a mask to form an N-type impurity region in a self-alignment manner. A positive photoresist is applied to a substrate so as to cover the pattern and then is exposed to light applied to the back of the substrate and then is developed, whereby a photoresist 110 is formed. The pattern is etched by using the photoresist pattern as an etching mask to form a gate electrode. A channel forming region, a source region, a drain region, and low-concentration impurity regions, are formed in the semiconductor layer in a self-alignment manner by using the gate electrode as a doping mask.

Abstract: A multi-chamber system for providing a process of a high degree of cleanliness in fabricating semiconductor devices such as semiconductor integrated circuits. The system comprises a plurality of vacuum apparatus (e.g., a film formation apparatus, an etching apparatus, a thermal processing apparatus, and a preliminary chamber) for fabrication of semiconductor devices. At least one these vacuum apparatuses is a laser.

Abstract: A method for manufacturing a semiconductor device such as a thin film transistor using a crystal silicon film is provided. The crystal silicon film is obtained by selectively forming films, particles or clusters containing nickel, iron, cobalt, ruthenium, rhodium, paradium, osmium, iridium, platinum, scandium, titanium, vanadium, chrome, manganese, copper, zinc, gold, silver or silicide thereof in a form of island, line, stripe, dot or film on or under an amorphous silicon film and using them as a starting point, by advancing its crystallization by annealing at a temperature lower than a normal crystallization temperature of an amorphous silicon. A transistor whose leak current is low and a transistor in which a mobility is high are obtained in the same time in structuring a dynamic circuit having a thin film transistor by selectively forming a cover film on a semiconductor layer which is to become an active layer of the transistor and by thermally crystallizing it thereafter.

Abstract: A crystalline silicon film is formed on a substrate containing an OH group at 50-2,000 ppm and chlorine at 10-1,000 ppm at a process temperature range of 640°-980° C. by utilizing nickel. A thermal oxidation film is formed on the crystalline silicon film at a process temperature within the above range in an atmosphere containing HC1. By virtue of the action of chlorine, nickel is gettered into the thermal oxidation film. By removing the thermal oxidation film, a crystallline silicon film is obtained which has superior crystallinity and a low nickel concentration.

Abstract: A method for forming low defect density epitaxial layers on lattice-mismatched substrates includes confining dislocations through interactions between the dislocations and the stress field in the epitaxial layer. This method is applicable to any heteroepitaxial material systems with any degree of lattice mismatch. The method includes choosing the desired epilayer and the top substrate layer for epitaxial growth, determining the lattice constant and thermal expansion coefficient of the final epilayer and the top substrate layer, bonding an additional substrate layer under the top substrate layer to form a composite substrate so that the desired epilayer has negative (positive) or zero thermal mismatch to the composite substrate if the lattice mismatch between the epilayer and the top substrate layer is positive (negative), and choosing a buffer layer to be deposited before the desired epilayer which is lattice matched to the epilayer.

Abstract: There is provided a semiconductor manufacturing method capable of sufficiently reducing catalytic element in a crystalline silicon film and also increasing the area of the crystalline silicon film to be left on the substrate. A catalytic element for accelerating the crystallization is introduced into an amorphous silicon film on a substrate, and a first heat treatment is performed to crystallize the amorphous silicon film into a crystalline silicon film. A mask layer is provided on the surface of the crystalline silicon film, the mask layer having an opening passing thicknesswise through the mask layer. Further thereon, a sacrifice film is formed so as to continuously cover the surface of the mask layer and an opening-correspondent portion of the crystalline silicon film. A getter element for gettering the catalytic element is introduced into the sacrifice film and the opening-correspondent portion of the crystalline silicon film.

Abstract: The present invention relates to a method of crystallizing an amorphous silicon layer which is carried out by depositing a crystallization-inducing substance on an amorphous silicon layer on crystallizing the amorphous silicon layer by metal-induced crystallization whereby speed of crystallizing silicon is increased and metal contamination by MIC is reduced. The present invention includes the steps of depositing a crystallizing-induced layer of an induced substance for crystallizing silicon on an amorphous silicon layer wherein the crystallizing induced layer is formed to the thickness under 0.03 angstroms, and treating thermally the amorphous silicon layer on which the crystallizing-induced layer is deposited.

Abstract: A method for manufacturing an organic EL display device is provided, capable of improving an opening ratio and providing narrower pitches for narrowing non-lighting portion between pixels, and, at the same time, capable of eliminating short-circuiting between display pixels for eliminating cross-talk and non-lighting pixels. In the deposition process of the cathode 6, the incident angle of the deposition material onto the substrate is optimized by optionally changing parameters such as a distance between the substrate 1 and the mask 11 and a distance between the substrate and the point deposition source 13. Thus, deposition material from a plurality of deposition sources impinges onto the substrate surface obliquely passing at a different incident angles though opening (slits 11a) of the mask 11, so that the width 10 of the electrode pattern 6 becomes broader than the width of the slit by superposition of the deposition material passing through the slits at different incident angles.

Abstract: This invention discloses a method of manufacturing a semiconductor device which comprises the steps of: forming gate electrodes on a semiconductor substrate having a cell region and a peripheral region; forming spacers at both side walls of the gate electrodes; implanting impurity into the semiconductor substrate of the peripheral region; forming a growth suppression layer on gate electrodes and surface of the semiconductor substrate in the peripheral region; forming doped epitaxial layers over predetermined portions of the semiconductor substrate in the cell region so that the impurity implanted into the semiconductor substrate in the peripheral region is diffused in the semiconductor substrate to form junction regions and impurity existing in the doped epitaxial layers of the cell region is diffused into the semiconductor substrate; and removing the growth suppression layer.

Abstract: The present invention discloses a method of manufacturing a thin film transistor, including: depositing an amorphous silicon layer, an insulating layer, and a gate metal layer on a substrate sequentially; patterning the insulating layer and the gate metal layer to form a gate insulating layer and a gate electrode; treating an impurity and a catalyst metal on the amorphous silicon layer using the gate electrode as a mask; and applying a DC voltage to both terminals of the amorphous silicon layer to form a polysilicon layer, the polysilicon layer having source and drain regions and an active area.

Abstract: A method of crystallizing a silicon film and a method of manufacturing a liquid crystal display apparatus which uses the Joule heat of a heat generating conductive layer to increase the temperature of a silicon film for expediting silicon crystallization includes forming an amorphous silicon film on an insulating substrate, forming a heat generating conductive layer over the amorphous silicon film, and applying a voltage to the heat generating conductive layer wherein electric current flows through the heat generating conductive layer.

Abstract: In a crystallization process of an amorphous semiconductor film, a first crystalline semiconductor film having crystalline regions, and dotted with amorphous regions within the crystalline regions, is obtained by performing heat treatment processing after introducing a metallic element which promotes crystallization on the amorphous semiconductor film. The amorphous regions are kept within a predetermined range by regulating the heat treatment conditions at this point. Laser annealing is performed on the first crystalline semiconductor film, to form a second crystalline semiconductor film. Electrical characteristics for a TFT manufactured based on the second crystalline semiconductor film can be obtained having less dispersion.

Abstract: A method and semiconductor structure are provided for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors. A bulk silicon substrate is provided. A deep ion implant layer is implanted to reside below an oxide insulator. An oxygen implant layer is implanted while applying a mask to block the oxygen implant layer in selected regions. The selected regions provide for body contact for the SOI transistors. Holes are formed extending into the deep ion implant layer and the bulk silicon substrate. The holes are filled with an electrically conductive material to create stud contacts to the deep ion implant layer and the bulk silicon substrate.

Abstract: A method of fabricating a TFT includes a step of forming an impurity region for a source and a drain by simultaneously implanting and activating impurity ions. More particularly, the present invention includes the steps of forming a gate insulating layer and a gate on a predetermined and selected portion of an active layer, forming an excited region in the exposed portion of the active layer by implanting hydrogen ions to the active layer by using the gate as a mask, and forming an impurity region by implanting impurity ions heavily to the excited region which remains in an excited state.

Abstract: A thin film transistor including a gate, a source, and a drain is formed on a substrate. An insulating film containing H2O is formed on the thin film transistor. For example, spin-on glass (SOG) containing H2O may be used. H2O contained in the insulating film is diffused through the thin film transistor by performing thermal processing on the insulating film. Trapping centers in the polysilicon may therefore be reduced.

Abstract: The object of the present invention is to form a low-concentration impurity region with good accuracy in a top gate type TFT. Phosphorus is added to a semiconductor layer by using a pattern made of a conductive film as a mask to form an N-type impurity region in a self-alignment manner. A positive photoresist is applied to a substrate so as to cover the pattern and then is exposed to light applied to the back of the substrate and then is developed, whereby a photoresist 110 is formed. The pattern is etched by using the photoresist pattern as an etching mask to form a gate electrode. A channel forming region, a source region, a drain region, and low-concentration impurity regions, are formed in the semiconductor layer in a self-alignment manner by using the gate electrode as a doping mask.

Abstract: The present invention discloses a method of manufacturing a thin film transistor, including: preparing a process chamber having a stage; providing a substrate on the stage of the process chamber; injecting a first mixed gas of NH3, N2 and SiH4 into the process chamber; forming a plasma in the process chamber and forming a silicon nitride film (SiNx) on the substrate; injecting a second mixed gas of H2 and SiH4 into the process chamber while removing the first mixed gas in the plasma state; forming a pure amorphous silicon film (a-Si:H) on the silicon nitride film using the second mixed gas; injecting a third mixed gas of H2, SiH4 and PH3 into the process chamber while removing the second mixed gas in the plasma state; and forming a doped amorphous silicon film (n+a-Si:H) on the silicon nitride film using the second mixed gas.

Abstract: A semiconductor device is fabricated by implanting into a semiconductor substrate non-doping ions at a tilt angle of at least about 10° to laterally extend preamorphization of the substrate portion and then implanting into the substrate dopants for providing source/drain extensions or halo doping or both.

Abstract: A method for making a ULSI MOSFET using silicon on insulator (SOI) principles includes masking regions of an amorphous silicon film on a substrate and exposing intended active regions. Laser energy is directed against the intended active regions to anneal these regions without annealing the masked regions, thereby increasing production throughput and decreasing defect density.

Abstract: A thin film transistor wherein at least one of (1) a gate electrode and/or a scanning line therefor and (2) source/drain electrode and/or signal lines therefor comprises a laminated wiring structure in which a main wiring layer formed of a metal selected from Al and Cu or an alloy based on the metal is sandwiched between an underlying wiring layer and an overlaying wiring layer, the underlying and overlaying wiring layers being formed of a material based on a metal or alloy of metals and containing nitrogen, the metal being selected from Ti, Mo, W, Cr, Al and Cu, and the materials used in the underlying and overlaying wiring layers being different from each other. Alternatively, the underlying and overlaying wiring layers are formed of a material based on the same metal or alloy of metals and containing nitrogen, the metal being selected from Ti, Mo, W, Cr, Al and Cu, and contents of nitrogen in the underlying and overlaying wiring layers being different from each other.

Abstract: According to a method of manufacturing a thin film transistor (TFT), amorphous silicon is formed by ion-implanting either silicon or nitrogen into a region of polysilicon while a region located at the sidewall of a gate electrode is selectively left using the stepped portion of the gate electrode. Then, a heat treatment is applied to convert the amorphous silicon into polysilicon with the remaining polysilicon as a seed crystal. As a result, polysilicon having crystal grains of great grain size can be formed in uniform. Thus, the electric characteristics of a TFT can be improved with no difference in the electric characteristics between each TFT.

Abstract: A display unit capable of inhibiting moisture and gas from penetrating into a liquid crystal layer and an alignment layer also after formation of a display electrode and suppressing decomposition of a material forming the display electrode is obtained. In this display unit, an impurity-introduced layer containing an impurity element having high electronegativity is formed on the surface of an insulator film and the surface of the display electrode after formation of the display electrode. Thus, the insulator film and the display electrode are improved in effects of preventing transmission of moisture and gas also after formation of the display electrode. The impurity-introduced layer formed on the surface of the display electrode stabilizes the surface of an ITO film forming the display electrode, thereby suppressing decomposition of the ITO film.

Abstract: A method for crystallizing an amorphous layer into a polycrystalline layer. The method uses a substrate under the amorphous layer and a nickel film on the amorphous layer, which are subjected to a heat treatment. The nickel film is formed by a coating step that uses a nickel-containing solution. Alternatively, a nickel and gold, or a nickel and palladium, solution can be used. The method eliminates contamination with metal in the polycrystalline silicon layer and reduces its growth temperature.

Abstract: On a transparent substrate to which a gate electrode is arranged, a silicon nitride film and a silicon oxide film to be gate insulating films are deposited, and further, a polycrystalline silicon film as a semiconductor film to be an active region is formed. On the polycrystalline silicon film corresponding to the gate electrode, a stopper is arranged, and a silicon oxide film and a silicon nitride film to be an interlayer insulating films are deposited so as to cover this stopper. The film thickness T0 of the stopper is set in a range of 800 angstroms to 1200 angstroms.

Abstract: A thin film transistor includes: a) a thin film transistor layer comprising a source region, a channel region and a drain region; the thin film transistor layer further comprising a drain offset region positioned between the drain region and the channel region; b) the channel region being substantially polycrystalline and having a first average crystalline grain size; and c) the drain offset region being substantially polycrystalline and having a second average crystalline grain size, the second average crystalline grain size being larger than the first average crystalline grain size. A method for forming such a construction using polycrystalline materials, preferably polysilicon, and an amorphizing silicon implant with subsequent recrystallization is also disclosed.

Abstract: Concentration of metal element which promotes crystallization of silicon and which exists within a crystal silicon film obtained by utilizing the metal element is reduced. A first heat treatment for crystallization is implemented after introducing nickel to an amorphous silicon film. Then, after obtaining the crystal silicon film, another heat treatment is implemented within an oxidizing atmosphere at a temperature higher than that of the previous heat treatment. A thermal oxide film is formed in this step. At this time, gettering of the nickel element into the thermal oxide film takes place. Then, the thermal oxide film is removed. Thereby, a crystal silicon film having low concentration of the metal element and a high crystalinity can be obtained.

Abstract: A nitrogen implanted region formed substantially below and substantially adjacent to a source/drain region of an IGFET forms a liner to retard the diffusion of the source/drain dopant atoms during a subsequent heat treatment operation such as an annealing step. The nitrogen liner may be formed by implantation of nitrogen to a given depth before the implantation of source/drain dopant to a lesser depth. Nitrogen may also be introduced into regions of the IGFET channel region beneath the gate electrode for retarding subsequent lateral diffusion of the source/drain dopant. Such nitrogen introduction may be accomplished using one or more angled implantation steps, or may be accomplished by annealing an implanted nitrogen layer formed using a perpendicular implant aligned to the gate electrode. The liner may be formed on the drain side of the IGFET or on both source and drain side, and may be formed under a lightly-doped region or under a heavily-doped region of the drain and/or source.

Abstract: There is provided a field effect transistor including (a) an amorphous semiconductor layer made of amorphous silicon hydride containing impurities doped therein, (b) a semiconductor layer made of single crystal silicon having electron affinity greater than that of the amorphous silicon hydride, formed on the amorphous semiconductor layer, (c) a gate insulating film formed on the semiconductor layer, and (d) a gate electrode formed on the gate insulating film. The amorphous semiconductor layer and the semiconductor layer cooperate with each other to thereby form a potential well at a junction therebetween. The above mentioned field effect transistor utilizes a difference in electron affinity between the amorphous semiconductor layer and the semiconductor layer to thereby make it possible to operate at a higher speed because carriers are not influenced by scattering of doped ions.

Abstract: A thin film transistor includes: a) a thin film transistor layer comprising a source region, a channel region and a drain region; the thin film transistor layer further comprising a drain offset region positioned between the drain region and the channel region; b) the channel region being substantially polycrystalline and having a first average crystalline grain size; and c) the drain offset region being substantially polycrystalline and having a second average crystalline grain size, the second average crystalline grain size being larger than the first average crystalline grain size. A method for forming such a construction using polycrystalline materials, preferably polysilicon, and an amorphizing silicon implant with subsequent recrystallization is also disclosed.

Abstract: Barrier layers of an insulating material block the diffusion of the halo ions to an edge portion of the gate electrode, the halo ions being injected for improving short channel characteristic. The barrier layers prevent an increase of a threshold voltage of the device and improve electrical characteristics of the device.

Abstract: A monolithic type active matrix semiconductor device comprises a substrate having an insulating surface, a first plurality of thin film transistors formed on the substrate, each having a first channel region comprising an amorphous silicon semiconductor film, and a second plurality of thin film transistors, each having a second channel region comprising a crystalline semiconductor film. The crystalline semiconductor film of the second plurality of thin film transistors has a substantially single crystalline structure (mono-domain structure) and is doped with a recombination center neutralizer at a concentration of 1×1016 to 1×1020 atoms/cm3. The crystalline semiconductor film of the second plurality of thin film transistors contains a catalyst element which is capable of promoting crystallization of silicon.

Abstract: A method for fabricating a CMOS device on a SOI, comprising the steps of: providing a SOI wafer having a stack structure of a base substrate, a buried oxide layer and a semiconductor layer; forming a field oxide film in the semiconductor layer to define an active region in which a PMOS device and a NMOS device are to be formed in the semiconductor layer of the SOI wafer, wherein the field oxide film is formed by performing thermal oxidation process so as to apply a compressive stress to the semiconductor layer that the PMOS device is to be formed; and forming the PMOS device and NMOS device in the active region defined by the field oxide film.

Abstract: The semiconductor device includes and the method for fabricating the same forms a damaged region under a gate electrode to improve device performance and simplify the process. The semiconductor device includes a substrate in which a buried insulating layer is formed; device isolating layers buried in first predetermined areas of the substrate to contact with the buried insulating layer; a gate electrode formed over a second predetermined area of the substrate; sidewall spacers formed on both sides of the gate electrode; source and drain regions at both sides of the gate electrode; and the damaged region at boundary of the buried insulating layer under the gate electrode.

Abstract: A method of fabricating a thin film transistor having a vertical offset layer which prevents the damage on an active layer due to the etching plasma by preserving the vertical offset layer during an etching process for separating an ohmic contact layer.

Abstract: A TFT having stable characteristics is obtained by using a crystal silicon film obtained by crystallizing an amorphous silicon film by using nickel. Phosphorus ions are implanted to regions 111 and 112 by using a mask 109. Then, a heat treatment is performed to getter nickel existing in a region 113 to the regions 111 and 112. Then, the mask 109 is side-etched to obtain a pattern 115. Then, the regions 111 and 112 are removed by utilizing the pattern 115 and to pattern the region 113. Thus, a region 116 from which nickel element has been removed is obtained. The TFT is fabricated by using the region 116 as an active layer.

Abstract: A silicon film is crystallized in a predetermined direction by selectively adding a metal element having a catalytic action for crystallizing an amorphous silicon and annealing. In manufacturing TFT using the crystallized silicon film, TFT provided such that the crystallization direction is roughly parallel to a current-flow between a source and a drain, and TFT provided such that the crystallization direction is roughly vertical to a current-flow between a source and a drain are manufactured. Therefore, TFT capable of conducting a high speed operation and TFT having a low leak current are formed on the same substrate.

Abstract: In accordance with the present invention, an amorphous layer is formed in a crystalline substrate (e.g., the channel region of a MOSFET transistor) by, for example, implanting ions of an inert specie such as germanium. A dopant is implanted so that it overlaps with the amorphous layer. Subsequently, low temperature recrystallization of the amorphous layer leads to an abrupt retrograded layer of active dopant in the channel region of the MOSFET. This retrograded dopant layer could be formed before or after the formation of the gate electrode.

Abstract: In an electronic device, such as an active matrix display device or the like, comprising a top gate amorphous silicon thin film transistor (10) in which one or both of the source and drain electrodes (15, 16) is of transparent conductive material such as ITO, the PECVD deposited semiconductor layer (18) extending over and between the source and drain electrodes of the TFT is formed as first and second sub-layers (18A, 18B), using different source gas compositions. A noble inert gas such as helium is used as dilutant in forming the first sub-layer adjacent the source and drain electrodes to avoid reduction problems while hydrogen is used as the dilutant in forming the second sub-layer to achieve high stability and mobility characteristics in the completed transistor.

Abstract: Concentration of metal element which promotes crystallization of silicon and which exists within a crystalline silicon film obtained by utilizing the metal element is reduced. A first heat treatment for crystallization is performed after introducing nickel to an amorphous silicon film 103. Then, laser light is irradiated to diffuse nickel element which is concentrated locally. After that, another heat treatment is performed within an oxidizing atmosphere at a temperature higher than that of the previous heat treatment. At this time, HCl or the like is added to the atmosphere. A thermal oxide film 106 is formed in this step. At this time, gettering of the nickel element into the thermal oxide film 106 takes place. Then, the thermal oxide film 106 is removed. Thereby, a crystalline silicon film 107 having low concentration of the metal element and a high crystallinity can be obtained.

Abstract: This invention provides a semiconductor device with a SOI structure and a method of manufacturing the same, preventing deterioration in and making improvement in device characteristics. Nitrogen ion implantation into NMOS and PMOS regions (NR, PR) with resists (22b) and (22c) as masks, respectively, introduces nitrogen ions into channel doped layers (31). The subsequent thermal treatment provides a structure with the channel doped layers (31) containing nitrogen having a prescribed concentration distribution in the depth direction.

Abstract: A method for forming a silicon island used for forming a TFT or thin film diode comprises the step of pattering a silicon film with a photoresist mask. In order to prevent the contamination of the semiconductor film due to the photoresist material, a protective film such as silicon oxide is interposed between the semiconductor film and the photoresist film. Also, the protective film is preferably formed by thermal annealing or light annealing in an oxidizing atmosphere.

Abstract: A low temperature process for fabricating a high-performance and reliable semiconductor device in high yield, comprising forming a silicon oxide film as a gate insulator by chemical vapor deposition using TEOS as a starting material under an oxygen, ozone, or a nitrogen oxide atmosphere on a semiconductor coating having provided on an insulator substrate; and irradiating a pulsed laser beam or an intense light thereto to remove clusters of such as carbon and hydrocarbon to thereby eliminate trap centers from the silicon oxide film. Also claimed is a process comprising implanting nitrogen ions into a silicon oxide film and annealing the film thereafter using an infrared light, to thereby obtain a silicon oxynitride film as a gate insulator having a densified film structure, a high dielectric constant, and an improved withstand voltage.

Abstract: To provide a method of removing a catalyst element from a crystalline silicon film obtained by solid phase growth using the catalyst element promoting crystallization, phosphorus is implanted selectively to the crystalline silicon film having the catalyst element whereby a portion of the silicon film implanted with phosphorus is made amorphous, and when a thermal annealing treatment is performed and the silicon film is heated, the catalyst element is moved to an amorphous portion implanted with phosphorus having large gettering capacity by which the concentration of the catalyst element in the silicon film is lowered and a semiconductor device is fabricated by using the silicon film.

Abstract: In a method of manufacturing a semiconductor device, nickel elements 404 is held on a surface of an amorphous silicon film 403 in a contact manner, and then transformed into a crystalline silicon film 405 through a heat treatment. Thereafter a mask 406 is formed to conduct doping with phosphorus, In this process, a region 407 is doped with phosphorus. Then, the region 407 which has been doped with phosphorus is activated by the irradiation of a laser beam or an intense light. Then, a heat treatment is conducted on the layer again to getter nickel in the region 407. Subsequently, the region 407 into which nickel is concentrated is removed so nickel is gettered, to obtain a region 408 having still higher crystallinity.

Abstract: The present invention provide a semiconductor device having a first insulating layer provided in contact with a side of an active layer in the direction of thickness thereof, a second insulating layer provided in contact with the other side of the active layer in the direction of the thickness thereof, a first gate electrode for applying a predetermined voltage to the active layer through the first insulating layer, and a second gate electrode for applying a predetermined voltage to the active layer through the second insulating layer. In the semiconductor device, a leak current between the drain and the source is suppressed, thereby obtaining a large driving current.

Abstract: An ohmic layer of CMOS TFT is activated at temperature less than 550.degree. C. by doping N-type and P-type dopants into polycrystal semiconductor to form CMOS thin film transistor and then implanting hydrogen ions into CMOS thin film transistor into which the N-type ions and the P-type ions are doped. The hydrogen ions are generated from a plasma which is produced from a hydrogen containing gas(e.g., phosphine or diborane) and the implantation of the hydrogen ions is carried out by a magnetic mass spectroscopy or an ion doping apparatus in the same chamber where the doping of the N-type ions and the P-type ions is carried out.

Abstract: In a method of manufacturing a semiconductor device having an LDD structure, source gases for generating plural types of impurity ions exhibiting different molecular weights and different projected ranges in a target during impurity implantation are supplied to a plasma space, ionized, accelerated with a voltage, and implanted in a semiconductor region on the target substrate. In the case of manufacturing a top-gate transistor, a gate electrode on the semiconductor region has a sufficient thickness to serve as a mask. In the case of manufacturing a bottom-gate transistor, a mask and a resistor are used. An implantation angle is set to an optimum value as desired. Thereafter, the impurity is activated as desired. Thus, the semiconductor device having the LDD structure is manufactured by a single step of impurity implantation.