Abstract: Methods of fabricating of a light-emitting device are provided, the methods include forming a plurality of light-emitting units on a substrate, measuring light characteristics of the plurality of light-emitting units, respectively, depositing a phosphor layer on the plurality of light-emitting units using a printing method, and cutting the substrate to separate the plurality of light-emitting units into unit by unit. The phosphor layer is adjustably deposited according to the measured light characteristics of the plurality of light-emitting units.

Abstract: The present invention is a method for evaluating a silicon wafer by measuring, after fabricating a MOS capacitor by forming an insulator film and one or more electrodes sequentially on a silicon wafer, a dielectric breakdown characteristic of the insulator film by applying an electric field from the electrodes thus formed to the insulator film, the method in which the silicon wafer is evaluated at least by setting an area occupied by all the electrodes thus formed to 5% or more of an area of a front surface of the silicon wafer when the one or more electrodes are formed. This provides an evaluation method that can detect a defect by a simple method such as the TDDB method with the same high degree of precision as that of the DSOD method.

Abstract: A metrology system for gauging and spatially mapping a semiconductor material on a substrate can be used in controlling deposition and thermal activation processes.

Abstract: Projection systems and methods with mechanically decoupled metrology plates according to embodiments of the present invention can be used to characterize and compensate for misalignment and aberration in production images due to thermal and mechanical effects. Sensors on the metrology plate measure the position of the metrology plate relative to the image and to the substrate during exposure of the substrate to the production image. Data from the sensors are used to adjust the projection optics and/or substrate dynamically to correct or compensate for alignment errors and aberration-induced errors. Compared to prior art systems and methods, the projection systems and methods described herein offer greater design flexibility and relaxed constraints on mechanical stability and thermally induced expansion. In addition, decoupled metrology plates can be used to align two or more objectives simultaneously and independently.

Abstract: A semiconductor device and a method of manufacturing are provided. In some embodiments, a backside annealing process such that a first heat source is placed along a backside of the substrate. In other embodiments, the first heat source is used in combination with an anti-reflection dielectric (ARD) layer is deposited over the substrate. In yet other embodiments, a second heat source is placed along a front side of the substrate in addition to the first heat source placed on the backside of the substrate. In yet other embodiments, a heat shield may be placed between the substrate and the second heat source on the front side of the substrate. In yet further embodiments, a single heat source may be used on the front side of the substrate in combination with the ARD layer. A reflectivity scan may be performed to determine which anneal stage (RTA or MSA or both) to place thermal leveling solution.

Abstract: The present disclosure relates to methods for performing wafer-level measurement and wafer-level binning of LED devices. The present disclosure also relates to methods for reducing thermal resistance of LED devices. The methods include growing epitaxial layers consisting of an n-doped layer, an active layer, and a p-doped layer on a wafer of a growth substrate. The method further includes forming p-contact and n-contact to the p-doped layer and the n-doped layer, respectively. The method further includes performing a wafer-level measurement of the LED by supplying power to the LED through the n-contact and the p-contact. The method further includes dicing the wafer to generate diced LED dies, bonding the diced LED dies to a chip substrate, and removing the growth substrate from the diced LED dies.

Abstract: A component for a light-emitting device includes a fluorescent layer that is capable of emitting fluorescent light and a housing that is connected to the fluorescent layer for housing a light-emitting diode.

Abstract: Projection systems and methods with mechanically decoupled metrology plates according to embodiments of the present invention can be used to characterize and compensate for misalignment and aberration in production images due to thermal and mechanical effects. Sensors on the metrology plate measure the position of the metrology plate relative to the image and to the substrate during exposure of the substrate to the production image. Data from the sensors are used to adjust the projection optics and/or substrate dynamically to correct or compensate for alignment errors and aberration-induced errors. Compared to prior art systems and methods, the projection systems and methods described herein offer greater design flexibility and relaxed constraints on mechanical stability and thermally induced expansion. In addition, decoupled metrology plates can be used to align two or more objectives simultaneously and independently.

Abstract: An apparatus and method for monitoring precursor flux is disclosed herein. The apparatus comprises an optical cell configured for electromagnetic radiation spectroscopy and has a precursor reservoir or deposition chamber configured to provide a flow of a vapor deposition precursor therethrough, a first inner window sealing a first optical opening in the precursor reservoir or deposition chamber, a first outer window in optical communication with the first inner window, a first vacuum chamber disposed between the first inner window and the first outer window, a second inner window sealing a second optical opening in the precursor reservoir or deposition chamber, a second outer window in optical communication with the second inner window, a second vacuum chamber disposed between the second inner window and the second outer window. Each window being disposed to be in optical communication with one another, a electromagnetic radiation or light source, and an optical detector.

Abstract: A system and method for processing a wafer includes a charge neutralization system. The wafer processing system includes a wafer measuring device that can measure characteristics of a surface of the semiconductor wafer. One or more wafer processing stations perform a chemical mechanical polish (CMP) process on the wafer surface. A desica cleaning station can clean and dry the semiconductor wafer. The wafer processing system further includes a charge neutralizing device that can alter a surface charge of the wafer surface.

Abstract: A structure and methods for using an integrated circuit structure comprise a substrate and circuitry connected to the substrate. The substrate includes a heat sensitive material that changes color when heated. The heat sensitive material has one of a plurality of colors depending upon a temperature to which the substrate was exposed.

Abstract: A method to determine the cleanness of a semiconductor substrate and the quantity/density of pin holes that may exist within a patterned antireflective coating (ARC) is provided. Electroplating is employed to monitor the changes in the porosity of the ARC caused by the pin holes during solar cell manufacturing. In particular, electroplating a metal or metal alloy to form a metallic grid on an exposed front side surface of a substrate also fills the pin holes. The quantity/density of metallic filled pin holes (and hence the number of pin holes) in the patterned ARC can then be determined.

Abstract: Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. A combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.

Abstract: Methods of fabricating of a light-emitting device are provided, the methods include forming a plurality of light-emitting units on a substrate, measuring light characteristics of the plurality of light-emitting units, respectively, depositing a phosphor layer on the plurality of light-emitting units using a printing method, and cutting the substrate to separate the plurality of light-emitting units into unit by unit. The phosphor layer is adjustably deposited according to the measured light characteristics of the plurality of light-emitting units.

Abstract: A method of fabricating a semiconductor device and a fabrication system of the semiconductor device are provided. The method includes sequentially forming a film to be etched and a dielectric film and measuring a thickness of the dielectric film, forming a photoresist film on the dielectric film, performing a lithography process using the measured thickness of the dielectric film to form a photoresist film pattern, and etching the dielectric film and the film to be etched using the photoresist film pattern.

Abstract: A method of aligning a wafer when lithographically fabricating a light-emitting diode (LED). The method includes forming on the wafer at least one roughened alignment mark having a root-mean-square (RMS) surface roughness ?S. The roughened alignment mark is formed as a consequence of forming a plasma etch to roughen a LED surface on which the wafer alignment mark resides. The method also includes imaging the at least one roughened wafer alignment mark with alignment light having a wavelength ?A that is in the range from about 2?S to about 8?S. The method also includes comparing the detected image to an alignment reference to establish wafer alignment. Once wafer alignment is established, p-contacts and n-contacts can be formed on the LED upper surface in their proper locations.

Abstract: Protons are entered into a substrate to be analyzed at a proton incident angle larger than 0° and smaller 90°. Excited by the entered protons and emitted from the substrate to be analyzed, the characteristic X-ray is measured by an energy dispersive X-ray detector and the like. Impurity elements present in the substrate to be analyzed are identified based on the measured characteristic X-ray. The in-plane distribution in the substrate can be obtained by scanning the proton beam. The in-depth distribution can be obtained by entering protons at different proton incident angles. The elemental analysis method can be applied to semiconductor device manufacturing processes to analyze metal contamination or quantify a conductivity determining impurity element on an inline basis and with a high degree of accuracy.

Abstract: A method of manufacturing a nano device by directly printing a plurality of NW devices in a desired shape on a predesigned gate substrate. The method includes preparing an NW solution, preparing a building block for performing decaling onto the substrate by carrying an NW device, forming the NW device by connecting electrodes of each of building block units of the building block using NWs by dropping the NW solution between the electrodes and then through dielectrophoresis, visually inspecting the numbers of NW bridges that are formed between the electrodes of each of the building block units through the dielectrophoresis, grouping the building block units according to the numbers, and decaling the NW device formed on each of the building block units onto the gate substrate by bringing the grouped building block units into contact with the predesigned gate substrate and then detaching the grouped building block units.

Abstract: A method for evaluating a process of manufacturing a semiconductor integrated circuit including a deposition step and a polishing step after the deposition step, the method includes: dividing the semiconductor integrated circuit into a plurality of areas; determining a deposition height after the deposition step for each of the areas; and determining a risk value for each of the areas on the basis of a difference in the deposition height between each of the areas and its adjacent areas.

Abstract: A nondestructive testing method for an oxide semiconductor layer includes the steps of applying excitation light to an amorphous or polycrystalline target oxide semiconductor layer to be tested and measuring an intensity of photoluminescence in a wavelength region longer than a wavelength corresponding to a bandgap energy among light emitted from the target oxide semiconductor layer; and estimating a film property of the target oxide semiconductor layer on the basis of measurement results.

Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first electrode, a second electrode, a first insulating layer, a first interconnect layer, a second interconnect layer, a first metal pillar, a second metal pillar and a second insulating layer. The semiconductor layer includes a first major surface, a second major surface opposite to the first major surface and a light emitting layer. An edge of a part of the first interconnect layer is exposed laterally from the first insulating layer and the second insulating layer.

Abstract: According to one embodiment, a method for manufacturing a semiconductor light emitting device is disclosed. The method can include forming a first interconnect layer, a second interconnect layer, a first metal pillar, a second metal pillar, a second insulating layer, a transparent material and a phosphor layer. The transparent material is formed on the first major surface of a semiconductor layer selected from the plurality of semiconductor layers on the basis of an emission spectrum of a light obtained from the first major surface side. The transparent material transmits the light. The phosphor layer is formed on the transparent material and the first major surface of the plurality of the semiconductor layers.

Abstract: An object is to prevent a breakage of a membrane probe and a wafer to be tested in a probe testing using a membrane probe with styluses formed by a manufacturing technology for a semiconductor integrated circuit device. Measures are: obtaining an image of a region PCA within the surface of a wafer including a region OGA pressed by a pressing member, at the center of which a chip just after probe-tested is located, by an imaging means such as a camera; comparing an image of a normal chip obtained in advance and an image of all the chips within the region PCA; and judging thereby whether an abnormal shape is caused or not in all the chips within the region PCA.

Abstract: A method of forming a monitor mark includes forming an insulating film on a semiconductor substrate, and forming a first repetitive line pattern group and a second repetitive line pattern group by patterning the insulating film on the semiconductor substrate, such that the first repetitive line pattern group and the second repetitive line pattern group face each other with a predetermined space therebetween.

Abstract: The present invention relates to integrating an inertial mechanical device on top of an IC substrate monolithically using IC-foundry compatible processes. The IC substrate is completed first using standard IC processes. A thick silicon layer is added on top of the IC substrate. A subsequent patterning step defines a mechanical structure for inertial sensing. Finally, the mechanical device is encapsulated by a thick insulating layer at the wafer level. Compared with the incumbent bulk or surface micromachined MEMS inertial sensors, vertically monolithically integrated inertial sensors provided by embodiments of the present invention have one or more of the following advantages: smaller chip size, lower parasitics, higher sensitivity, lower power, and lower cost.

Abstract: An inspecting method increases the accuracy of a DSA (Defect Source Analysis) for thereby increasing the yield of semiconductor devices which are manufactured. For performing a DSA using data of a defect inspecting process obtained when wiring patterns are formed on a wafer and data of a VC (Voltage Contrast) inspecting process performed after the wiring patterns are formed, a rectangular DSA area is established in relation to a wiring pattern in which a nonconductive area is detected, based on the shape of the wiring pattern. For example, if three defects are detected in the defect inspecting process, then it is possible to select only at least one of those defects which affects the wiring pattern in the DSA area. Since fabrication steps can appropriately be evaluated based on the selected defect, suitable actions may be taken for any problematic fabrication step based on the evaluation of the fabrication steps.

Abstract: A semiconductor integrated circuit includes: a semiconductor chip; a through-chip via passing through a conductive pattern disposed in the semiconductor chip and cutting the conductive pattern; and an insulation pattern disposed on an outer circumference surface of the through-chip via to insulate the conductive pattern from the through-chip via.

Abstract: According to a sub-resolution assist feature arranging method in embodiments, it is selected which of a rule base and a model base is set for which pattern region on pattern data corresponding to a main pattern as a type of the method of arranging the sub-resolution assist feature for improving resolution of the main pattern formed on a substrate. Then, the sub-resolution assist feature by the rule base is arranged in a pattern region set as the rule base and the sub-resolution assist feature by the model base is arranged in a pattern region set as the model base.

Abstract: A light-emitting device having improved light conversion efficiency, a light-emitting system including the same, and fabricating methods of the light-emitting device and the light-emitting system, are provided. The light-emitting device includes one or more light-emitting elements arranged on one surface of a substrate, and a phosphor layer disposed inside or on the substrate to a predetermined thickness and partially wavelength-converts the light emitted from the one or more light-emitting elements into light having different wavelength, wherein a light conversion efficiency of the phosphor layer is maximized when the phosphor layer has the predetermined thickness.

Abstract: A method for producing a plurality of LED illumination devices which each emit light having an average value of a first photometric parameter including producing a plurality of LED chips which emit light of the same color; measuring values of the first photometric parameter of the LED chips; combining the LED chips to form groups of at least two LED chips which have different values of the first photometric parameter such that differences in the average values of all the LED illumination devices are imperceptible to the human eye; and equipping a respective LED illumination device with a group of LED chips.

Abstract: A transducer array on a common substrate includes a membrane and first and second transducer devices. The membrane is formed on the common substrate, and includes a lower layer and an upper layer. The first transducer device includes a first resonator stack formed on at least the lower layer in a first portion of the membrane, the upper layer having a first thickness in the first portion of the membrane. The second transducer device includes a second resonator stack formed on at least the lower layer in a second portion of the membrane, the upper layer having a second thickness in the second portion of the membrane, where the second thickness is different from the first thickness, such that a first resonant frequency of the first transducer device is different from a second resonant frequency of the second transducer device.

Abstract: A first wafer is fabricated using a first value for a process parameter specifying a process condition in fabricating the structure. A first value of a dispersion is measured from the first wafer. A second wafer is fabricated using a second value for the process parameter. A second value of the dispersion is measured from the second wafer. A third wafer is fabricated using a third value for the process parameter. The first, second, and third values for the process parameter are different from each other. A third value of the dispersion is measured from the third wafer. A dispersion function is defined to relate the process parameter to the dispersion using the first, second, and third values for the process parameter and the measured first, second, and third values of the dispersion. The simulated diffraction signal is generated using the defined dispersion function. The simulated diffraction signal is stored.

Abstract: According to one exemplary embodiment, a method for determining a power spectral density of an edge of at least one patterned feature situated over a semiconductor wafer includes measuring the edge of the at least one patterned feature at a number of points on the edge. The method further includes determining an autoregressive estimation of the edge of the at least one patterned feature using measured data corresponding to a number of points on the edge. The method further includes determining a power spectral density of the edge using autoregressive coefficients from the autoregressive estimation. The method further includes utilizing the power spectral density to characterize line edge roughness of the at least one patterned feature in a frequency domain.

Abstract: A method of enabling a circuit board analysis is disclosed. The method comprising removing a portion of the circuit board on a first side of the circuit board opposite a second side of the circuit board having an integrated circuit package; removing the circuit board from the integrated circuit package; performing a dye mapping to analyze bonds between the integrated circuit package and the circuit board; and performing an analysis of the integrated circuit package.

Abstract: Methods of forming conductive patterns include forming a conductive layer including a metal element on a substrate. The conductive layer is partially etched to generate a residue including an oxide of the metal element and to form a plurality of separately formed conductive layer patterns. A cleaning gas is inflowed onto the substrate including the conductive layer pattern. The metal compound is evaporated to remove the metal element contained in the residue and to form an insulating interface layer on the conductive layer pattern and a surface portion of the substrate through a reaction of a portion of the cleaning gas and oxygen. The residue may be removed from the conductive layer pattern to suppress generation of a leakage current.

Abstract: A method comprises providing a semiconductor structure. The semiconductor structure comprises a feature comprising a first material and a layer of a second material formed over the feature. The semiconductor structure is exposed to an etchant. The etchant is adapted to selectively remove the first material, leaving the second material substantially intact. After exposing the semiconductor structure to the etchant, it is detected whether the feature has been affected by the etchant.

Abstract: A surface plasmon resonance sensor includes a substrate, a dielectric film having a nonlinear optical effect on a first surface of the substrate, and a probe fixed to the dielectric film. A plasmon resonance is produced by resonating a surface plasmon generated on the first surface of the substrate with an evanescent wave generated on a second surface of the substrate by incident light radiated to the second surface. The plasmon resonance is detected by measuring a change of a component of light reflected on the second surface of the substrate. The component of the reflected light is caused by the nonlinear optical effect. This surface plasmon resonance sensor has a high measuring sensitivity.

Abstract: The active pixel cell structures and methods of preparing such structures described above enable reduction of dark current and white cell counts for active pixel cells. The process of preparing active pixel cell structures introduces stress on the substrate, which could lead to increased dark current and white cell counts of active pixel cells. By depositing a stress layer as part of a pre-metal dielectric layer with a stress that counters the stress induced, both the dark current and the white cell counts can be reduced. If the transistors of the active pixel cells are NMOS, the carrier mobility can also be increased by a tensile stress layer. Raman Spectroscopy can be used to measure the stress exerted on the substrate prior to the deposition of the stress layer.

Abstract: A method of removing contaminations includes providing a wafer, performing an inspection or a measuring step to the wafer, and performing a baking step to re-vaporize and remove contaminations from the wafer after the inspection or measuring step.

Abstract: An inspection tool includes a camera for obtaining images of a wafer and a controller configured for performing light source flat field correction, optical image warping correction, and optical image scale correction of the images. In operation, separate inspection tools are calibrated separately to obtain a characteristic response with respect to imaging and/or illumination for each such inspection tool. A standard target is then imaged by each inspection tool and the response of each of the inspection tools is normalized to ensure uniformity of the output of each inspection tool with respect to the other inspection tools.

Abstract: The present invention provides a method for forming an oxide film on a silicon wafer, comprising: measuring surface roughness of the silicon wafer and/or crystallinity in a surface layer portion of the silicon wafer in advance; adjusting oxidizing conditions for the silicon wafer based on the measurement value; and forming the oxide film on the silicon wafer under the adjusted oxidizing conditions. As a result, there can be provided the method for forming an oxide film by which the oxidizing conditions can be adjusted based on a state of the surface and/or the surface layer of the silicon wafer before forming the oxide film and even an ultrathin oxide film can be thereby accurately formed.

Abstract: In accordance with one embodiment of the present disclosure, a process of manufacturing a semiconductor laser diode comprising a gain section, a QWI output window, and QWI waveguide areas is provided. The QWI waveguide areas are fabricated using quantum well intermixing and define a QWI waveguide portion in the QWI output window of the laser diode. The QWI output window is transparent to the lasing wavelength ?L. The QWI waveguide portion in the QWI output window is characterized by an energy bandgap that is larger than an energy bandgap of the gain section such that the band gap wavelength ?QWI in the QWI waveguide portion and the QWI output window is shorter than the lasing wavelength ?L. The QWI output window is characterized by a photoluminescent wavelength ?PL. The manufacturing process comprises a ?PL screening protocol that determines laser diode reliability based on a comparison of the lasing wavelength ?L and the photoluminescent wavelength ?PL of the QWI output window.

Abstract: A mask forming method includes preparing design data of mask including pattern regions having identical repetition patterns respectively, generating mask pattern data of mask based on the design data, generating inspection control information for controlling inspection of defect on mask based on the mask pattern data, the information including positional information of the pattern regions and inspection sensitivity information of the repetition pattern, providing the inspection control information to mask pattern data, forming mask pattern of mask based on the mask pattern data, and inspecting the mask pattern based on the mask pattern data comprising inspecting portion in the mask pattern different from the pattern regions by Die-to-Database comparison method, the inspecting the portion including selecting portion corresponding to repetition pattern from the mask pattern based on the positional information, and inspecting the selected portion by Die-to-Die comparison method at an inspection sensitivity corre

Abstract: A method for inspection of defects on a substrate includes positioning a probe of a scanning probe microscopy (SPM) over and spaced apart from a substrate, includes scanning the substrate by changing a relative position of the probe with respect to the substrate on a plane spaced apart from and parallel to the substrate, and includes measuring a value of an induced current generated via the probe in at least two different regions of the substrate. The value of the induced current is variable according to at least a shape and a material of the substrate. The method further includes determining whether a defect exists by comparing the values of the induced currents measured in the at least two different regions of the substrate.

Abstract: A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a second notch; laminating the semiconductor substrate with the supporting substrate so that the first notch can be matched with the second notch; and processing a second main surface of the semiconductor substrate opposite to a first main surface thereof facing to the supporting substrate to reduce a thickness of the semiconductor substrate to a predetermined thickness.

Abstract: Embodiments of the present invention provide an LED having a Wavelength Shift Layer (WSL) and method of manufacture. Specifically, under embodiment of the present invention, a WSL layer is applied over an LED chip. The WSL itself typically comprises two layers: an adhesion layer applied over a set (at least one) of LED chips, and a conformal coating over the adhesion layer. The adhesion layer provides improved adhesive effect of the conformal coating to the LED chip(s). The conformal coating is comprised of a particular phosphor ratio that is determined based on a wavelength measurement of the underlying LED chip(s). Specifically, under the present invention, a wavelength of a light output by an LED chip(s) (e.g., blue or ultra-violet (UV)) is measured (e.g., at the wafer level). Typically, the phosphor ratio of is comprised of at least one of the following colors: yellow, green, or red. Regardless, this conformal coating is applied over a glue layer that itself is applied over the LED chip.

Abstract: Provided is a TFT board for a liquid crystal display device including: a circuit layer formed on a substrate, the circuit layer including a thin film transistor including a semiconductor layer, a gate electrode, a drain electrode, and a source electrode; and a color filter layer formed on the circuit layer. The color filter layer has a through hole formed therein above the semiconductor layer in a region between the source electrode and the drain electrode.

Abstract: A product layout testing method includes testing and correcting one or more patterns of a product layout, detecting and correcting electrical characteristic changes of transistors of the product layout, and testing whether a product characteristic predicted from the product layout is equal to that predicted from a designed circuit view. Weak points with respect to the pattern may be detected and corrected, electrical characteristic changes depending on layout parameters may be detected and corrected, and whether a circuit operation depending on parasitic components is normal may be checked.

Abstract: Wafers A1 to A10 of a first lot A and wafers B1 to B10 of a second lot B are processed by a second heating unit at different temperatures, respectively. A wafer W is carried in a processing block included in coating and developing system along a route passing a temperature control unit CPL2, a coating unit BCT, a heating unit LHP2, a temperature control unit CPL3, a coating unit COT, a heating unit LHP3, and a cooling unit COL in that order. The process temperature of the heating unit LHP3 is changed after the last wafer A10 of the first lot A has been processed by the heating unit LHP3.

Abstract: An apparatus for performing non-contact material characterization includes a wafer carrier adapted to hold a plurality of substrates and a material characterization device, such as a device for performing photoluminescence spectroscopy. The apparatus is adapted to perform non-contact material characterization on at least a portion of the wafer carrier, including the substrates disposed thereon.