Abstract: An expansion/contraction measuring apparatus includes a transport section which transports a flexible substrate along a surface of the substrate; a detecting section detecting first and second marks which are formed on the substrate while being separated from each other by a predetermined spacing distance in a transport direction of the substrate and which are moved, in accordance with the transport of the substrate, to first and second detection areas disposed on a transport route for the substrate respectively; a substrate length setting section which sets a length of the substrate along the transport route between the first and second detection areas to a reference length; and a deriving section which derives information about expansion/contraction of the substrate in relation to the transport direction based on a detection result of the first and second marks. Accordingly, the expansion/contraction state of an expandable/contractible substrate is measured highly accurately.

Abstract: The present disclosure relates to the field of microelectronic substrate fabrication and, more particularly, to alignment inspection for vias formed in the microelectronic substrates. The alignment inspection may be achieved by determining the relative positions of fluorescing and non-fluorescing elements in a microelectronic substrate.

Abstract: According to one embodiment, a method for manufacturing a semiconductor light emitting device is disclosed. The method can include forming a first interconnect layer, a second interconnect layer, a first metal pillar, a second metal pillar, a second insulating layer, a transparent material and a phosphor layer. The transparent material is formed on the first major surface of a semiconductor layer selected from the plurality of semiconductor layers on the basis of an emission spectrum of a light obtained from the first major surface side. The transparent material transmits the light. The phosphor layer is formed on the transparent material and the first major surface of the plurality of the semiconductor layers.

Abstract: A laser diode includes a junction surface configured to interface with an integrated optics slider. Cathode and anode electrical junctions are disposed on the junction surface. The cathode and anode electrical junctions are configured for electrical and mechanical coupling to the integrated optics slider. At least one test pad is disposed on the junction surface that is physically separate from and electrically coupled to one of the cathode and anode electrical junctions. The test pad is configured to be contacted by a test probe and is not configured for electrical or mechanical coupling to the integrated optics slider.

Abstract: A method of forming ohmic contacts on a light emitting diode that features a surface treatment of a substrate includes exposing a surface of a p-type gallium nitride layer to an acid-containing solution and a buffered oxide etch process. A quantum well is formed in a gallium nitride substrate and a layer of p-type gallium nitride is deposited over the quantum well. The surface of the p-type gallium nitride is exposed to an acid-containing solution and then a buffered oxide etch process is performed to provide an etched surface. A metal stack including a layer of silver disposed between layers of platinum is then deposited.

Abstract: An organic light-emitting display device includes a gate electrode, a source electrode, and a drain electrode on a substrate, a gate interconnection line connected to the gate electrode, a source and drain interconnection line connected to the source and drain electrodes, a first test pad electrically connected to the source and drain interconnection line, and a second test pad electrically connected to the gate interconnection line. The second test pad is at a same level as the first test pad, and the gate electrode is on a different layer than the source and drain electrodes.

Abstract: An optoelectronic device including at least one of a solar device, a semiconductor device, and an electronic device. The device includes a semiconductor unit. A plurality of metal fingers is disposed on a surface of the semiconductor unit for electrical conduction. Each of the metal fingers includes a pad area for forming an electrical contact. The optoelectronic device includes a plurality of pad areas that is available for connection to a bus bar, wherein each of the metal fingers is connected to a corresponding pad area for forming an electrical contact.

Abstract: Methods for fabricating semiconductor devices such as LED chips with emission wavelength correction and devices fabricated using these methods. Different embodiments include sequential coating methods that provide two or more coatings or layers of conversion material over LEDs, which can be done at the wafer level. The methods are particularly applicable to fabricating LED chips that emit a warm white light, which typically requires covering LEDs with one or more wavelength conversion materials such as phosphors. In one embodiment, a base wavelength conversion material is applied to the semiconductor devices. A portion of the base conversion material is removed. At least two different tuning wavelength conversion materials are also applied to the semiconductor devices, either before or after the application of the base conversion material.

Abstract: In a plasma processing apparatus in which a wafer is processed while supplying radio frequency power to electrodes disposed in a sample stage in a processing chamber within a reactor via a matching box, by matching a specific value of power at transition points of data values of at least two kinds among characteristic data including light emission intensity of the plasma, magnitude of its time variation, a matching position of the matching box, and a change of a value of a voltage of the radio frequency power supplied to the electrodes detected by varying the power to a plurality of values during the processing with a value detected by using characteristic data which is detected during the processing executed on a wafer of the same kind in a different reactor, the differences of the states inside the processing chamber or plasma among a plurality of semiconductor processing apparatuses or reactors are reduced.

Abstract: A method for depositing a semiconductor layer on a multiplicity of substrates. The process chamber height (H), which is defined by the spacing between a process chamber ceiling (8) and a process chamber floor (9) is variable and influences the growth rate of the layer. The layer thickness is measured continuously or at in short intervals on at least one substrate (5) in each process chamber (2) while the layer is growing. The process chamber height (H) is varied by means of a controller (12) and an adjusting member (6), so that layers having the same layer thickness are deposited in the process chambers.

Abstract: Provided is a method of manufacturing a TFT substrate for preventing characteristics of a native oxide layer in a boundary between a microcrystal semiconductor layer and an amorphous semiconductor layer from being degraded. The method includes forming a gate electrode, forming a gate insulating film, modifying the formed first amorphous silicon thin film into a first crystalline silicon thin film, removing a silicon oxide layer on the surface of the first crystalline silicon thin film, forming the second amorphous silicon thin film, and dry etching the first crystalline silicon thin film and the second amorphous silicon thin film, and it is determined whether or not the in-process TFT substrate after the dry etching is returned to the processes after the dry etching by measuring the emission intensity of radicals in plasma during the dry etching and detecting the presence or absence of the silicon oxide layer in the boundary.

Abstract: A substrate processing system includes a resist pattern forming apparatus including modules each configured to perform a predetermined process on a substrate with an underlying film formed thereon, an etched pattern forming apparatus including chambers each configured to perform patterning of the underlying film by use of a resist pattern as a mask, and examination devices configured to perform measurement and examination of a pattern attribute rendered on a substrate after a process in the resist pattern forming apparatus and after a process in the etched pattern forming apparatus. A controller is preset to utilize measurement results and transfer data to calculate correction value ranges respectively settable in the modules and the chambers and to determine combinations of the modules and the chambers such that corrections made within the correction value ranges cause a pattern attribute to approximate a predetermined value for each of the substrates.

Abstract: Disclosed herein are systems and methods for in-situ measurement of impurities on metal slugs utilized in electron-beam metal evaporation/deposition systems, and for increasing the production yield of a semiconductor manufacturing processes utilizing electron-beam metal evaporation/deposition systems. A voltage and/or a current level on an electrode disposed in a deposition chamber of an electron-beam metal evaporation/deposition system is monitored and used to measure contamination of the metal slug. Should the voltage or current reach a certain level, the deposition is completed and the system is inspected for contamination.

Abstract: Embodiments of the present invention pertain to substrate processing equipment and methods incorporating light sources which provide independent control of light pulse duration, shape and repetition rate. Embodiments further provide rapid increases and decreases in intensity of illumination.

Abstract: To provide a manufacturing method of a semiconductor device capable of placing a larger number of alignment marks for lithography and PCM and at the same time, preventing information leakage from the PCM. In a portion of a first scribe region sandwiched between first semiconductor chip regions, a first region and a second region are placed in parallel to each other. The first region is equipped with at least one monitor selected from a first monitor for electrically evaluating at least either one of an active element (such as transistor) and a passive element (such as resistor or capacitor), a second monitor for dimensional control, and a third monitor for measuring film thickness. In the second region, an alignment mark for lithography is placed. In the cutting step, the first region is cut off.

Abstract: A technique is provided which can exactly recognize a chip to be picked up when picking up the chip from a wafer sheet in a process of die bonding a thin chip. A camera is coupled to one end of a lens barrel, an objective lens is attached to an opposite end of the lens barrel, and an image of a main surface of a chip is photographed through the objective lens. A surface-emitting lighting unit, a diffusing plate and a half mirror are internally provided between the lens barrel and the chip. Further, another lens barrel having a coaxial drop lighting function of radiating light to the main surface of the chip along the same optical axis as that of the camera is disposed.

Abstract: Wafer-level packaging of solid-state transducers (“SSTs”) is disclosed herein. A method in accordance with a particular embodiment includes forming a transducer structure having a first surface and a second surface opposite the first surface, and forming a plurality of separators that extend from at least the first surface of the transducer structure to beyond the second surface. The separators can demarcate lateral dimensions of individual SSTs. The method can further include forming a support substrate on the first surface of the transducer structure, and forming a plurality of discrete optical elements on the second surface of the transducer structure. The separators can form barriers between the discrete optical elements. The method can still further include dicing the SSTs along the separators. Associated SST devices and systems are also disclosed herein.

Abstract: Methods of fabricating of a light-emitting device are provided, the methods include forming a plurality of light-emitting units on a substrate, measuring light characteristics of the plurality of light-emitting units, respectively, depositing a phosphor layer on the plurality of light-emitting units using a printing method, and cutting the substrate to separate the plurality of light-emitting units into unit by unit. The phosphor layer is adjustably deposited according to the measured light characteristics of the plurality of light-emitting units.

Abstract: A method of forming an optical sensor includes the following steps. A substrate is provided, and a read-out device is formed on the substrate. a first electrode electrically connected to the read-out device is formed on the substrate. a photosensitive silicon-rich dielectric layer is formed on the first electrode, wherein the photosensitive silicon-rich dielectric layer comprises a plurality of nanocrystalline silicon crystals. A second electrode is formed on the photosensitive silicon-rich dielectric layer.

Abstract: A method for checking an ion implantation condition when ions are implanted over an entirety of one surface of a semiconductor wafer having an insulator film on the one surface, the method including checking whether the ions are implanted over the entirety of the one surface of the semiconductor wafer by directly or indirectly observing light emitted when the one surface of the semiconductor wafer is irradiated with an ion beam of the implanted ions throughout the ion implantation.

Abstract: A manufacturing method of a semiconductor device capable of efficiently inspecting whether a metal silicide layer is sufficiently formed is provided. The manufacturing method is provided with the steps of forming a metal layer over a semiconductor layer containing silicon; forming a metal silicide layer over a surface of the semiconductor layer by heating the semiconductor layer and the metal layer; generating image data by performing color imaging of the metal silicide layer from above the metal silicide layer; calculating saturation of the metal silicide layer by processing the image data; and judging the formation amount of the metal silicide layer on the basis of the calculated saturation.

Abstract: A processing system having a chamber for in-situ optical interrogation of plasma emission to quantitatively measure normalized optical emission spectra is provided. The processing chamber includes a confinement ring assembly, a flash lamp, and a set of quartz windows. The processing chamber also includes a plurality of collimated optical assemblies, the plurality of collimated optical assemblies are optically coupled to the set of quartz windows. The processing chamber also includes a plurality of fiber optic bundles. The processing chamber also includes a multi-channel spectrometer, the multi-channel spectrometer is configured with at least a signal channel and a reference channel, the signal channel is optically coupled to at least the flash lamp, the set of quartz windows, the set of collimated optical assemblies, the illuminated fiber optic bundle, and the collection fiber optic bundle to measure a first signal.

Abstract: According to example embodiments, a methods includes forming a peripheral structure including peripheral circuits on a peripheral circuits region of a substrate, recessing a cell array region of the substrate to form a concave region having a bottom surface lower than a top surface of the peripheral structure, forming a stacked layer structure conformally covering the concave region, the stacked layer structure including a plurality of layers sequentially stacked and having a lowest top surface in the cell array region and a highest top surface in the peripheral circuits region, forming a planarization stop layer that conformally covers the stacked layer structure, and planarizing the stacked layer structure using the planarization stop layer in the cell array region as a planarization end point to expose top surfaces of the thin layers between the cell array region and the peripheral circuits region simultaneously with a top surface of the peripheral structure.

Abstract: A solid-state image pickup device includes a plurality of photoelectric conversion units, a plurality of signal read-out circuits, and a test terminal for testing the photoelectric conversion units. Each of the photoelectric conversion units includes a pixel electrode film, an opposing electrode film opposing the pixel electrode film and a light receiving layer disposed between the pixel electrode film and the opposing electrode film. The photoelectric conversion units are arranged in a two-dimensional array above a semiconductor substrate. Each of the signal read-out circuits are configured to read out a signal corresponding to an amount of electrical charges generated in the light receiving layer and transferred to the pixel electrode film. The test terminal is disposed outside of an area where the photoelectric conversion units are disposed, disposed on the same plane as the pixel electrode film, and made of the same material as the pixel electrode film.

Abstract: A method of manufacturing a semiconductor device, includes providing a mark above a main surface on a semiconductor substrate, separating the semiconductor substrate into a plurality of semiconductor elements by cutting the semiconductor substrate, determining a reference semiconductor element on the basis of a coordinate data indicating coordinates of the mark and coordinates of all of the semiconductor elements on the semiconductor substrate, and picking-out the semiconductor elements on the basis of the coordinate data using a pick-out apparatus. The providing operation includes forming a protective coat onto the main surface of the semiconductor substrate, irradiating a point on the main surface of the semiconductor substrate with a laser beam through the protective coat, and eliminating the protective coat from the main surface of the semiconductor substrate.

Abstract: Provided is a method for processing a wafer edge portion using photolithograph equipment. The method includes placing a wafer on a support plate, inspecting a bead removal state of an edge portion of the wafer placed on the support plate, and exposing the edge portion of the wafer placed on the support plate to light. The inspecting of the bead removal state is performed by capturing first images from the wafer placed on the support plate and inspecting the first images.

Abstract: The present invention relates generally to assembly techniques. According to the present invention, the alignment and probing techniques to improve the accuracy of component placement in assembly are described. More particularly, the invention includes methods and structures to detect and improve the component placement accuracy on a target platform by incorporating alignment marks on component and reference marks on target platform under various probing techniques. A set of sensors grouped in any array to form a multiple-sensor probe can detect the deviation of displaced components in assembly.

Abstract: A device includes first and second material facing towards each other as to form at least one focusing microstructure with a focal point located outside of the first material.

Abstract: A thin film transistor array panel and a manufacturing method therefor. A shorting bar for connecting a thin film transistor with data lines is formed separate from the data lines, and then the data lines and the shorting bar are connected through a connecting member. As a result, all the data lines are floated during manufacture, so that variation in etching speed between data lines does not occur. Since variation in etching speed between the data lines can be prevented, performance deterioration of the transistor caused by a thickness difference in the lower layer of the data line can be prevented, as can resulting deterioration in display quality. Also, the influence of static electricity can be reduced or eliminated. Furthermore, since the data lines and the shorting bar are connected to each other, the generation of static electricity can be prevented or reduced, and quality testing is more readily performed.

Abstract: A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a second notch; laminating the semiconductor substrate with the supporting substrate so that the first notch can be matched with the second notch; and processing a second main surface of the semiconductor substrate opposite to a first main surface thereof facing to the supporting substrate to reduce a thickness of the semiconductor substrate to a predetermined thickness.

Abstract: A method for in situ determination of a material composition of optically thin layers deposited from a vapor phase onto a substrate includes irradiating the substrate with incoherent light of at least three different wavelengths, optically detecting in a spatially resolved manner a reflection intensity of a diffuse or a direct light scattering emanating from a deposited layer outside of a total reflection, concurrently providing numerical values of the detected reflection intensity to an optical layer model based on general line transmission theory, ascertaining values for the optical layer parameters of the deposited layer from the optical layer model for the at least three different wavelengths by numerically adapting the optical layer model to a time characteristic of the detected reflection intensities, and quantitatively determining a material composition of the deposited layer from the ascertained values by comparing the ascertained values to standard values.

Abstract: An overlay mark for determining the relative shift between two or more successive layers of a substrate is disclosed. The overlay mark includes at least one test pattern for determining the relative shift between a first and a second layer of the substrate in a first direction. The test pattern includes a first set of working zones and a second set of working zones. The first set of working zones are disposed on a first layer of the substrate and have at least two working zones diagonally opposed and spatially offset relative to one another. The second set of working zones are disposed on a second layer of the substrate and have at least two working zones diagonally opposed and spatially offset relative to one another. The first set of working zones are generally angled relative to the second set of working zones thus forming an “X” shaped test pattern.

Abstract: Excitation light is irradiated onto a GaN layer on a silicon carbide substrate constituting a layered product that is set on a stage. Then light is emitted from a defective part caused by a structural defect of the silicon carbide substrate out of the GaN layer. By using this light luminescence phenomena, a position of a defective part of the silicon carbide substrate can be detected.

Abstract: A method of detecting manufacturing defects at a memory array may include disposing an active area of a first width in communication with a first conductive member of the memory array to define a grounded conductive member, disposing an isolation structure of a second width in communication with a second conductive member of the memory array to define a floating conductive member, and providing an alternating arrangement of floating and grounded conductive members including arranging a plurality of the grounded and floating conductive members adjacent to each other to define a sequence of alternating floating and grounded conductive members. A corresponding test device is also provided.

Abstract: A method for designing a two-dimensional array overlay target comprises the steps of: selecting a plurality of two dimensional array overlay targets having different overlay errors; calculating a deviation of a simulated diffraction spectrum for each two-dimensional array overlay target; selecting an error-independent overlay target by taking the deviations of the simulated diffraction spectra into consideration; and designing a two dimensional array overlay target based on structural parameters of the error-independent overlay target.

Abstract: A light source manufacturing apparatus, which manufactures a light source device by adhering a laser device and a wavelength converting device that converts the laser light emitted by the laser device to laser light of a different wavelength, includes a first stage that holds the wavelength converting device, a second stage that holds the laser device, a power meter that measures the amount of laser light emitted by the wavelength converting device, a light receiving device that detects the drive waveform of the laser light, and a controlling unit that changes relative positions of the first stage and the second stage in such a manner that the amount of laser light measured by the power meter is a predetermined value or greater and the drive waveform detected by the light receiving device falls within a reference range.

Abstract: After flash irradiation on a semiconductor wafer is started and then the temperatures of front and back surfaces of the semiconductor wafer become equal to each other, the temperature of the back surface of the semiconductor wafer, which has a known emissivity, is measured with a radiation thermometer. The emissivity of the front surface of the semiconductor wafer is calculated based on the intensity of radiated light from a black body having an equal temperature to the temperature of the back surface thereof, and the intensity of radiated light actually radiated from the front surface of the semiconductor wafer. Then, the temperature of the front surface of the semiconductor wafer heated by the flash irradiation is calculated based on the calculated emissivity and the intensity of the radiated light from the front surface of the semiconductor wafer that has been measured after the flash irradiation is started.

Abstract: An inspection method of an SOI wafer in which profiles P1 and P2 are calculated in the SOI wafer to be inspected and in an SOI wafer having a film thickness of the SOI layer thicker or thinner than that of the SOI wafer to be inspected, respectively; a profile P3 of a difference between P1 and P2, or a profile P4 of a change ratio of P1 and P2 is calculated; light having the wavelength band selected on the basis of a maximum peak wavelength within the calculated profiles P3 or P4 is irradiated to the surface of the SOI wafer to be inspected, to detect the reflected-light from the SOI wafer; and a place of a peak generated by an increase in reflection intensity of the detected reflected-light is found, as the defect caused by the change in the film thickness of the SOI layer.

Abstract: A substrate including phosphor is remotely illuminated by an LED. Optical radiation that emerges through the substrate is measured. Portions of the substrate, such as raised features on the substrate, are then selectively removed responsive to the measuring, so as to obtain a desired optical radiation. In removing portions of the substrate, holes may be drilled through the substrate to provide a separate path for light from the LED that does not pass through the phosphor. Alternatively, a separate LED may be provided outside the dome.

Abstract: A chamber-status monitoring apparatus includes a plurality of chambers, a time-division multiplexer configured to receive, via optical fiber probes, optical signals from each chamber, to divide each optical signal into first time slots having a predetermined duration, and to multiplex the first time slots to generate an OTDM signal, a multi-input optical emission spectroscope configured to receive and disperse the OTDM signal according to wavelengths to measure spectrum information, and a controller configured to divide the spectrum information of the dispersed OTDM signal into second time slots with a predetermined time interval therebetween, to classify the second time slots according to the chambers to obtain spectrum information of the optical signals of the individual chambers, and to control endpoint detection in each of the chambers in accordance with the spectrum information of the optical signal of the corresponding chamber.

Abstract: A method of manufacturing a plurality of semiconductor wafers comprising micro-inspecting at least one location within at least one micro-inspected pattern field and determining at least one parameter value representing a property of the wafer at the micro-inspected location, macro-inspecting a plurality of locations within the at least one micro-inspected pattern field and determining, for each macro-inspected location of the macro-inspected pattern field, at least one parameter value representing the property of the wafer at the macro-inspected location based on the light intensity recorded for the macro-inspected location and on the at least one parameter value representing the property of the wafer at the micro-inspected location of this pattern field.

Abstract: The invention relates to a substrate for use in a lithography system, said substrate being provided with an at least partially reflective position mark comprising an array of structures, the array extending along a longitudinal direction of the mark, characterized in that said structures are arranged for varying a reflection coefficient of the mark along the longitudinal direction, wherein said reflection coefficient is determined for a predetermined wavelength. In an embodiment a specular reflection coefficient varies along the substrate, wherein high order diffractions are substantially absorbed by the substrate. A position of a beam on a substrate can thus be determined based on the intensity of its reflection in the substrate. The invention further relates to a positioning device and lithography system for cooperation with the substrate, and a method of manufacture of the substrate.

Abstract: Methods and systems are provided for fabricating a semiconductor device. An exemplary method involves forming a feature of a semiconductor device in a first region of a layer of material on a semiconductor substrate and forming a test structure in a second region of the layer of material. The test structure is formed concurrently to forming the feature, and a dimension of the feature is determined using the test structure.

Abstract: A polishing method and a method for forming a gate are provided. The method includes forming a dummy gate on a semiconductor substrate including a sacrificial oxide layer and a polysilicon layer which covers the sacrificial oxide layer, forming spacers around the dummy gate, and successively forming a silicon nitride layer and a dielectric layer covering the silicon nitride layer. The method further includes polishing the dielectric layer until the silicon nitride layer is exposed, polishing the silicon nitride layer on a fixed abrasive pad until the polysilicon layer is exposed by using a polishing slurry with a PH value ranging from 10.5 to 11 and comprising an anionic surfactant or a zwitterionic surfactant. Additionally, the method includes forming an opening after removing the dummy gate, and forming a gate in the opening. The method eliminates potential erosion and dishing caused in the polishing of the silicon nitride layer.

Abstract: A method of manufacture of an integrated circuit system includes: forming reticle data; detecting a sub-geometry, a singularity, or a combination thereof in the reticle data; applying a unit cell, a patch cell, or a combination thereof for removing the sub-geometry, the singularity, or the combination thereof from the reticle data; and fabricating an integrated circuit from the reticle data.

Abstract: An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.

Abstract: An embodiment of a method to form a hybrid integrated circuit device is described. This embodiment of the method comprises: forming a first die using a first lithography, where the first die is on a substrate; and forming a second die using a second lithography, where the second die is on the first die. The first lithography used to form the first die is a larger lithography than the second lithography used to form the second die. The first die is an IO die.

Abstract: A method of forming a standard mask for an inspection system is provided, the method comprising providing a substrate within a chamber, and providing a tetraethylorthosilicate (TEOS) precursor within the chamber. The method further includes reacting the TEOS precursor with an electron beam to form silicon oxide particles of controlled size at one or more controlled locations on the substrate, the silicon oxide particles disposed as simulated contamination defects.

Abstract: The disclosure relates to a method of aligning a set of patterns on a substrate, which includes depositing on the substrate's surface a set of silicon nanoparticles, which includes a set of ligand molecules including a set of carbon atoms. The method involves forming a first set of regions where the nanoparticles are deposited, while the remaining portions of the substrate surface define a second set of regions. The method also includes densifying the set of nanoparticles into a thin film to form a set of silicon-organic zones on the substrate's surface, wherein the first and the second set of regions have respectively first and second reflectivity values, such that the ratio of the second reflectivity value to the first reflectivity value is greater than about 1.1.

Abstract: The invention relates to a process for deposition of elongated nanoparticles from a liquid carrier onto a substrate, and to electronic devices prepared by this process.