Abstract: A process for alignment a subsequent layer over a previous layer comprising metal features or vias encapsulated in dielectric material comprising the steps of: thinning and planarizing the dielectric material to create a smooth surface of dielectric material and coplanar exposed ends of the via posts; imaging the smooth surface; discerning the position of the end of at least one feature, and using the position of the end of at least one via feature as a registration mark for aligning the subsequent layer.

Abstract: A method of processing IC units comprising the steps of: dicing said IC units from a substrate; delivering said IC units to a idle block; inspecting a face of said units as exposed during the dicing step using an inspection device whilst said units are on said idle block, then; engaging said units with a picker assembly; passing said units over a second inspection device to inspect an opposed face of said units.

Abstract: Methods and systems for resolving and determining sub-wavelength sized features and stresses by using infrared optical and thermal wavelength probing for holographic or interferometric evaluation and testing for all phases of semiconductor device development and manufacture. Specifically, systems and methods are disclosed for extending the range of optical holographic interferometric inspection for testing and evaluating microelectronic devices and determining the interplay of electromagnetic signals and dynamic stresses to the semiconductor material in which an enhanced imaging method provides continuous and varying magnification of the optical holographic interferometric images over a plurality of interleaved optical pathways of varying optical paths and imaging devices.

Abstract: A method of polishing a substrate includes: performing a first polishing process of bringing the substrate into sliding contact with a polishing pad on a first polishing table to polish a metal film; performing a second polishing process of bringing the substrate into sliding contact with a polishing pad on a second polishing table to polish the metal film until a conductive film is exposed; performing a third polishing process of bringing the substrate into sliding contact with a polishing pad on a third polishing table to polish at least the conductive film; and performing a fourth polishing process of bringing the substrate into sliding contact with a polishing pad on a fourth polishing table to polish at least a dielectric film.

Abstract: A method for fabricating a stackable integrated circuit layer and a device made from the method are disclosed. A stud bump is defined on the contact pad of an integrated circuit die and the stud-bumped die encapsulated in a potting material to define a potted assembly. A predetermined portion of the potting material is removed whereby a portion of the stud bump is exposed. One or more electrically conductive traces are defined on the layer surface and in electrical connection with the stud bump to reroute the integrated circuit contacts to predetermined locations on the layer to provide a stackable neolayer.

Abstract: A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.

Abstract: A semiconductor device includes: a semiconductor substrate, first and second internal electrodes provided on a surface of the semiconductor substrate; a first through electrode which penetrates through the semiconductor substrate in a thickness direction and is electrically connected to the first internal electrode; and a second through electrode connected to the second internal electrode, and the second internal electrode is thinner than the first internal electrode. The second through electrode may penetrate through the second internal electrode.

Abstract: A coating film (90) is formed by causing vapor deposition particles (91) discharged from a vapor deposition source opening (61) of a vapor deposition source (60) to pass through a space between a plurality of control plates (81) of a control plate unit (80) and a mask opening (71) of a vapor deposition mask in this order and adhere to a substrate, while the substrate (10) is moved relative to the vapor deposition mask (70) in a state in which the substrate (10) and the vapor deposition mask (70) are spaced apart at a fixed interval. A difference in the amount of thermal expansion between the vapor deposition source and the control plate unit is detected and corrected. It is thereby possible to form, at a desired position on a large-sized substrate, the coating film in which edge blur and variations in the edge blur are suppressed.

Abstract: The present disclosure provides a method and system for characterizing a pattern loading effect. A method may include performing a reflectivity measurement on a semiconductor wafer and determining an anneal process technique based on the reflectivity measurement. The determining the anneal process technique may include determining a spatial distance for a reflectivity change using a reflectivity map generated using the reflectivity measurement. This spatial distance is compared with the thermal diffusion length associated with each of the plurality of anneal process techniques. In an embodiment, a thermal profile map and/or a device performance map may be provided.

Abstract: The present invention suppresses reductions in inspection precision caused by reflected and scattered light produced by wafer holders. In a wafer holder (10) that has protruding support parts (11) that contact and support a wafer and groove parts (12) that are separated from the wafer, the protruding support parts (11) are extended continuously from a part that supports one edge of the wafer to a part that supports the other edge of the wafer. Connecting parts (13) that connect adjacent protruding support parts (11) are provided in each of the vicinity of the parts supporting the one edge and the vicinity of the parts supporting the other edge.

Abstract: There is provide an inspection apparatus configured to detect a change in shape of a pattern in the depth direction o the pattern, the apparatus including: an illumination section 20 which illuminates a wafer 5 having a periodic pattern with an illumination light having transmittance with respect to the wafer 5; a reflected diffraction light detecting section 30 which outputs a first detection signal by receiving a reflected diffraction light generated by the pattern on a surface, of the wafer, on an illumination side illuminated with the illumination light; a transmitted diffraction light detecting section 40 which outputs a second detection signal by receiving a transmitted diffraction light generated by the pattern to a back surface, of the wafer, opposite to the illumination side; and a signal processing section 51 which detects a state of the pattern based on at least one of the first and second detection signals.

Abstract: A method to determine the cleanness of a semiconductor substrate and the quantity/density of pin holes that may exist within a patterned antireflective coating (ARC) is provided. Electroplating is employed to monitor the changes in the porosity of the ARC caused by the pin holes during solar cell manufacturing. In particular, electroplating a metal or metal alloy to form a metallic grid on an exposed front side surface of a substrate also fills the pin holes. The quantity/density of metallic filled pin holes (and hence the number of pin holes) in the patterned ARC can then be determined.

Abstract: A metrology system for gauging and spatially mapping a semiconductor material on a substrate can be used in controlling deposition and thermal activation processes.

Abstract: A method of processing a substrate having integrated circuitry includes forming through-substrate vias partially through the substrate from a first side of the substrate. At least one through-substrate structure is formed partially through the substrate from the first substrate side. The at least one through-substrate structure extends deeper into the substrate than do the through-substrate vias. Substrate material is removed from a second side of the substrate to expose the through-substrate vias and the at least one through-substrate structure on the second substrate side. Additional implementations are disclosed. Integrated circuit substrates are disclosed independent of method of manufacture.

Abstract: A method, a system and a computer program product suitable for use in a manufacturing environment comprising a multiplicity of nominally identical independent tools. A computing device generates a multi dimensional array of process trace data derived from at least one of the independent tools, wherein, the array includes data representing a first dimension comprising a list of steps in a manufacturing recipe and data representing a second dimension comprising a list of a set of sensors generating measurements from at least one of the independent tools. The computing device conducts an analysis on at least one preselected subset of the multi dimensional array for the purpose of evaluating at least one operating characteristic of at least one of the independent tools. The computing device presents results of the analysis via a set of hierarchically linked and browseable graphics.

Abstract: A method comprises providing a semiconductor substrate having a first layer and a second layer above the first layer. The first layer haw a plurality of first patterns, vias or contacts. The second layer has second patterns corresponding to the first patterns, vias or contacts. The second patterns have a plurality of in-plane offsets relative to the corresponding first patterns, vias or contacts. A scanning electron microscope is used to measure line edge roughness (LER) values of the second patterns. An overlay error is calculated between the first and second layers based on the measured LER values.

Abstract: A method for forming a dual damascene structure is disclosed. First a substrate is provided. There are an etching stop layer and an interlayer dielectric layer disposed on the substrate in order. The interlayer dielectric layer has a thickness A. Second, the interlayer dielectric layer is patterned to form a first opening. Later, a photo resist layer with a thickness B is formed on the interlayer dielectric layer. Then, the photo resist layer is patterned by a light source to construct a patterned photo resist layer. Later, the interlayer dielectric layer is again patterned by the patterned photo resist to pattern the interlayer dielectric layer to construct a second opening on the first opening by means of a light source and the photo resist layer so as to form a dual damascene structure. The light source has a periodic parameter C so that (A+B)/C?X/2, where X is an odd number.

Abstract: A method for analyzing molecular pollutants of a fluid. From a calibrated flow of fluid, a combination of a measurement of a total amount of molecular pollutants and a determination of chemical compositions and relative amounts of the molecular pollutants by adsorption on materials is carried out. The determination of the chemical compositions and relative amounts advantageously occur after a threshold value for the total measured amount is exceeded.

Abstract: A technique is provided which can exactly recognize a chip to be picked up when picking up the chip from a wafer sheet in a process of die bonding a thin chip. A camera is coupled to one end of a lens barrel, an objective lens is attached to an opposite end of the lens barrel, and an image of a main surface of a chip is photographed through the objective lens. A surface-emitting lighting unit, a diffusing plate and a half mirror are internally provided between the lens barrel and the chip. Further, another lens barrel having a coaxial drop lighting function of radiating light to the main surface of the chip along the same optical axis as that of the camera is disposed.

Abstract: In manufacturing light emitting element packages by coating the top surfaces of LED elements with the resin containing the fluorescent substance, in a resin supplying operation of discharging to supply the resin onto the LED elements in a wafer state, the light emission characteristics of the light that the resin emits when excitation light from a light source part is irradiated onto a light-passing member on which the resin is test supplied for light emission characteristic measurement are measured, and the appropriate resin supply quantity is revised based on the result of the measurement and light emission characteristics prescribed beforehand, to derive an appropriate resin supply quantity of the resin which should be supplied to the LED elements for practical production.

Abstract: A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.

Abstract: A method of controlling a polishing operation includes polishing a substrate, during polishing obtaining a sequence over time of measured spectra from the substrate with an in-situ optical monitoring system, for each measured spectrum from the sequence of measured spectra applying a Fourier transform to the measured spectrum to generate a transformed spectrum thus generating a sequence of transformed spectra, for each transformed spectrum identifying a peak of interest from a plurality of peaks in the transformed spectrum, for each transformed spectrum determining a position value for the peak of interest in the transformed spectrum thus generating a sequence of position values, and determining at least one of a polishing endpoint or an adjustment of a pressure to the substrate from the sequence of position values.

Abstract: Methods, devices, systems and/or articles related to techniques for forming a graphene film on a substrate, and the resulting graphene layers and graphenated substrates are generally disclosed. Some example techniques may be embodied as methods or processes for forming graphene. Some other example techniques may be embodied as devices employed to manipulate, treat, or otherwise process substrates, graphite, graphene and/or graphenated substrates as described herein. Graphene layers and graphenated substrates produced by the various techniques and devices provided herein are also disclosed.

Abstract: PICA test methods are shown that includes forming semiconductor devices having proximal light emitting regions, such that the light emitting regions are grouped into distinct shapes separated by a distance governed by a target resolution size; forming logic circuits to control the semiconductor devices; activating the one or more semiconductor devices by providing an input signal; and suppressing light emissions from one or more of the activated semiconductor devices by providing one or more select signals to the logic circuits.

Abstract: Methods for tracking the identity of die after singulation from a wafer. The product chips and die include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification used to fabricate the die and a product chip location for the die on a wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging.

Abstract: A method of controlling a polishing operation includes polishing a substrate, during polishing obtaining a sequence over time of measured spectra from the substrate with an in-situ optical monitoring system, for each measured spectrum from the sequence of measured spectra applying a Fourier transform to the measured spectrum to generate a transformed spectrum thus generating a sequence of transformed spectra, for each transformed spectrum identifying a peak of interest from a plurality of peaks in the transformed spectrum, for each transformed spectrum determining a position value for the peak of interest in the transformed spectrum thus generating a sequence of position values, and determining at least one of a polishing endpoint or an adjustment of a pressure to the substrate from the sequence of position values.

Abstract: A method for forming a light-emitting device of the present application comprises providing a wafer; forming a first plurality of light-emitting elements on the wafer; providing a first connection structure to connect each of the first plurality of light-emitting elements; and applying a current flow to one of the first plurality of light-emitting elements for testing at least one electrical property of the light-emitting element while no current flow is applied to the remaining of the first plurality of light-emitting elements.

Abstract: An object is to provide a method for manufacturing a lighting device, in which a problem of a short circuit between an upper electrode and a lower electrode of a light-emitting element is solved without reducing a light-emitting property of a normal portion of the light-emitting element to the utmost. In a light-emitting element including an upper electrode, an electroluminescent layer, and a lower electrode, a short-circuited portion that is undesirably formed between the upper electrode and the lower electrode is irradiated with a laser beam, whereby a region where the short-circuited portion is removed is formed, and then the region is filled with an insulating resin having a light-transmitting property. Thus, the problem of the short circuit between the upper electrode and the lower electrode is solved and yield of a lighting device is improved.

Abstract: Inspection guided overlay metrology may include performing a pattern search in order to identify a predetermined pattern on a semiconductor wafer, generating a care area for all instances of the predetermined pattern on the semiconductor wafer, identifying defects within generated care areas by performing an inspection scan of each of the generated care areas, wherein the inspection scan includes a low-threshold or a high sensitivity inspection scan, identifying overlay sites of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique, comparing location data of the identified defects of a generated care area to location data of the identified overlay sites within the generated care area in order to identify one or more locations wherein the defects are proximate to the identified overlay sites, and generating a metrology sampling plan based on the identified locations.

Abstract: A whole determination area of a targeted wafer is concentrically divided in a radial direction, COP density is obtained in each divided determination segment, a maximum value of the COP density is set as COP densityRADIUSMAX, a minimum value of the COP density is set as COP densityRADIUSMIN, a value computed by “(COP densityRADIUSMAX-COP densityRADIUSMIN)/COP densityRADIUSMAX” is compared to a predetermined set value, and a non-crystal-induced COP and a crystal-induced COP are distinguished from each other based on a clear criterion, thereby determining the COP generation factor. Therefore, a rejected wafer in which a determination of the crystal-induced COP is made despite being the non-crystal-induced COP can be relieved, so that a wafer production yield can be enhanced.

Abstract: The present disclosure involves a method of fabricating a light-emitting diode (LED) wafer. The method first determines a target surface morphology for the LED wafer. The target surface morphology yields a maximum light output for LEDs on the LED wafer. The LED wafer is etched to form a roughened wafer surface. Thereafter, using a laser scanning microscope, the method investigates an actual surface morphology of the LED wafer. Afterwards, if the actual surface morphology differs from the target surface morphology beyond an acceptable limit, the method repeats the etching step one or more times. The etching is repeated by adjusting one or more etching parameters.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate and an interconnect structure disposed over the substrate. The interconnect structure includes a plurality of interconnect layers. One of the interconnect layers contains: a plurality of metal via slots and a bulk metal component disposed over the plurality of metal via slots. The present disclosure also provides a method. The method includes providing a wafer, and forming a first layer over the wafer. The method includes forming an interconnect structure over the first layer. The forming the interconnect structure includes forming a second interconnect layer over the first layer, and forming a third interconnect layer over the second interconnect layer. The second interconnect layer is formed to contain a plurality of metal via slots and a bulk metal component formed over the plurality of metal via slots. The third interconnect layer contains one or more metal trenches.

Abstract: The present invention provides an evaluation substrate for evaluating a foreign object defect included in an organic material, a defect examination method and defect detection device. The evaluation substrate of the present invention includes a substrate, a first film arranged on the substrate, and a second film arranged on the first film, wherein a film containing an organic material is formed on the second film; the first film being set lower than an etching rate of the second film with respect to an etchant used in etching the second film, the first film having the same or a smaller detection lower limit value of an optically detectable defect than a detection lower limit value of a defect of the second film; and a thickness of the second film being set to a value near an optically measured lowest or minimum Haze value.

Abstract: Method form via chain and serpentine/comb test structures in kerf areas of a wafer. The via chain test structures comprise a first via chain and a second via chain in a first kerf area. The via chain test structures are formed such that geometrically shaped portions of the first via chain and geometrically shaped portions of the second via chain alternate along the length of the first kerf area. The methods perform relatively low (first) magnification testing to identify a defective geometrically shaped portion that contains a defective via structure. The methods then perform relatively high (second) magnification testing only within the defective geometrically shaped portion. The first magnification testing is performed at a lower magnification relative to the second magnification testing.

Abstract: To provide an integrated circuit with functionality under environment with temperature lower than a working condition, the integrated circuit is designed to include a heating element incorporated with signal pins on a carrier, such as a lead frame, that supports a chip die and controlled by a heating control unit to increase temperature of the chip die. The heating control unit provides voltage for the heating element when a detecting unit detects that the temperature of the chip die falls below a predetermined temperature and a power control unit provide operation power for the chip die when the temperature of the chip die detected by the detecting unit reaches or falls above the predetermined temperature.

Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units.

Abstract: A substrate bonding apparatus is equipped with a first table that holds one wafer of two wafers, a stage device that holds the other wafer in an orientation capable of opposing to the one wafer and that is movable at least within an XY plane, an interferometer system that measures positional information of the stage device within the XY plane, a first mark detection system that can detect subject marks including alignment marks on the other wafer held by the stage device, and a second mark detection system fixed to a part (the second table) of the stage device that can detect subject marks including alignment marks on the one wafer held by the first table.

Abstract: An integrated circuit structure includes a work piece selected from the group consisting of a semiconductor chip and a package substrate. The work piece includes a plurality of under bump metallurgies (UBMs) distributed on a major surface of the work piece; and a plurality of metal bumps, with each of the plurality of metal bumps directly over, and electrically connected to, one of the plurality of UBMs. The plurality of UBMs and the plurality of metal bumps are allocated with an overlay offset, with at least some of the plurality of UBMs being misaligned with the respective overlying ones of the plurality of metal bumps.

Abstract: A method is provided including depositing a layer of material on a substrate, during deposition of the material, at a predetermined depth, laterally implanting a first dopant and a second dopant in the material, the second dopant being different from the first dopant, etching the material, during etching, detecting the positions and intensities of the first and second dopants, and calculating lateral homogeneity of the material in situ from the intensities of the first and second dopants.

Abstract: A method to determine the cleanness of a semiconductor substrate and the quantity/density of pin holes that may exist within a patterned antireflective coating (ARC) is provided. Electroplating is employed to monitor the changes in the porosity of the ARC caused by the pin holes during solar cell manufacturing. In particular, electroplating a metal or metal alloy to form a metallic grid on an exposed front side surface of a substrate also fills the pin holes. The quantity/density of metallic filled pin holes (and hence the number of pin holes) in the patterned ARC can then be determined.

Abstract: A photodiode array for near infrared rays that includes photodiodes having a uniform size and a uniform shape, has high selectivity for the wavelength of received light between the photodiodes, and has high sensitivity with the aid of a high-quality semiconducting crystal containing a large amount of nitrogen, a method for manufacturing the photodiode array, and an optical measurement system are provided. The steps of forming a mask layer 2 having a plurality of openings on a first-conductive-type or semi-insulating semiconductor substrate 1, the openings being arranged in one dimension or two dimensions, and selectively growing a plurality of semiconductor layers 3a, 3b, and 3c including an absorption layer 3b in the openings are included.

Abstract: A method, apparatus, and a system for performing an adaptive state estimation process for processing semiconductor wafers. A processing of a first workpiece is controlled using a process controller and a processing tool. Manufacturing data relating to the processing of the first workpiece is acquired. Status data relating to the manufacturing data is acquired. The status data includes data relating to the source of the manufacturing data. A state of a process controller or a processing tool is determined based upon the status data and the manufacturing data.

Abstract: A thin overlay structure for use in imaging based metrology is disclosed. The thin overlay structure may include a first structure and second structure, the first and second structures designed to have a common center of symmetry, both structures being invariant to a 180 degree rotation about the common center of symmetry, wherein a mark region defining the extent of the structures is characterized by a first direction and a second direction orthogonal to the first direction, a length of the mark region along the first direction being greater than a length of the mark region along the second direction.

Abstract: In certain desirable embodiments, the present invention relates to the use of 15N isotopes into GaAsN, InAsN or GaSbN films for ion beam analysis. A semiconductor-nitride assembly for growing and analyzing crystal growth in a group III-V semiconductor sample that includes: a substrate; a buffer layer deposited on the substrate, a nitrogen gas injector to incorporate enriched nitrogen gas and the nitrogen gas injector includes a concentration of enriched nitrogen gas, a thin film consisting of at least one group III element containing compound where at least one group III element is covalently bonded with the nitrogen in the presence of the same or different group V element of the buffer layer, and a proton beam to analyze the incorporation of the nitrogen gas in the thin film layer is described.

Abstract: A wafer containing a plurality of electro-optical devices, each device being enclosed in chamber that has a translucent cover. An X-Y matrix of pairs of interconnections on the wafer are connected to the circuitry of the electro-optical devices for addressing the electro-optical devices. The pairs of interconnections extend outside of the chambers enclosing the devices to testing areas on the periphery of the wafer. Testing is done by signals applied through the interconnections while simultaneously exposing the devices to light through the translucent covers.

Abstract: A substrate treatment apparatus configured such that substrates in a same lot are distributed by a delivery mechanism into a plurality of unit blocks, each unit block including a solution treatment module, an ultraviolet irradiation module, and a substrate carrying mechanism, the apparatus includes: an illuminance detection part that detects an illuminance of a light source of the ultraviolet irradiation module; and a control part that controls, when an illuminance detection value of the ultraviolet irradiation module in one unit block among the plurality of unit blocks becomes a set value or less, the delivery mechanism to stop delivery of a substrate to the one unit block and deliver subsequent substrates to another unit block, and the ultraviolet irradiation module to perform irradiation on substrates which have already been delivered to the one unit block with an irradiation time adjusted to a length according to the illuminance detection value.

Abstract: A semiconductor package test apparatus having a test head and a test handler is provided. The semiconductor package test apparatus may include an insert in which a plurality of semiconductor packages are stacked and received in an offset fashion. Further, the semiconductor package test apparatus may include a plurality of sockets located adjacent to the insert and each of the inserts may have a plurality of socket pins. The sockets have different surface levels and are aligned with the semiconductor packages.

Abstract: A method of manufacturing a plurality of semiconductor wafers comprising micro-inspecting at least one location within at least one micro-inspected pattern field and determining at least one parameter value representing a property of the wafer at the micro-inspected location, macro-inspecting a plurality of locations within the at least one micro-inspected pattern field and determining, for each macro-inspected location of the macro-inspected pattern field, at least one parameter value representing the property of the wafer at the macro-inspected location based on the light intensity recorded for the macro-inspected location and on the at least one parameter value representing the property of the wafer at the micro-inspected location of this pattern field.

Abstract: This invention discloses a defect isolation method for thin-film solar cell having at least a defect therein. The thin-film solar cell comprises a substrate, a front electrode layer, an absorber layer and a back electrode layer stacked in such a sequence. The defect isolation method includes the steps of: detecting at least a defect formed in thin-film solar cell and acquiring the positions of the defects, and applying a laser light to scribe the outer circumference of the defects according to the positions of the defects so as to form at least an isolation groove having a closed-curve configuration.

Abstract: Methods of forming conductive patterns include forming a conductive layer including a metal element on a substrate. The conductive layer is partially etched to generate a residue including an oxide of the metal element and to form a plurality of separately formed conductive layer patterns. A cleaning gas is inflowed onto the substrate including the conductive layer pattern. The metal compound is evaporated to remove the metal element contained in the residue and to form an insulating interface layer on the conductive layer pattern and a surface portion of the substrate through a reaction of a portion of the cleaning gas and oxygen. The residue may be removed from the conductive layer pattern to suppress generation of a leakage current.