And Passive Electrical Device (e.g., Resistor, Capacitor, Etc.) Patents (Class 438/171)
  • Patent number: 10367074
    Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: July 30, 2019
    Assignee: Cree, Inc.
    Inventors: Zoltan Ring, Scott Thomas Sheppard, Helmut Hagleitner
  • Patent number: 10256134
    Abstract: An integrated circuit (IC) structure is disclosed. The structure can include: a first heat dissipative element disposed between a pair of shallow trench isolations (STIs) in a substrate, and a first polysilicon resistor in a polysilicon layer positioned over the substrate and the pair of STIs, the first polysilicon resistor in thermal communication with the first heat dissipative element. The structure can also include a second polysilicon resistor in the polysilicon layer, the second polysilicon resistor laterally separated from the first polysilicon resistor, and the first heat dissipative element in thermal communication with the first polysilicon resistor and the second polysilicon element. The structure can also include a second heat dissipative element, the second heat dissipative element in a different directional orientation than the first heat dissipative element.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: April 9, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ricardo P. Mikalo, Martin Gerhardt
  • Patent number: 10249616
    Abstract: One illustrative method disclosed herein includes, among other things, forming first and second adjacent gates above a semiconductor substrate, each of the gates comprising a gate structure and a gate cap, forming a conductive resistor structure between the first and second adjacent gates, the conductive resistor structure having an uppermost surface that is positioned at a level that is below a level of an uppermost surface of the gate caps of the first and second adjacent gates, and forming first and second separate conductive resistor contact structures, each of which is conductively coupled to the conductive resistor structure.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: April 2, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Manfred Eller, Haiting Wang, Daniel Jaeger
  • Patent number: 9105571
    Abstract: Techniques for fabricating self-aligned contacts in III-V FET devices are provided. In one aspect, a method for fabricating a self-aligned contact to III-V materials includes the following steps. At least one metal is deposited on a surface of the III-V material. The at least one metal is reacted with an upper portion of the III-V material to form a metal-III-V alloy layer which is the self-aligned contact. An etch is used to remove any unreacted portions of the at least one metal. At least one impurity is implanted into the metal-III-V alloy layer. The at least one impurity implanted into the metal-III-V alloy layer is diffused to an interface between the metal-III-V alloy layer and the III-V material thereunder to reduce a contact resistance of the self-aligned contact.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: August 11, 2015
    Assignee: International Business Machines Corporation
    Inventors: Christian Lavoie, Uzma Rana, Devendra K. Sadana, Kuen-Ting Shiu, Paul Michael Solomon, Yanning Sun, Zhen Zhang
  • Patent number: 9029180
    Abstract: A method of producing a temperature sensing device is provided. The method includes forming at least one silicon layer and at least one electrode or contact to define a thermistor structure. At least the silicon layer is formed by printing, and at least one of the silicon layer and the electrode or contact is supported by a substrate during printing thereof. Preferably, the electrodes or contacts are formed by printing, using an ink comprising silicon particles having a size in the range 10 nanometers to 100 micrometers, and a liquid vehicle composed of a binder and a suitable solvent. In some embodiments the substrate is an object the temperature of which is to be measured. Instead, the substrate may be a template, may be sacrificial, or may be a flexible or rigid material. Various device geometries are disclosed.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: May 12, 2015
    Assignee: PST Sensors (Proprietary) Limited
    Inventors: David Thomas Britton, Margit Harting
  • Patent number: 9018060
    Abstract: A variable capacitance sensor includes a first conductive electrode comprising electrically interconnected first conductive sheets; a second conductive electrode comprising electrically interconnected second conductive sheets, wherein the first conductive sheets are at least partially interleaved with the second conductive sheets, and wherein the second conductive electrode is electrically insulated from the first conductive electrode; and microporous dielectric material at least partially disposed between and contacting the first conductive sheets and the second conductive sheets. A method of making a variable capacitance sensor by replacing ceramic in a ceramic capacitor with a microporous material is also disclosed.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: April 28, 2015
    Assignee: 3M Innovative Properties Company
    Inventors: Stefan H. Gryska, Michael C. Palazzotto
  • Patent number: 9006703
    Abstract: Aspects of the present invention relate to method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof. Various embodiments include a method for reducing lateral extrusion formed in semiconductor structures. The method can include removing a portion of a first lateral extrusion in an aluminum layer of the semiconductor structure, and determining a post-removal thickness of a dielectric layer positioned adjacent the aluminum layer. The post-removal thickness may be determined subsequent to the removing of the portion of the first lateral extrusion. The method can also include determining a difference between the post-removal thickness of the dielectric layer and a pre-removal thickness of the dielectric layer.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Shawn A. Adderly, Brian M. Czabaj, Daniel A. Delibac, Jeffrey P. Gambino, Matthew D. Moon, David C. Thomas
  • Patent number: 8993396
    Abstract: A method for fabricating a capacitor includes forming a mold structure over a substrate, wherein the mold structure has a plurality of open parts and has a mold layer stacked with a support layer; forming cylinder type lower electrodes in the open parts; forming a first upper electrode over an entire surface of a structure including the cylinder type lower electrodes to fill the cylinder type lower electrodes; defining a through hole that passes through portions of the first upper electrode and the support layer; removing the mold layer through the through hole and exposing the cylinder type lower electrodes; forming a second upper electrode to fill the through hole and spaces between the cylinder type lower electrodes; and forming a third upper electrode to connect the second upper electrode and the first upper electrode with each other.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: March 31, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jong-Kook Park, Yong-Tae Cho
  • Patent number: 8975133
    Abstract: One illustrative integrated circuit product disclosed herein includes a metal-1 metallization layer positioned above a semiconducting substrate, a capacitor positioned between a surface of the substrate and a bottom of the metal-1 metallization layer, wherein the capacitor includes a plurality of conductive plates that are oriented in a direction that is substantially normal relative to the surface of the substrate, and at least one region of insulating material positioned between the plurality of conductive plates.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: March 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kok Yong Yiang, Patrick R. Justison
  • Patent number: 8970003
    Abstract: System and method for embedded passive integration relating to a multi-chip packaged device. The packaged device includes a capacitance layer that is configured for electrical coupling to a power supply and to a reference power supply. Further, the capacitance layer is configured for filtering the power supply and providing a filtered power supply. A semiconductor layer including a logic device is configured for electrical coupling to the filtered power supply.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: March 3, 2015
    Assignee: Tessera, Inc.
    Inventor: Michael Curtis Parris
  • Patent number: 8916426
    Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: William F. Clark, Jr., Robert J. Gauthier, Jr., Terence B. Hook, Junjun Li, Theodorus E. Standaert, Thomas A. Wallner
  • Patent number: 8865518
    Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: October 21, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Nitin Kumar, Tony P. Chiang, Chi-I Lang, Zhi-Wen Wen Sun, Jihong Tong
  • Patent number: 8815695
    Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. A second electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the second electrode layer contains a conductive base layer and conductive metal oxide layer. In some embodiments, both the first electrode layer and the second electrode layer contain a conductive base layer and conductive metal oxide layer.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: August 26, 2014
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Xiangxin Rui, Mitsuhiro Horikawa, Hiroyuki Ode, Karthik Ramani
  • Patent number: 8796087
    Abstract: A semiconductor device including a substrate; a bottom electrode on the substrate; a first dielectric layer on the bottom electrode, the first dielectric layer including a first metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb; a second dielectric layer on the first dielectric layer, the second dielectric layer including a second metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb, wherein the first metal oxide and the second metal oxide are different materials; a third dielectric layer on the second dielectric layer, the third dielectric layer including a metal carbon oxynitride; and an upper electrode on the third dielectric layer.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: August 5, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Weon-Hong Kim, Min-Woo Song, Jung-Min Park
  • Patent number: 8790989
    Abstract: A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: July 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Louis L. Hsu, Xu Ouyang, Chih-Chao Yang
  • Patent number: 8766410
    Abstract: Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Josephine Chang, Leland Chang, Brian L. Ji, Steven John Koester, Amlan Majumdar
  • Patent number: 8748988
    Abstract: A semiconductor device has a semiconductor substrate, a field insulating film disposed on a surface of the semiconductor substrate, a base insulating film disposed on a surface of the field insulating film, and a resistor disposed on the base insulating film. The resistor is formed of a polycrystalline silicon film and has a resistance region and electrode lead-out regions disposed at both ends of the resistance region. A portion of the base insulating film below the resistance region projects with respect to portions of the base insulating film below the electrode lead-out regions so that a height difference occurs therebetween. The resistance region has a thickness thinner than that of each of the electrode lead-out regions.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: June 10, 2014
    Assignee: Seiko Instruments Inc.
    Inventor: Yuichiro Kitajima
  • Patent number: 8748282
    Abstract: A semiconductor device is manufactured by forming a hole as being extended through a first insulating film and an insulating interlayer stacked over a semiconductor substrate, allowing side-etching of the inner wall of the hole to proceed specifically in a portion of the insulating interlayer, to thereby form a structure having the first insulating film projected out from the edge towards the center of the hole; forming a lower electrode film as being extended over the top surface, side face and back surface of the first insulating film, and over the inner wall and bottom surface of the hole; filling a protective film in the hole; removing the lower electrode film specifically in portions fallen on the top surface and side face of the first insulating film; removing the protective film; and forming a cylindrical capacitor in the hole.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: June 10, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Ryo Kubota, Nobutaka Nagai, Satoshi Kura
  • Patent number: 8722475
    Abstract: A method for forming a variable capacitor includes providing a semiconductor substrate of a first conductivity type and forming an active region of a second conductivity type within the substrate. The method forms a first dielectric layer overlying the active region. The method provides a conductive gate layer over the first dielectric layer and selectively patterns the conductive gate layer to form a plurality of holes in the conductive gate layer. A perimeter of the holes and a spacing between a first and a second holes are selective to provide a high quality factor (Q) of the capacitor. The method implants impurities of the second conductivity type into the active region through the plurality of holes in the conductive layer. The method also includes providing a second dielectric layer and patterning the second dielectric layer to form contacts to the active region and the gate.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: May 13, 2014
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Zhen Chen, Yung Feng Lin
  • Patent number: 8710593
    Abstract: A manufacturing method for a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor, a transitional structure, and a dielectric layer covering the transistor and the transitional structure formed thereon, forming a recess in between two opposite polysilicon end portions in the transitional structure, forming a U-shaped resistance modulating layer and an insulating layer filling the recess, removing a dummy gate of the transistor and the polysilicon end portions of the transitional structure to form a gate trench and two terminal trenches respectively in the transistor and the transitional structure, and forming a metal gate in the gate trench and conductive terminals in the terminal trenches simultaneously.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: April 29, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chi-Sheng Tseng, Yao-Chang Wang, Jie-Ning Yang
  • Patent number: 8701283
    Abstract: A method for producing an integrated device including a capacitor. The method includes the steps of providing a functional substrate including functional circuits of the integrated device, forming a first conductive layer including a first plate of the capacitor on the functional substrate, forming a layer of insulating material including a dielectric layer of the capacitor on a portion of the first conductive layer corresponding to the first plate, forming a second conductive layer including a second plate of the capacitor and functional connections to the functional circuits on a portion of the layer of insulating material corresponding to the dielectric layer, forming a protective layer of insulating material covering the second plate and the functional connections, forming a first contact for contacting the first plate, and forming a second contact and functional contacts for contacting the second plate and the functional connections, respectively, through the protective layer.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: April 22, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventor: Alessandro Dundulachi
  • Patent number: 8698251
    Abstract: An organic light emitting diode display includes a substrate, a semiconductor layer on the substrate, the semiconductor layer including an impurity-doped polycrystalline silicon layer, a first capacitor electrode on the substrate main body, the first capacitor electrode including an impurity-doped polycrystalline silicon layer, and bottom surfaces of the first capacitor electrode and semiconductor layer facing the substrate main body being substantially coplanar, a gate insulating layer on the semiconductor layer and the first capacitor electrode, a gate electrode on the semiconductor layer with the gate insulating layer therebetween, and a second capacitor electrode on the first capacitor electrode with the gate insulating layer therebetween, bottom surfaces of the second capacitor electrode and gate electrode facing the substrate main body being substantially coplanar, and the second capacitor electrode having a smaller thickness than the gate electrode.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: April 15, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Oh-Seob Kwon, Moo-Soon Ko
  • Patent number: 8692291
    Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device structure is formed that includes a well of a first conductivity type in a device region and a doped region of a second conductivity in the well. The device region is comprised of a portion of a device layer of a semiconductor-on-insulator substrate. The doped region and a first portion of the well define a junction. A second portion of the well is positioned between the doped region and an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: April 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: William F. Clark, Jr., Robert J. Gauthier, Jr., Junjun Li
  • Patent number: 8664741
    Abstract: Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: March 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
  • Patent number: 8627258
    Abstract: According to one exemplary embodiment, a method for adjusting geometry of a capacitor includes fabricating a first composite capacitor residing in a first standard cell with a first set of process parameters. The method further includes using a second standard cell having substantially same dimensions as the first standard cell. The method further includes using a capacitance value from the first composite capacitor to adjust a geometry of a second composite capacitor residing in the second standard cell, wherein the second composite capacitor is fabricated with a second set of process parameters. The geometry of the second composite capacitor can be adjusted to cause the second composite capacitor to have a capacitance value substantially equal to the capacitance value from the first composite capacitor.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: January 7, 2014
    Assignee: Broadcom Corporation
    Inventors: Peter Huang, Ming-Chun Chen
  • Patent number: 8627259
    Abstract: According to one exemplary embodiment, a method for adjusting geometry of a capacitor includes fabricating a first composite capacitor residing in a first standard cell with a first set of process parameters. The method further includes using a second standard cell having substantially same dimensions as the first standard cell. The method further includes using a capacitance value from the first composite capacitor to adjust a geometry of a second composite capacitor residing in the second standard cell, wherein the second composite capacitor is fabricated with a second set of process parameters. The geometry of the second composite capacitor can be adjusted to cause the second composite capacitor to have a capacitance value substantially equal to the capacitance value from the first composite capacitor.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: January 7, 2014
    Assignee: Broadcom Corporation
    Inventors: Peter Huang, Ming-Chun Chen
  • Patent number: 8618523
    Abstract: On an insulating film (41) in which a plug (43) as a lower electrode is embedded, a laminated layer pattern of an insulating film (51) made of tantalum oxide, a recording layer (52) made of Ge—Sb—Te based chalcogenide to which indium is introduced and an upper electrode film (53) made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film (51) between the recording layer (52) and the plug (43), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer (52) can be achieved. Further, by using the Ge—Sb—Te based chalcogenide to which indium is introduced as the recording layer (52), the difference in work function between the insulating film (51) and the recording layer (52) is increased, and the programming voltage of the phase change memory can be reduced.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: December 31, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Norikatsu Takaura, Yuichi Matsui, Motoyasu Terao, Yoshihisa Fujisaki, Nozomu Matsuzaki, Kenzo Kurotsuchi, Takahiro Morikawa
  • Patent number: 8580627
    Abstract: A compound semiconductor device is provided, including a gallium arsenide (GaAs) substrate having a first protrusion portion and a second protrusion portion, wherein the first protrusion portion is formed over a first portion of the GaAs substrate and the second protrusion is formed over a second portion of the GaAs substrate. A first element is disposed over the first protrusion portion, and a second element is disposed over the second protrusion portion.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: November 12, 2013
    Assignee: RichWave Technology Corp.
    Inventors: Kuo-Jui Peng, Chuan-Jane Chao, Tsyr-Shyang Liou
  • Patent number: 8569769
    Abstract: An Enhancement-mode (E-mode) high electron mobility transistor (HEMT) includes a channel layer with a 2-Dimensional Electron Gas (2DEG), a barrier layer inducing the 2DEG in the channel layer, source and drain electrodes on the barrier layer, a depletion layer on the barrier layer between the source and drain electrodes, and a gate electrode on the depletion layer. The barrier layer is recessed below the gate electrode and the depletion layer covers a surface of the recess and extends onto the barrier layer around the recess.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: October 29, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-jun Hwang, Ki-ha Hong, Jong-seob Kim, Jae-Kwang Shin, Jae-joon Oh, Jong-bong Ha, Hyuk-soon Choi
  • Patent number: 8569127
    Abstract: A method for fabricating a semiconductor device is described. A substrate having thereon a polysilicon resistor is provided. A dielectric layer is formed over the substrate covering the polysilicon resistor. The dielectric layer is etched to form a contact opening over the polysilicon resistor, with overetching into the polysilicon resistor. A metal silicide layer is formed on the polysilicon resistor in the contact opening. A metal material is filled in the contact opening. A portion of the dielectric layer, the metal material, and a portion of the polysilicon resistor are removed to expose the metal silicide layer. A metal contact is formed over the metal silicide layer.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: October 29, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Yang Chen, Chen-Hua Tsai, Shih-Fang Hong, Po-Chao Tsao, Ming-Te Wei
  • Patent number: 8530288
    Abstract: Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: September 10, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Kunal R. Parekh
  • Patent number: 8476107
    Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: July 2, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Nitin Kumar, Chi-I Lang, Tony Chiang, Zhi-Wen Sun, Jinhong Tong
  • Patent number: 8450163
    Abstract: In a replacement gate approach, the semiconductor material or at least a significant portion thereof in a non-transistor structure, such as a precision resistor, an electronic fuse and the like, may be preserved upon replacing the semiconductor material in the gate electrode structures. To this end, an appropriate dielectric material may be provided at least prior to the removal of the semiconductor material in the gate electrode structures, without requiring significant modifications of established replacement gate approaches.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: May 28, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sven Beyer, Klaus Hempel, Roland Stejskal, Andy Wei, Thilo Scheiper, Andreas Kurz, Uwe Griebenow, Jan Hoentschel
  • Patent number: 8409933
    Abstract: The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: April 2, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Gurtej S. Sandhu, H. Montgomery Manning
  • Patent number: 8410577
    Abstract: The invention provides a semiconductor device which has a capacitor element therein to achieve size reduction of the device, the capacitor element having larger capacitance than conventional. A semiconductor integrated circuit and pad electrodes are formed on the front surface of a semiconductor substrate. A second insulation film is formed on the side and back surfaces of the semiconductor substrate, and a capacitor electrode is formed between the back surface of the semiconductor substrate and the second insulation film, contacting the back surface of the semiconductor substrate. The second insulation film is covered by wiring layers electrically connected to the pad electrodes, and the wiring layers and the capacitor electrode overlap with the second insulation film being interposed therebetween. Thus, the capacitor electrode, the second insulation film and the wiring layers form capacitors.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: April 2, 2013
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Katsu Horikoshi, Hisayoshi Uchiyama, Takashi Noma, Yoshinori Seki, Hiroshi Yamada, Shinzo Ishibe, Hiroyuki Shinogi
  • Patent number: 8394696
    Abstract: A semiconductor device includes a capacitance, the numerical value of which is relevant for a device function. The capacitance is formed from a parallel connection of at least a first and a second capacitor element, wherein the first and second capacitor elements are formed in respective manufacturing steps that exhibit uncorrelated process fluctuations.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: March 12, 2013
    Assignee: Infineon Technologies AG
    Inventors: Peter Baumgartner, Philipp Riess, Thomas Benetik
  • Patent number: 8361848
    Abstract: A method includes forming a polysilicon layer on a substrate; and patterning the polysilicon layer to form a polysilicon resistor and a polysilicon gate. A first ion implantation is performed on the polysilicon resistor to adjust electric resistance of the polysilicon resistor. A second ion implantation is performed on a top portion of the polysilicon resistor such that the top portion of the polysilicon resistor has an enhanced etch resistance. An etch process is then used to remove the polysilicon gate while the polysilicon resistor is protected by the top portion.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: January 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Da-Yuan Lee, Matt Yeh
  • Patent number: 8339769
    Abstract: A method of making an electrolytic capacitor includes providing a first electrode that includes a metal substrate, a carbide layer, and a carbonaceous material. The metal substrate includes a metal selected from the group consisting of titanium, aluminum, tantalum, niobium, zirconium, silver, steel, and alloys and combinations thereof. The method further includes providing a second electrode and an electrolyte.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: December 25, 2012
    Assignees: Medtronic, Inc., Kemet Electronics Corporation
    Inventors: Joachim Hossick Schott, Brian Melody, John Tony Kinard
  • Patent number: 8288212
    Abstract: A method of fabricating a pixel structure of a thin film transistor liquid crystal display is provided. A transparent conductive layer and a first metallic layer are sequentially formed over a substrate. The first metallic layer and the transparent conductive layer are patterned to form a gate pattern and a pixel electrode pattern. A gate insulating layer and a semiconductor layer are sequentially formed over the substrate. A patterning process is performed to remove the first metallic layer in the pixel electrode pattern while remaining the gate insulating layer and the semiconductor layer over the gate pattern. A second metallic layer is formed over the substrate. The second metallic layer is patterned to form a source/drain pattern over the semiconductor layer. A passivation layer is formed over the substrate and then the passivation layer is patterned to expose the transparent conductive layer in the pixel electrode pattern.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: October 16, 2012
    Assignee: Au Optronics Corporation
    Inventors: Mao-Tsun Huang, Tzufong Huang
  • Patent number: 8269308
    Abstract: A semiconductor device is made by forming an oxide layer over a substrate and forming a first conductive layer over the oxide layer. The first conductive layer is connected to ground. A second conductive layer is formed over the first conductive layer as a plurality of segments. A third conductive layer is formed over the second conductive layer as a plurality of segments. If the conductive layers are electrically isolated, then a conductive via is formed through these layers. A first segment of the third conductive layer operates as a first passive circuit element. A second segment operates as a second passive circuit element. A third segment is connected to ground and operates as a shield disposed between the first and second segments. The shield has a height at least equal to a height of the passive circuit elements to block cross-talk between the passive circuit elements.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: September 18, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: YongTaek Lee, Gwang Kim, ByungHoon Ahn
  • Patent number: 8255858
    Abstract: According to one exemplary embodiment, a method for adjusting geometry of a capacitor includes fabricating a first composite capacitor residing in a first standard cell with a first set of process parameters. The method further includes using a second standard cell having substantially same dimensions as the first standard cell. The method further includes using a capacitance value from the first composite capacitor to adjust a geometry of a second composite capacitor residing in the second standard cell, wherein the second composite capacitor is fabricated with a second set of process parameters. The geometry of the second composite capacitor can be adjusted to cause the second composite capacitor to have a capacitance value substantially equal to the capacitance value from the first composite capacitor.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: August 28, 2012
    Assignee: Broadcom Corporation
    Inventors: Peter Huang, Ming-Chun Chen
  • Patent number: 8241986
    Abstract: The present invention, in one aspect, provides an integrated circuit that comprises a first region of transistors having gate structures with a low dopant concentration, and a second region of transistors having gate structures with a dopant concentration substantially higher than the gate structures of the first region, and wherein the transistors in the first region comprise a substantial portion of the integrated circuit. The transistors may include a resistor region located between an upper portion of the gate and the gate dielectric.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: August 14, 2012
    Assignee: Agere Systems Inc.
    Inventors: Taeho Kook, Tanya Nigam, Bonnie E. Weir
  • Patent number: 8227872
    Abstract: Example embodiments relate to a heterojunction diode, a method of manufacturing the heterojunction diode, and an electronic device including the heterojunction diode. The heterojunction diode may include a first conductive type non-oxide layer and a second conductive type oxide layer bonded to the non-oxide layer. The non-oxide layer may be a Si layer. The Si layer may be a p++ Si layer or an n++ Si layer. A difference in work functions of the non-oxide layer and the oxide layer may be about 0.8-1.2 eV. Accordingly, when a forward voltage is applied to the heterojunction diode, rectification may occur. The heterojunction diode may be applied to an electronic device, e.g., a memory device.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: July 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-hwan Kim, Young-bae Kim, Seung-ryul Lee, Young-soo Park, Chang-jung Kim, Bo-soo Kang
  • Patent number: 8206995
    Abstract: A method for manufacturing a resistive switching memory device comprises providing a substrate comprising an electrical contact, providing on the substrate a dielectric layer comprising a trench exposing the electrical contact, and providing in the trench at least the bottom electrode and the resistive switching element of the resistive memory device. The method may furthermore comprise providing a top electrode at least on or in the trench, in contact with the resistive switching element. The present invention also provides corresponding resistive switching memory devices.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: June 26, 2012
    Assignee: IMEC
    Inventors: Judit Gloria Lisoni Reyes, Ludovic Goux, Dirk Wouters
  • Patent number: 8187343
    Abstract: There are provided methods of manufacturing an electric double layer capacitor cell and an electric double layer capacitor and an apparatus for manufacturing an electric double layer capacitor cell.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: May 29, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sang Kyun Lee, Sung Ho Lee, Dong Sup Park, Yeong Su Cho, Chang Ryul Jung, Wan Suk Yang
  • Patent number: 8119446
    Abstract: An integrated chip package structure and method of manufacturing the same is by adhering dies on a metal substrate and forming a thin-film circuit layer on top of the dies and the metal substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: February 21, 2012
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee, Ching-Cheng Huang
  • Patent number: 8071433
    Abstract: A semiconductor component including: a substrate, at least one semiconductor chip arranged on the substrate and at least one passive device likewise arranged on the substrate. The passive device is mounted with its underside on the substrate. The semiconductor component further includes an interspace disposed between the underside of the passive device and the substrate. The interspace is filled with an underfilling material. In order to avoid the solder pumping effect, the upper side and the lateral sides of the passive device are also embedded in a plastic compound.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: December 6, 2011
    Assignee: Infineon Technologies AG
    Inventors: Erich Syri, Gerold Gruendler, Juergen Hoegerl, Thomas Killer, Volker Strutz
  • Patent number: 8058125
    Abstract: The present disclosure provides a poly resistor on a semiconductor device and a method of fabricating the same. In an embodiment, a poly silicon resistor device is formed by providing a substrate having a first region and a second region. A dummy gate stack is formed on the substrate in the first region, wherein the dummy gate stack has a dummy gate stack thickness extending above the substrate. A poly silicon resister is formed on the substrate in the second region, wherein the poly silicon resistor has a poly silicon resistor thickness extending above the substrate a distance which is less than the dummy gate stack thickness. A dopant is implanted into the substrate in the first region thereby forming a source region and a drain region in the first region of the substrate. The dopant is also implanted into the poly silicon resistor. An inter-level dielectric (ILD) layer is formed on the substrate over the dummy gate stack and also over the poly silicon resistor.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: November 15, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsien Lin, Inez Fu, Yimin Huang
  • Patent number: 8034642
    Abstract: A negative electrode of an electrochemical capacitor includes an electrode layer using a material capable of reversibly absorbing and releasing a lithium ion. A method for pretreating the negative electrode includes forming a lithium layer on a substrate by a gas phase method or a liquid phase method, and transferring the lithium layer onto a surface of the electrode layer of the negative electrode.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: October 11, 2011
    Assignee: Panasonic Corporation
    Inventors: Keiichi Kondou, Susumu Nomoto, Hideki Shimamoto
  • Patent number: 8030691
    Abstract: An MMIC 100 is a semiconductor device which includes an FET formed on a GaAs substrate 10 and an MIM capacitor having a dielectric layer 20b arranged between a lower electrode 18b and an upper electrode 22b. A method for manufacturing the MMIC 100 is provided, in which a source electrode 16a and a drain electrode 16b of the FET are formed and then a gate electrode 18a of the FET and a lower electrode 18b of the MIM capacitor are formed simultaneously by the lift-off method.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: October 4, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hisao Kawasaki