Abstract: Example embodiments of the invention may provide for a multi-package system. The multi-package system may include a first package having a plurality of first organic dielectric layers, where the first package includes at least one first conductive layer positioned between two of the plurality of first organic dielectric layers, and where the at least one first conductive layer is circuitized to form at least one first passive device. The multi-package system may also include a second package having a plurality of second organic dielectric layers, where the second package includes at least one second conductive layer positioned between two of the plurality of second organic dielectric layers, and where the at least one second conductive layer is circuitized to form at least one second passive device. An electrical connector may be provided between a bottom surface of the first package and a top surface of the second package to electrically connect the first package and the second package.

Abstract: Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.

Abstract: A method may include depositing a dielectric layer onto a substrate, removing portions of the dielectric layer to create a plurality of separated non-removed portions of the dielectric layer, depositing one or more passive electronic components into each of the plurality of separated non-removed portions, and curing the separated non-removed portions of the dielectric layer.

Abstract: A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates.

Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

Abstract: A semiconductor structure formation method and operation method. The structure includes (i) a dielectric layer, (ii) a bottom capacitor plate and an electrically conductive line on the dielectric layer, (iii) a top capacitor plate on top of the bottom capacitor plate, (iv) a gap region, and (v) a solder ball on the dielectric layer. The dielectric layer includes a top surface that defines a reference direction perpendicular to the top surface. The top capacitor plate overlaps the bottom capacitor plate in the reference direction. The gap region is sandwiched between the bottom capacitor plate and the top capacitor plate. The gap region does not include any liquid or solid material. The solder ball is electrically connected to the electrically conductive line. The top capacitor plate is disposed between the dielectric layer and the solder ball.

Abstract: The invention provides a manufacturing method for a semiconductor photoelectrochemical cell, comprising the steps of burning a base made of titanium or a titanium alloy in an atmosphere of 700° C. to 1000° C. at a rate of temperature increase of no lower than 5° C./second so that a titanium oxide layer is formed on the surface, and thus, mixing titanium metal into said titanium oxide layer.

Abstract: A semiconductor device including a metallic compound Hfx1Moy1Nz1 as an electrode. The work function of the electrode can be modulated by doping the metallic compound with dopants including nitrogen, silicon or germanium. The metallic compound of the present invention is applicable to PMOS, NMOS, CMOS transistors and capacitors.

Abstract: Methods for fabricating and testing integrated circuit devices and systems. The integrated circuit device generally includes two semiconductor dies. The first die has little or no I/O or ESD protection, and the second die includes at least one exposed terminal in electrical communication with one or more terminals on the first die, at least one I/O circuit in electrical communication with one or more terminals on the second die, and at least one I/O terminal in electrical communication with the I/O circuit(s). The method of forming an integrated circuit includes aligning at least one of the exposed terminals on the first die with at least one of the exposed terminals on the second die, and forming at least one electrical junction between them such that the exposed terminal(s) on the first die is/are in electrical communication with an I/O circuit and an I/O terminal on the second die.

Abstract: A semiconductor device includes a semiconductor substrate divided into a cell array region, a core region, and a peripheral region. Bit lines are formed in the respective regions. Storage node contact plugs are formed in the cell array region, and blocking patterns are simultaneously formed around the bit lines of the core region and the peripheral region. Capacitors are formed in the cell array region to come into contact with the storage node contact plugs, and metal contact plugs are formed to come into contact with the capacitors of the cell array region and the bit lines of the core region and the peripheral region. In the semiconductor device, even if the metal contact plugs are not aligned with the bit lines, the blocking pattern works to stabilize the contact between the metal contact plugs and the bit lines.

Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another.

Abstract: A semiconductor device according to an embodiment of the present invention includes: a transistor including, a gate insulator formed of an insulating layer deposited on a substrate, and a gate electrode formed of an electrode layer deposited on the insulating layer; a capacitor including, a first capacitor electrode formed of the electrode layer, a first capacitor insulator formed on the first capacitor electrode, a second capacitor electrode formed on the first capacitor insulator, a second capacitor insulator formed on the second capacitor electrode, and a third capacitor electrode formed on the second capacitor insulator; and line patterns which are in contact with a contact plug for the transistor, a contact plug for the first capacitor electrode, a contact plug for the second capacitor electrode, and the third capacitor electrode.

Abstract: Methods of forming an integrated circuit device may include forming an insulating layer on an integrated circuit substrate, forming a first conductive layer on the insulating layer, and forming a second conductive layer on the first conductive layer so that the first conductive layer is between the second conductive layer and the insulating layer. Moreover, the first conductive layer may be a layer of a first material, the second conductive layer may be a layer of a second material, and the first and second materials may be different. A hole may be formed in the second conductive layer so that portions of the first conductive layer are exposed through the hole. After forming the hole in the second conductive layer, the first and second conductive layers may be patterned so that portions of the first and second conductive layers surrounding portions of the first conductive layer exposed through the hole are removed while maintaining portions of the first conductive layer previously exposed through the hole.

Abstract: A semiconductor device may include a resistance pattern including a resistance material on a substrate. The resistance pattern may include first and second spaced apart base elements, a bridge element, and first, second, third, and fourth extension elements. The first and second base elements may be substantially parallel, and the bridge element may be connected between respective center portions of the first and second spaced apart base elements. The first and second extension elements may be connected to opposite ends of the first base element and may extend toward the second base element, and the third and fourth extension elements may be connected to opposite ends of the second base element and may extend toward the first base element. Related methods are also discussed.

Abstract: A semiconductor device includes a capacitor formed by successively stacking a lower electrode, a capacitor dielectric film and an upper electrode on a substrate. The lower electrode includes a first conducting layer and a second conducting layer formed on the first conducting layer and having higher resistivity than the first conducting layer, and the capacitor dielectric film is formed so as to be in contact with the second conducting layer of the lower electrode.

Abstract: A semiconductor component that includes an integrated passive device and method for manufacturing the semiconductor component. Vertically integrated passive devices are manufactured above a substrate. In accordance with one embodiment, a resistor is manufactured in a first level above a substrate, a capacitor is manufactured in a second level that is vertically above the first level, and a copper inductor is manufactured in a third level that is vertically above the second level. The capacitor has aluminum plates. In accordance with another embodiment, a resistor is manufactured in a first level above a substrate, a copper inductor is manufactured in a second level that is vertically above the first level, and a capacitor is manufactured in a third level that is vertically above the second level. The capacitor may have aluminum plates or a portion of the copper inductor may serve as one of its plates.

Abstract: Disclosed herein are a metal-ferroelectric-metal-substrate (MFMS) field-effect transistor (FET), an MFMS-ferroelectric memory device, and method of manufacturing the same. The MFMS-FET and the ferroelectric memory device in accordance with the present invention include: a substrate including source and drain regions, and a channel region formed therebetween; a buffer layer formed on the top of the channel region of the substrate; a ferroelectric layer formed on the buffer layer; and a gate electrode formed on the ferroelectric layer, wherein the buffer layer is formed of a conductive material.

Abstract: Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.

Abstract: The inductor for a semiconductor device comprises a first interlayer dielectric formed on a top of a silicon substrate, at least one first metal wire formed on a top of the first interlayer dielectric, a second interlayer dielectric formed on a top of the first interlayer dielectric to cover the first metal wire, at least one second metal wire formed on a top of the second interlayer dielectric and connected to the first metal wire, and an upper protective film formed on the top of the second interlayer dielectric to cover the second metal wire, wherein the first and second metal wires are alternately arranged and are formed in a spiral structure.

Abstract: An improved method for forming a capacitor. The method includes the steps of: providing a metal foil; forming a dielectric on the metal foil; applying a non-conductive polymer dam on the dielectric to isolate discrete regions of the dielectric; forming a cathode in at least one discrete region of the discrete regions on the dielectric; and cutting the metal foil at the non-conductive polymer dam to isolate at least one capacitor comprising one cathode, one discrete region of the dielectric and a portion of the metal foil with the discrete region of the dielectric.

Abstract: A method of forming an integrated circuit includes forming magnetic tunnel junction (MTJ) layers; etching the MTJ layers to form a MTJ cell; and forming a dielectric capping layer on sidewalls of the MTJ cell, wherein the step of forming the dielectric capping layer is in-situ performed with the step of etching the MTJ layers.

Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

Abstract: An organic electroluminescent display device having an organic thin film transistor (OTFT) and a method of fabricating the same is disclosed. The display device can maintain an insulation property of a TFT and concurrently, ensure a sufficient capacitance by using an organic insulating layer for a gate insulating layer and using an inorganic insulating layer for a capacitor dielectric. In one embodiment, the organic electroluminescent display device includes a substrate having a capacitor region and a transistor region, a TFT formed in the transistor region of the substrate, and having a gate electrode, an organic semiconductor layer, a source electrode, and a drain electrode, a capacitor formed in the capacitor region of the substrate, and having a lower electrode and an upper electrode, and a display element connected to one of source/drain electrodes of the TFT.

Abstract: The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.

Abstract: A method for integrally forming a metal-oxide-semiconductor (MOS) device and an electrical fuse device on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. A dielectric layer is deposited over the isolation structure and the semiconductor substrate. A metal layer is deposited on the dielectric layer. A polysilicon layer is deposited on the metal layer. The dielectric layer, the metal layer and the polysilicon layer are patterned into a first stack of the dielectric layer, the metal layer and the polysilicon layer on the isolation structure for functioning as the electrical fuse device, and a second stack of the dielectric layer, the metal layer and the polysilicon layer on the semiconductor substrate for functioning as a gate of the MOS device.

Abstract: Thick-film capacitors are formed on ceramic interconnect substrates having high capacitance densities and other desirable electrical and physical properties. The capacitor dielectrics are fired at high temperatures.

Abstract: A polycrystalline dielectric layer is formed wherein the dielectric layer comprises a first dielectric material containing an oxide or nitride and a second material contributing to less than 1% in weight to the dielectric layer, forming a non-conductive oxide or nitride having an enthalpy lower than the enthalpy of the first dielectric material such that a leakage current along grain boundaries of the first dielectric material is reduced.

Abstract: A very, very low resistance micro-electromechanical system (MEMS) inductor, which provides resistance in the single-digit milliohm range, is formed by utilizing a single thick wide loop of metal formed around a magnetic core structure. The magnetic core structure, in turn, can utilize a laminated Ni—Fe structure that has an easy axis and a hard axis.

Abstract: Structurally-stable, tall capacitors having unique three-dimensional architectures for semiconductor devices are disclosed. The capacitors include monolithically-fabricated upright microstructures, i.e., those having large height/width (H/W) ratios, which are mechanical reinforcement against shear forces and the like, by a brace layer that transversely extends between lateral sides of at least two of the free-standing microstructures. The brace layer is formed as a microbridge type structure spanning between the upper ends of the two or more microstructures.

Abstract: A semiconductor device includes a semiconductor substrate formed with a trench having a sidewall including a middle point. The trench includes a first part extending from a surface of the semiconductor substrate to the middle point of the trench and having a diameter that is gradually reduced as the first part extends deeper from the surface of the semiconductor substrate to the middle point of the trench. The trench includes a second part that is deeper than the middle point of the sidewall and that has a larger diameter than the middle point of the sidewall. An electrically conductive film is formed in an interior of the trench so as to be located lower than the middle point of the sidewall, the conductive film having a planarized upper surface, and a collar insulating film is formed on the conductive film and the sidewall of the trench so as to extend through the middle point of the sidewall along the sidewall.

Abstract: Methods are provided for manufacturing an electrode. In one exemplary embodiment, the method includes the steps of contacting the silver layer with vanadium oxide, and heating the silver layer and vanadium oxide in an oxygen-containing atmosphere to form a silver vanadium oxide layer chemically bonded to the metal substrate.

Abstract: The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Abstract: A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as a memory device. A method of forming the trap cites involves an atomic layer deposition of a material at pre-determined areas in the dielectric layer.

Abstract: An MMIC 100 is a semiconductor device which includes an FET formed on a GaAs substrate 10 and an MIM capacitor having a dielectric layer 20b arranged between a lower electrode 18b and an upper electrode 22b. A method for manufacturing the MMIC 100 is provided, in which a source electrode 16a and a drain electrode 16b of the FET are formed and then a gate electrode 18a of the FET and a lower electrode 18b of the MIM capacitor are formed simultaneously by the lift-off method.

Abstract: Methods and apparatus for screening diverse arrays of materials using infrared imaging techniques are provided. Typically, each of the individual materials on the array will be screened or interrogated for the same material characteristic. Once screened, the individual materials may be ranked or otherwise compared relative to each other with respect to the material characteristic under investigation. According to one aspect, infrared imaging techniques are used to identify the active sites within an array of compounds by monitoring the temperature change resulting from a reaction. This same technique can also be used to quantify the stability of each new material within an array of compounds. According to another aspect, identification and characterization of condensed phase products is achieved, wherein library elements are activated by a heat source serially, or in parallel.

Abstract: A metal resistor and resistor material and method of forming the metal resistor are disclosed. The metal resistor may include an infused metal selected from the group consisting of: copper (Cu) infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W), and aluminum infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W). The method is less complex than conventional processes, allows control of the resistance by the amount of infusion material infused, and is compatible with conventional BEOL processes.

Abstract: An embodiment of the present invention provides a method for performing a lateral flow assay. The method includes depositing a sample on a test strip at an application region, detecting a first detection signal arising from the test strip in the first detection zone, and generating a baseline for the first measurement zone by interpolating between values of the detection signal outside of the first measurement zone and inside of the first detection zone. The method may include locating a beginning boundary and an ending boundary for the first measurement zone on the test strip. Additional detection zones having measurement zones may also be incorporated with the embodiment.

Abstract: An impedance matching network is integrated on a first die and coupled to a second die, with the first and second dies mounted on a conductive back plate. The impedance matching network comprises a first inductor bridging between the first and second dies, a second inductor coupled to the first inductor and disposed on the first die, and a metal-insulator-metal (MIM) capacitor disposed on the first die. The MIM capacitor has a first metal layer coupled to the second inductor, and a second metal layer grounded to the conductive back plate. A method for manufacturing the integrated impedance matching network comprises the steps of forming an inductor on a die, forming a capacitor on the die, coupling the capacitor to the inductor, coupling the die bottom surface and the capacitor to a conductive plate, and coupling the inductor to another inductor that bridges between the die and another die.

Abstract: Methods of forming an integrated circuit device may include forming an insulating layer on an integrated circuit substrate, forming a first conductive layer on the insulating layer, and forming a second conductive layer on the first conductive layer so that the first conductive layer is between the second conductive layer and the insulating layer. Moreover, the first conductive layer may be a layer of a first material, the second conductive layer may be a layer of a second material, and the first and second materials may be different. A hole may be formed in the second conductive layer so that portions of the first conductive layer are exposed through the hole. After forming the hole in the second conductive layer, the first and second conductive layers may be patterned so that portions of the first and second conductive layers surrounding portions of the first conductive layer exposed through the hole are removed while maintaining portions of the first conductive layer previously exposed through the hole.

Abstract: Deposition of a metal-containing reagent solution or suspension onto a conductive substrate by various pad-printing techniques is described. The result in a pseudocapacitive oxide coating, nitride coating, carbon nitride coating, or carbide coating having an acceptable surface area for incorporation into an electrolytic capacitor, such as one have a tantalum anode.

Abstract: The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.

Abstract: A capacitor includes a capacitor part formed of a dielectric film sandwiched by a pair of electrodes and a support body formed of a film of an organic polysilane. The support body is provided so as to support the capacitor part thereon.

Abstract: A semiconductor device includes a first transistor having a first gate oxide layer with a first thickness; a second transistor having a second gate oxide layer with a second thickness different from the first thickness; and at least one of a capacitor and a variable capacitance diode. One of the capacitor and the variable capacitance diode includes a first electrode having a first area and a second area; a second electrode formed in the first area with the first gate oxide layer in between; and a third electrode formed in the second area with the second gate oxide layer in between. The second electrode and third electrode have comb shapes nested inside one another.

Abstract: An integrated circuit resistor is provided that comprises a mesa 14 between electrical contacts 16 and 18. The electrical resistance between electrical contacts 16 and 18 is selectively increased through the formation of recesses 20 and 22 in the mesa 14. The size of recesses 20 and 22 can be used to tune the value of the electrical resistance between contacts 16 and 18.

Abstract: Disclosed is a method for fabricating a thin film transistor for a liquid crystal display device using four masks and without using a diffraction mask. The method of the present invention uses a first mask when forming a gate electrode, a second mask when forming an active pattern, a third mask when forming a plurality of contact holes at an upper portion of a channel layer, and a fourth mask when forming a pixel electrode and source and drain electrodes, so that the resulting liquid crystal display device may be completed by four masks without using a diffraction exposure method. Instead of using a diffraction mask, the present invention uses different etching rates between an insulating layer and an electrode layer, which is used for source and drain electrodes, in fabricating a thin film transistor.

Abstract: A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor dielectric is formed from a high permittivity dielectric with a relative permittivity, preferably greater than about 5. The capacitor also includes a substantially flat top electrode that overlies the capacitor dielectric. In the preferred application, the top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.

Abstract: A semiconductor package structure for improving electrical performance and a method for fabricating the same are proposed, in which a substrate having at least one pair of passive component pads is provided, wherein a semiconductor chip is attached on the substrate and a passive component is mounted to the passive component pads to locate between the substrate and the semiconductor chip. Thus, the passive component can electrically connect the chip and the substrate simultaneously without arranging an additional conductive trace layer, thereby improving the electrical performance of the semiconductor package structure and reducing the structure size.

Abstract: According to one exemplary embodiment, an integrated circuit chip comprises a first interconnect metal layer. The integrated circuit chip further comprises a first intermediate dielectric layer situated over the first interconnect metal layer. The integrated circuit chip further comprises a metal resistor situated over the first intermetallic dielectric layer and below a second intermetallic dielectric layer. The integrated circuit chip further comprises a second interconnect metal layer over the second intermetallic dielectric layer. The integrated circuit chip further comprises a first intermediate via connected to first terminal of the metal resistor, where the first intermediate via is further connected to a first metal segment patterned in the second interconnect metal layer.

Abstract: An electrolytic capacitor comprising an anode, cathode and an electrolyte. The electrolyte comprises: about 35-60%, by weight water; about 10-55%, by weight organic solvent; about 0.05 to 10%, by weight, sulphuric acid; about 0.05 to 10%, by weight, boric acid; and about 0.05 to 10%, by weight, phosphorus oxy acid.