Abstract: The present invention relates to a method of manufacturing a flat aluminum electrolytic capacitor comprising a separator impregnated with an electrolytic solution, an anode foil and a cathode foil, a flat capacitor element that has external lead-out terminals connected respectively to the anode foil and the cathode foil, and a flexible casing that houses the capacitor element and is hermetically sealed, said method comprising the steps of encasing the capacitor element in the flexible casing and applying aging treatment before hermetically sealing the casing, and hermetically sealing the flexible casing, and also relates to a flat aluminum electrolytic capacitor comprising a separator impregnated with the electrolytic solution, the anode foil and the cathode foil, the flat capacitor element that has the external lead-out terminals connected respectively to the anode foil and the cathode foil, and the flexible casing that houses the capacitor element and is hermetically sealed, wherein the electrolytic capacit

Abstract: Methods and apparatus are described for capacitively signaling between different semiconductor chips and modules without the use of connectors, solder bumps, wire-bond interconnections or the like. Preferably, pairs of half-capacitor plates, one half located on each chip, module or substrate are used to capacitively couple signals from one chip, module or substrate to another. The use of plates relaxes the need for high precision alignment as well as reduces the area needed to effect signaling, and reduces or eliminates the requirements for exotic metallurgy.

Abstract: A multi-layer capacitor including a capacitor body including dielectric layers, and first and second internal electrode layers which are alternately laminated by mediation of the dielectric layers. The laminate of the first and second internal electrode layers and the dielectric layers are co-fired. The capacitor body further includes first and second electrode terminals formed on one main surface of the capacitor body. At least a single first via electrode extends through the capacitor body in the lamination direction of the capacitor body so as to connect the first electrode terminal and the first internal electrode layers, and at least a single second via electrode extends through the capacitor body in the lamination direction of the capacitor body so as to connect the second electrode terminal and the second internal electrode layers. The via electrodes have an aspect ratio of 4 to 30 as measured after firing.

Abstract: An integrated magnetoresisitive semiconductor memory configuration has MRAM memory cells located at crossover points of selection lines that are embedded in different, mutually separate line planes. A read/write current can be impressed in respective selection lines for writing to each MRAM memory cell and for reading an information item written therein. In this magnetoresistive semiconductor memory configuration, selection lines that serve for reading a cell information item are in each case located in separate first and second line planes in direct contact with the memory cells. A third and a fourth line plane are spatially separated and electrically isolated from the first and second line planes and are occupied by write selection lines for writing a cell information item.

Abstract: A method and apparatus for adjusting capacitance of an on-chip capacitor uses exposure of a dielectric material of the capacitor to an ion beam comprising ions of at least one material to modify a dielectric constant of the dielectric material.

Abstract: The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN).

Abstract: To provide a solid electrolytic capacitor where solid electrolyte is formed at the cut end part and at the masking part to a larger thickness than in other parts, where the adhesion of the solid electrolyte formed on the valve acting metal oxide film is improved, and whereby the capacitor is highly stabilized in various basic properties such as capacitance, dielectric loss (tan ?), leakage current and short circuit defective ratio and also in the reflow soldering heat resistance and moisture resistance load characteristics. These solid electrolytic capacitor can be obtained by forming electrically conducting polymer on a dielectric film by specifying time for dipping of the surface of a valve actiong metal porous body with a solution containing a monomer and with a solution containing an oxidizing agent, time for vaporization of the solvent of the solution containing a monomer, and polymerization conditions after dipping of the solution containing an oxidizing agent.

Abstract: A method for forming multiple resistors on a substrate. The method initially includes providing a first resistor on the substrate. A first dielectric layer is deposited, patterned, and selectively etched over the first resistor. Second resistor material is provided over the first dielectric layer. Furthermore, landing pad material is provided over the second resistor material. The landing pad material and the second resistor material are then selectively etched. The selective etching forms contacts for the first resistor in a first region, and forms a second resistor and associated contacts in a second region.

Abstract: A method of patterning a bottom electrode for a magnetic memory cell. The bottom electrode is patterned prior to the deposition of the soft layer of the magnetic tunnel junction (MTJ) material stack, preventing the formation of fencing on the sidewalls of the soft layer, which can cause shorts to subsequently formed conductive lines of the magnetic memory device. A sacrificial mask is used to pattern the bottom electrode material, and at least a portion of the sacrificial mask is consumed or removed during the patterning of the bottom electrode material. The soft layer is then deposited and patterned using a hard mask.

Abstract: This invention relates to an apparatus and method of using a high frequency, high power, fluid dielectric variable capacitor for an impedance matching network. The apparatus consists of a bow-tie rotary vane, a set of two fixed vanes, and a set of rotating vanes adapted to rotate interdigitally between the fixed vanes. A dielectric fluid is circulated between the fixed vanes and the rotating vanes for cooling the device. This arrangement facilitates production of a device having a higher capacitance and a smaller size, thus making it suitable for use in a matching network.

Abstract: The present invention is directed to an electrolytic capacitor having a novel floating anode between the cathode and the powered anode of the capacitor, resulting in a single capacitor having a working voltage double that of the formation voltage of the powered anode. The floating anode acts as cathode to the powered anode and as an anode to the cathode, such that the capacitor according to the present invention supports half the working voltage between the cathode and the floating anode and half the working voltage between the floating anode and the powered anode. The arrangement of the cathode, floating anode and powered anode according to the present invention results in a single capacitor with half the capacitance and twice the voltage of a single anode device.

Abstract: A WN film serving as an adhesive layer is deposited over the sidewalls and bottom surface of a hole in a silicon oxide film where an information storage capacitor is to be formed. A Ru film to serve as a lower electrode for the information storage capacitor is formed above the WN film by CVD using Ru(HFAC)3, H2O and H2 as ingredients, so that a ratio of partial pressure of H2O to H2 is controlled to be in the area below a curve (a). When the Ru film is formed by CVD utilizing hydrolysis, the film quality of the Ru film can be enhanced. The ratio of partial pressure of H2O to H2 is controlled, whereby oxidation of the Ru film can be suppressed. When it is controlled to be in the area below a curve (b) to form the Ru film, oxidation of the WN film can be suppressed.

Abstract: The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN).

Abstract: A method of making a flat capacitor includes forming at least one recess on an inside surface of a metal foil blank, leaving a surrounding peripheral flange. A coating performing as an electrode of the capacitor is applied to the inside surface of the metal foil blank and an ion-permeable separator is placed on that inside surface of the metal foil blank. A substantially planar anode with a protruding lead is placed in the recess with the lead extending through a hole of the metal foil blank. Thereafter, the metal foil blank is folded along a line intersecting the hole so that the anode is sandwiched between parts of the separator and the separator is in contact with the coating on the inside surface of the metal foil blank. In the folding process, parts of the peripheral flange of the metal foil blank are brought into contact with each other and these parts are sealed to each other to form a hermetically sealed metal foil case of the capacitor.

Abstract: A semiconductor device having an alternating conductivity type layer improves the tradeoff between the on-resistance and the breakdown voltage and facilitates increasing the current capacity by reducing the on-resistance while maintaining a high breakdown voltage. The semiconductor device includes a semiconductive substrate region, through which a current flows in the ON-state of the device and that is depleted in the OFF-state. The semiconductive substrate region includes a plurality of vertical alignments of n-type buried regions 32 and a plurality of vertical alignments of p-type buried regions. The vertically aligned n-type buried regions and the vertically aligned p-type buried regions are alternately arranged horizontally. The n-type buried regions and p-type buried regions are formed by diffusing respective impurities into highly resistive n-type layers 32a laminated one by one epitaxially.

Abstract: A method of fabricating apparatus, and the apparatus, for providing low voltage temperature compensation in a single power supply HFET including a stack of epitaxially grown compound semiconductor layers with an HFET formed in the stack. A Schottky diode is formed in the stack adjacent the HFET during the formation of the HFET. The HFET and the Schottky diode are formed simultaneously, with a portion of one of the layers of metal forming the gate of the HFET being positioned in contact with a layer of the stack having a low bandgap (e.g. less than 0.8 eV) to provide a turn-on voltage for the Schottky diode of less than 1.8 Volts. The Schottky diode is connected to the gate contact of the HFET by a gate circuit to compensate for changes in current loading in the gate circuit with changes in temperature.

Abstract: The integrated inductor comprises a coil of metal which is formed in the second metal level. The coil is supported by a bracket extending above spaced from a semiconductor material body by an air gap obtained by removing a sacrificial region formed in the first metal level. The bracket is carried by the semiconductor material body through support regions which are arranged peripherally on the bracket and are separated from one another by through apertures which are connected to the air gap. A thick oxide region extends above the semiconductor material body, below the air gap, to reduce the capacitive coupling between the inductor and the semiconductor material body. The inductor thus has a high quality factor, and is produced by a process compatible with present microelectronics processes.

Abstract: Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

Abstract: An integrated semiconductor circuit device comprising a diode bridge circuit formed of a Schottky barrier diode and a periphery circuit formed of a MOS transistor which are formed on a single silicon substrate, wherein a Schottky barrier, which is a component of the Schottky barrier diode, is made of a silicide layer.

Abstract: A thin film resistor (60) is contained between two metal interconnect layers (40, 100) of an integrated circuit. Contact may be made to the resistor (60) through vias (95) from the metal layer (100) above the resistor (60) to both the thin film resistor (60) and the underlying metal layer (40) simultaneously. The resistor (60) may include portions of a hard mask (70) under the vias (95) to protect the resistor material (60) during the via (95) etch. This design provides increased flexibility in fabricating the resistor (60) since processes, materials, and chemicals do not have to satisfy the conditions of both the resistor (60) and the rest of the integrated circuit (especially the interconnect layer 40) simultaneously.

Abstract: Providing a capacitance element which prevents short-circuit between adjacent storage node layers caused by an adhering conductive foreign matter.

Abstract: An anode lead 17 extending from a capacitor body 18 of a capacitor element 14 is mounted on a connecting portion 21 of an anode terminal 12 and the anode lead 17 and the connecting portion 21 are welded together by laser light B. The welding operation is performed by laser light B in a state where the anode lead 17 is urged to the connecting portion 21 in a region between said anode lead and said connecting portion. Alternatively, the welding operation is performed by laser light B in a state where a reflection plate having a slot and functioning to reflect reflected laser light is arranged in a region between the connecting portion and the capacitor body while the anode lead is received in said slot.

Abstract: The invention provides systems and methods for interconnecting circuit devices, wherein decoupling capacitors are disposed on a substrate and an interconnect layer having a pattern of circuit connections is formed by a deposition process over the capacitors thereby embedding the decoupling capacitors within the interconnect layer. Circuit devices can be mounted to the surface of the deposited interconnect layer at locations that minimize, or substantially minimize, the interconnect length between the chip device and the decoupling capacitors for that circuit device.

Abstract: A multi-layered memory cell is described having a plurality of magnetic layers, each of the magnetic layers being for magnetically storing one bit of information. A plurality of access lines are integrated with the plurality of magnetic layers and configured such that the bits of information stored in each of selected ones of the magnetic layers may be independently accessed using selected ones of the plurality of access lines and the giant magnetoresistive effect. The memory cell further includes at least one keeper layer. The magnetic layers, the access lines, and the at least one keeper layer form a substantially closed flux structure.

Abstract: A microwave monolithic integrated circuit comprises a T-shaped gate electrode including a Schottky gate electrode formed on a first region of a compound semiconductor substrate, a pair of ohmic electrodes making an ohmic contact with a surface of the substrate in the first region at respective sides of the T-shaped gate electrode, a lower capacitor electrode pattern formed on a second region of the compound semiconductor substrate with a composition substantially identical with a low-resistance, top electrode constituting the T-shaped gate electrode on the Schottky gate electrode, a dielectric film formed on the lower electrode pattern, and an upper electrode pattern formed on the dielectric film.

Abstract: A polycrystal thin film forming method comprising the step of forming a semiconductor thin film on a substrate 14, and the step of flowing a heated gas to the semiconductor thin film while an energy beam 38 is being applied to the semiconductor thin film at a region to which the gas is being applied to thereby melt the semiconductor film, and crystallizing the semiconductor thin film in its solidification. The energy beam is applied while the high-temperature gas is being flowed, whereby the melted semiconductor thin film can have low solidification rate, whereby the polycrystal thin film can have large crystal grain diameters and can have good quality of little defects in crystal grains and little twins.

Abstract: An improved and novel MRAM device with magnetic memory elements and circuitry for controlling magnetic memory elements is provided. The circuitry, for example, transistor (12a) having a gate (17a), a drain (18) and a source (16a) is integrated on a substrate (11) and coupled to a magnetic memory element (43) on the circuitry through a plug conductor (19a) and a conductor line (45). The circuitry is fabricated first under the CMOS process and then magnetic memory elements (43, 44). Digit line (29) and bit line (48) are placed under and on top of magnetic memory element (43), respectively, and enabled to access magnetic memory element (43). These lines are enclosed by a high permeability layer (31, 56, 58) excluding a surface facing magnetic memory element (43), which shields and focuses a magnetic field toward magnetic memory element (43).

Abstract: The manufacture of AMLCDs and similar large-area electronic devices includes forming thin-film circuit elements (11, 12, 13, 14) on a substrate (10), with some of the process steps being self-aligned by shadow-masking. An upstanding post (20) is provided at a first area (10a) of the substrate (10) to one side of a second area (10b) where there is to be formed a thin-film circuit element (11), for example a TFT. First and second parts of the circuit element (11), for example, the TFT channel (3′) and gate (5a′), are defined by respective first and second angled exposures with beams (61, 62) from the direction of the upstanding post (20) which acts as a shadow mask for part of the second area (10b). A plurality of the upstanding posts (20) may be at least partly retained in the manufactured device, for example, as supports on which a plate (30) is mounted so as to be spaced from the substrate (10).

Abstract: A diffusion resistor is provided that utilizes the block mask to cover only the intrinsic polysilicon gate region. The n-type source/drain doping is implanted in the contact regions, but not in the intrinsic polysilicon gate region. A N-type (or P-type) diffusion resistor in P-well (or N-well) is provided that utilizes a block mask to cover only the intrinsic polysilicon gate region. The N-type (or P-type) source/drain doping is implanted in the contact regions but not in the intrinsic polysilicon gate region. The P-well (or N-well) block mask is used to keep the P-well (or N-well) from forming under the buried resistor. This makes the parasitic capacitance of the diffusion junction very low. Also provided is a buried capacitor and method of making both a buried resistor and a buried capacitor.

Abstract: The present invention provides a method for enlarging the surface area of hemi-spherical grains on the surface of a semiconductor chip. The hemi-spherical grain structure is formed by combining a poly-silicon layer with an underlying amorphous silicon layer. In processing, the two layers are etched with a corrosive solution that etches the amorphous silicon layer at a higher rate than it etches the poly-silicon layer. In this way, a ring-shaped slot forms at the bottom of each hemi-spherical grain thus increasing the total surface area of the hemi-spherical grain structure. Furthermore, surface area of the storage node is increased and the cell capacitor capacitance increases in excess of 15%.

Abstract: A high density magnetic memory device and method of manufacture therefor, wherein the magnetic bit region is provided after selected higher temperature processing steps are performed. Illustrative higher temperature processing steps include those that are performed above for example 400.degree. C., any may include contact and via plug processing. The present invention may allow, for example, contact and via plug processing to be used to form magnetic RAM devices. As indicated above, contact and/or via plug processing typically allows the size of the contacts and vias to be reduced, and the packing density of the resulting memory device to be increased.

Abstract: A low cost highly integrated method of fabricating a heat sink on the backside of a power semiconductor device maintains device performance, improves thermal transfer, and enables reliable planar connections without having to dice the wafer or package the discrete device-heat sink assembly. An etch stop layer is formed between the wafer and the frontside power devices to protect them during backside processing and to reduce the contact resistance between the device and its heat sink. The heat sinks are formed by thinning, patterning and then plating the wafer in such a manner that the devices can be released without dicing. The heat sinks are preferably oversized so that a vacuum tool can grasp the heat sink from above without damaging the device and then compression bond the heat sink onto a planar microstrip circuit assembly, which is designed and packaged to facilitate easy replacement of failed devices.

Abstract: A process enabling high density, DRAM semiconductor chips to be achieved, via formation of DRAM cells, in SOI segments, has been developed. The process features the formation of an SOI layer, propagating from a central node region of a semiconductor substrate, exposed in an opening in an insulator layer, and with the SOI layer extending, and overlying, a portion of the insulator layer, at a distance between about 4 to 5 um, from the central node region. Individual SOI segments are then formed via trimming of the SOI layer, via oxidation of unwanted regions of the SOI layer, followed by removal of these oxidized regions. The DRAM cell, at an area between about 0.28 to 0.32 um.sup.2 is next formed in the individual SOI segments.

Abstract: Method for fabricating an inductor on a semiconductor substrate including a cell region in a semiconductor device is disclosed, including the steps of forming impurity diffusion regions having a predetermined diffusion depth and spaced away from one another by a predetermined distance beneath surface of a semiconductor substrate; selectively oxidizing the semiconductor substrate in a direction crossing the impurity diffusion regions to form an inductor core layer; and forming a polysilicon layer on the entire surface including the inductor core layer and selectively patterning the polysilicon layer to form a plurality of polysilicon pattern layers each connecting with one of ends of the impurity diffusion regions with an opposite end of the adjacent impurity diffusion region so as to form an inductor coil layer electronically connecting the impurity diffusion regions.

Abstract: Cathode and anode sides of a plurality of solid electrolytic capacitors are connected by simultaneous electric welding. The welding step is effected to connect an anode lead of a lead frame to the anode electrode of a capacitor body and simultaneously connect a cathode lead of the lead frame to the cathode conductor layer of an adjacent capacitor body. The welding electrode for the cathode lead exerts moderate force to the capacitor bodies using a spring function of the capacitor lead. The simultaneous welding for the adjacent capacitor bodies and the moderate force prevent electrical and mechanical damages of the insulator layer of the solid electrolytic capacitors during the welding.

Abstract: A buried plate particularly suitable for formation of a common plate of a plurality of trench capacitors, such as are employed in dynamic random access memories, is formed by implantation of impurities in one or more regions of a wafer or semiconductor layer, epitaxially growing a layer of semiconductor material over the implanted regions and diffusing the implanted impurities into the wafer or semiconductor layer and into the epitaxial layer. Diffusion from such a source avoids process complexity compared with provision of diffusion sources within capacitor trenches and further provides an impurity concentration profile which varies with depth within the resulting body of semiconductor material, resulting in a well-defined boundary of the buried plate and an isolation region both above and below the buried plate.

Abstract: Methods for foming an inductor devices used for impedance matching in the radio frequency integrated circuits are disclosed. In the integrated inductor device according to the present invention, an additional electrode is arranged in surroundings of an inductor metal line, and the reverse bias voltage is applied to the region between the substrate and the electrode so as to form a depletion layer. Therefore, the substrate biasing is effected and thus an inductor having improved performance can be formed by decreasing the parasitic capacitance between the inductor metal line and the substrate. The present invention can also be applied to another semiconductor device having metal lines and pads.