Abstract: A semiconductor device includes a semiconductor layer formed on a substrate, an electrode contact window that includes a recess formed on a surface of the semiconductor layer, an inner wall having a slope, and a source electrode, a drain electrode, and a gate electrode formed on the semiconductor layer, in which the drain electrode is in contact with the slope of the inner wall.

Abstract: A light emitting device includes an active layer configured to provide light emission due to carrier recombination therein, a surface on the active layer, and an electrically conductive contact structure on the surface. The contact structure includes at least one plated contact layer. The contact structure may include a sublayer that conforms to the surface roughness of the underlying surface, and the plated contact layer may be substantially free of the surface roughness of the underlying surface. The surface of the plated contact layer may be substantially planar and/or otherwise configured to reflect the light emission from the active layer. Related fabrication methods are also discussed.

Abstract: System and method for processing a semiconductor device surface to reduce dark current and white pixel anomalies. An embodiment comprises a method applied to a semiconductor or photodiode device surface adjacent to a photosensitive region, and opposite a side having circuit structures for the device. A doped layer may optionally be created at a depth of less than about 10 nanometers below the surface of the substrate and may be doped with a boron concentration between about 1E13 and 1E16. An oxide may be created on the substrate using a temperature sufficient to reduce the surface roughness below a predetermined roughness threshold, and optionally at a temperature between about 300° C. and 500° C. and a thickness between about 1 nanometer and about 10 nanometers. A dielectric may then be created on the oxide, the dielectric having a refractive index greater than a predetermined refractive threshold, optionally at least about 2.0.

Abstract: A semiconductor device is provided which includes a GaN-on-SiC substrate (50-51) and a multi-layer passivation stack (52-54) in which patterned step openings (76) are defined and filled with gate metal layers using a lift-off gate metal process to form a T-gate electrode (74) as a stepped gate electrode having sidewall extensions and a contact base portion with one or more gate ledges.

Abstract: A semiconductor device includes: a first electrode; a second electrode; an interlayer insulating film made of a porous insulating material and formed above the first electrode and the second electrode; and connection parts electrically connected to the first electrode and the second electrode respectively, wherein a cavity is formed between the interlayer insulating film and a surface of the first electrode, a surface of the second electrode, and parts of surfaces of the connection parts.

Abstract: An enhanced GaN transistor is provided. The structure comprises a substrate, a heterostructure, a p-element epitaxy growth layer, a drain ohmic contact and a source ohmic contact disposed on the heterostructure and on two sides of the p-element epitaxy growth layer, a gate structure disposed on the p-element epitaxy growth layer, and is separated from the drain ohmic contact and the source ohmic contact, a surface passivation layer covered the drain ohmic contact, source ohmic contact, and p-element epitaxy growth layer, and covered portion of the gate structure.

Abstract: A field effect transistor is provided. The transistor may include a source electrode and a drain electrode provided spaced apart from each other on a substrate and a ‘+’-shaped gate electrode provided on a portion of the substrate located between the source and drain electrodes.

Abstract: The present invention discloses a gate structure, which is applied for an electronic component comprising a substrate and an active region defined thereon, and such the gate structure is disposed in the active region and is a T-shaped gate having a stem with a height of 250 nm. Preferably, the gate structure has a gate length of 60 nm.

Abstract: Disclosed are a semiconductor device having a stable gate structure, and a manufacturing method thereof, in which a gate structure is stabilized by additionally including a plurality of gate feet under a gate head in a width direction of the gate head so as to serve as supporters in a gate structure including a fine gate foot having a length of 0.2 ?m or smaller, and the gate head having a predetermined size. Accordingly, it is possible to prevent the gate electrode of the semiconductor device from collapsing, and improve reliability of the semiconductor device during or after the process of the semiconductor device.

Abstract: In sophisticated semiconductor devices, the encapsulation of sensitive gate materials, such as a high-k dielectric material and a metal-containing electrode material, which are provided in an early manufacturing stage may be achieved by forming an undercut gate configuration. To this end, a wet chemical etch sequence is applied after the basic patterning of the gate layer stack, wherein at least ozone-based and hydrofluoric acid-based process steps are performed in an alternating manner, thereby achieving a substantially self-limiting removal behavior.

Abstract: A FinFET structure which includes: silicon fins on a semiconductor substrate, each silicon fin having two sides and a horizontal surface; a gate wrapping around at least one of the silicon fins, the gate having a first surface and an opposing second surface facing the at least one of the silicon fins; a hard mask on a top surface of the gate; a silicon nitride layer formed in each of the first and second surfaces so as to be below and in direct contact with the hard mask on the top surface of the gate; spacers on the gate and in contact with the silicon nitride layer; and epitaxially deposited silicon on the at least one of the silicon fins so as to form a raised source/drain.

Abstract: A method of forming a FinFET structure which includes forming fins on a semiconductor substrate; forming a gate wrapping around at least one of the fins, the gate having a first surface and an opposing second surface facing the fins; depositing a hard mask on a top of the gate; angle implanting nitrogen into the first and second surfaces of the gate so as to form a nitrogen-containing layer in the gate that is below and in direct contact with the hard mask on top of the gate; forming spacers on the gate and in contact with the nitrogen-containing layer; and epitaxially depositing silicon on the at least one fin so as to form a raised source/drain. Also disclosed is a FinFET structure.

Abstract: A transistor includes a substrate. A first electrically conductive material layer is positioned on the substrate. A second electrically conductive material layer is in contact with and positioned on the first electrically conductive material layer. The second electrically conductive material layer includes a reentrant profile. The second electrically conductive material layer also overhangs the first electrically conductive material layer.

Abstract: A semiconductor device (100) includes a substrate (1) having a semiconductor layer (102); a trench (12) in the semiconductor layer (102); a gate insulating film (11) covering a periphery and an inner surface of the trench (12); a gate electrode (8) including a portion filling the trench (12) and a portion around the trench (12), and provided on the gate insulating film (11); an interlayer insulating film (13) on the gate electrode (8); and a hollow (50) above and around the trench (12), and between the gate electrode (8) and the gate insulating film (11). Above the trench (12), the hollow (50) protrudes inside the trench (12) from a plane extending from an upper surface of the gate insulating film (11) at a portion covering the side surface of the trench (12) with a flat shape.

Abstract: Disclosed are a semiconductor device including a stepped gate electrode and a method of fabricating the semiconductor device. The semiconductor device according to an exemplary embodiment of the present disclosure includes: a semiconductor substrate having a structure including a plurality of epitaxial layers and including an under-cut region formed in a part of a Schottky layer in an upper most part thereof; a cap layer, a first nitride layer and a second nitride layer sequentially formed on the semiconductor substrate to form a stepped gate insulating layer pattern; and a stepped gate electrode formed by depositing a heat-resistant metal through the gate insulating layer pattern, wherein the under-cut region includes an air-cavity formed between the gate electrode and the Schottky layer.

Abstract: A method of forming a field effect transistor (FET) device includes forming a gate structure over a substrate, the gate structure including a wide bottom portion and a narrow portion formed on top of the bottom portion; the wide bottom portion comprising a metal material and having a first width that corresponds substantially to a transistor channel length, and the narrow portion also including a metal material having a second width smaller than the first width.

Abstract: Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.

Abstract: A transistor is manufactured by a method including: forming a first wiring layer; forming a first insulating film to cover the first wiring layer; forming a semiconductor layer over the first insulating film; forming a conductive film over the semiconductor layer; and performing at least two steps of etching on the conductive film to form second wiring layers which are apart from each other, wherein the two steps of etching include at least a first etching process performed under the condition that the etching rate for the conductive film is higher than the etching rate for the semiconductor layer, and a second etching process performed under the condition that the etching rates for the conductive film and the semiconductor layer are higher than those of the first etching process.

Abstract: A method of manufacturing a semiconductor device includes forming an insulating layer over a semiconductor region; forming a multilayer resist composite including a plurality of resist layers over the insulating layer; forming an opening in the resist layers of the multilayer resist composite except in the lowermost resist layer adjacent to the insulating layer; forming a reflow opening in the lowermost resist layer; reflowing part of the lowermost resist layer exposed in the reflow opening by heating to form a slope at the surface of the lowermost resist layer; forming a first gate opening in the lowermost resist layer so as to extend from the slope; and forming a gate electrode having a shape depending on the shapes of the opening in the multilayer resist composite, the slope and the first gate opening.

Abstract: The present invention provides a method of manufacturing a dummy gate in a gate last process, which comprises the steps of forming a dummy gate material layer and a hard mask material layer sequentially on a substrate; etching the hard mask material layer to form a top-wide-bottom-narrow hard mask pattern; dry etching the dummy gate material layer using the hard mask pattern as a mask to form a top-wide-bottom-narrow dummy gate. According to the dummy gate manufacturing method of the present invention, instead of vertical dummy gates used conventionally, top-wide-bottom-narrow trapezoidal dummy gates are formed, and after removing the dummy gates, trapezoidal trenches can be formed. It facilitates the subsequent filling of the high-k or metal gate material and enlarges the window for the filling process; as a result, the device reliability will be improved.

Abstract: Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.

Abstract: Provided is a semiconductor device. The semiconductor device includes: a substrate; an active layer on the substrate; a capping layer on the active layer; source/drain electrodes on the capping layer; a gate electrode on the active layer; and a first void region on a first sidewall of the gate electrode and a second void region on a second sidewall facing the first sidewall.

Abstract: Fabrication methods of a high frequency (sub-micron gate length) operation of AlInGaN/InGaN/GaN MOS-DHFET, and the HFET device resulting from the fabrication methods, are generally disclosed. The method of forming the HFET device generally includes a novel double-recess etching and a pulsed deposition of an ultra-thin, high-quality silicon dioxide layer as the active gate-insulator. The methods of the present invention can be utilized to form any suitable field effect transistor (FET), and are particular suited for forming high electron mobility transistors (HEMT).

Abstract: In high frequency circuits, the switching speed of devices is often limited by the series resistance and capacitance across the input terminals. To reduce the resistance and capacitance, the cross-section of input electrodes is made into a T-shape or inverted L-shape through lithography. The prior art method for the formation of cavities for T-gate or inverted L-gate is achieved through several steps using multiple photomasks. Often, two or even three different photoresists with different sensitivity are required. In one embodiment of the present invention, an optical lithography method for the formation of T-gate or inverted L-gate structures using only one photomask is disclosed. In another embodiment, the structure for the T-gate or inverted L-gate is formed using the same type of photoresist material.

Abstract: Provided are a method of manufacturing a normally-off mode high frequency device structure and a method of simultaneously manufacturing a normally-on mode high frequency device structure and a normally-off mode high frequency device structure on a single substrate.

Abstract: The present invention provides methods for fabricating devices with low resistance structures involving a lift-off process. A radiation blocking layer is introduced between two resist layers in order to prevent intermixing of the photoresists. Cavities suitable for the formation of low resistance T-gates or L-gates can be obtained by a first exposure, developing, selective etching of blocking layer and a second exposure and developing. In another embodiment, a low resistance gate structure with pillars to enhance mechanical stability or strength is provided.

Abstract: There is provided a semiconductor device including: a SiC substrate; an AlGaN layer formed on the SiC substrate; a source electrode and a drain electrode formed on the AlGaN layer so as to be spaced from each other; a first insulation film formed between the source electrode and the drain electrode and having a band-like opening parallel to the drain electrode and the source electrode; a gate electrode formed at the opening in the first insulation film; a second insulation film formed on the first insulation film in such a manner as to cover a surface of the gate electrode; and a source field plate electrode which is formed on the second insulation film and the source electrode and an end portion of which on the drain electrode side is spaced from the second insulation film, thereby suppressing degradation in device performance.

Abstract: A method of fabricating a semiconductor device is disclosed. The method comprises patterning a photoresist over a compound semiconductor substrate; reducing a width of the photoresist; forming a hardmask over the substrate and not over the photoresist; removing the photoresist; etching to form and opening down to the substrate; forming a gate in the opening; and removing the hardmask except beneath the gate.

Abstract: Methods of forming Group III-nitride transistor device include forming a protective layer on a Group III-nitride semiconductor layer, forming a via hole through the protective layer to expose a portion of the Group III-nitride semiconductor layer, and forming a masking gate on the protective layer. The masking gate includes an upper portion having a width that is larger than a width of the via hole and having a lower portion extending into the via hole. The methods further include implanting source/drain regions in the Group III-nitride semiconductor layer using the masking gate as an implant mask.

Abstract: A III-nitride device includes a recessed electrode to produce a nominally off, or an enhancement mode, device. By providing a recessed electrode, a conduction channel formed at the interface of two III-nitride materials is interrupted when the electrode contact is inactive to prevent current flow in the device. The electrode can be a schottky contact or an insulated metal contact. Two ohmic contacts can be provided to form a rectifier device with nominally off characteristics. The recesses formed with the electrode can have sloped sides. The electrode can be formed in a number of geometries in conjunction with current carrying electrodes of the device. A nominally on device, or pinch resistor, is formed when the electrode is not recessed. A diode is also formed by providing non-recessed ohmic and schottky contacts through an insulator to an AlGaN layer.

Abstract: Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.

Abstract: A field effect transistor includes a GaN epitaxial substrate, a gate electrode formed on an electron channel layer of the substrate, and source and drain electrodes arranged spaced apart by a prescribed distance on opposite sides of the gate electrode. The source and drain electrodes are in ohmic contact with the substrate. At an upper portion of the gate electrode, a field plate is formed protruding like a visor to the side of drain electrode. Between the electron channel layer of the epitaxial substrate and the field plate, a dielectric film is formed. The dielectric film is partially removed at a region immediately below the field plate, to be flush with a terminal end surface of the field plate. The dielectric film extends from a lower end of the removed portion to the drain electrode, to be overlapped on the drain electrode.

Abstract: A method of fabricating a semiconductor device, the method comprises forming a mask layer over a compound semiconductor substrate; and patterning a photoresist over the mask layer. The method comprises etching a portion of the mask layer beneath the photoresist; forming a hardmask over the substrate and not over the mask layer; removing the mask layer; etching to form and opening down to the substrate; and forming a gate in the opening.

Abstract: A method for making a thin film transistor, the method comprising the steps of: (a) providing a carbon nanotube array and an insulating substrate; (b) pulling out a carbon nanotube film from the carbon nanotube array by using a tool; (c) placing at least one carbon nanotube film on a surface of the insulating substrate, to form a carbon nanotube layer thereon; (d) forming a source electrode and a drain electrode; wherein the source electrode and the drain electrode being spaced therebetween, and electrically connected to the carbon nanotube layer; and (e) covering the carbon nanotube layer with an insulating layer, and a gate electrode being located on the insulating layer.

Abstract: A method of fabricating a T-gate is provided. The method includes the steps of: forming a photoresist layer on a substrate; patterning the photoresist layer formed on the substrate and forming a first opening; forming a first insulating layer on the photoresist layer and the substrate; removing the first insulating layer and forming a second opening to expose the substrate; forming a second insulating layer on the first insulating layer; removing the second insulating layer and forming a third opening to expose the substrate; forming a metal layer on the second insulating layer on which the photoresist layer and the third opening are formed; and removing the metal layer formed on the photoresist layer. Accordingly, a uniform and elaborate opening defining the length of a gate may be formed by deposition of the insulating layer and a blanket dry etching process, and thus a more elaborate micro T-gate electrode may be fabricated.

Abstract: A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.

Abstract: A method of producing a T-gate in a single stage exposure process using electromagnetic radiation is disclosed.

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract: A method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices, particularly for integrated HBT/HEMT devices on a common substrate is disclosed. The method is based on dual-resist processes, wherein a first thin photo-resist layer is utilized for defining the gate dimension, while a second thicker photo-resist layer is used to obtain a better coverage on the surface for facilitating gate metal lift-off. The dual-resist method not only reduces the final gate length, but also mitigates the gate recess undercuts, as compared with those fabricated by the conventional single-resist processes. Furthermore, the dual-resist method of the present invention is also beneficial for the fabrication of multi-gate device with good gate-length uniformity.

Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer, source/drain extensions a distance beneath the metal gate, and lateral undercuts in the sides of the metal gate.

Abstract: In one embodiment, a tiered gate structure is provided having a substrate including a source, a drain and a gate thereon. The gate includes an elongated gate foot having a first deposition gate material extending from the substrate, the elongated gate foot having a top portion distal from the substrate. The gate head has a second deposition gate material and includes an elongated portion extending downward from the gate head to connect to the top portion of the elongated gate foot.

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract: There are provided a memory transistor having a select transistor with asymmetric gate electrode structure and an inverted T-shaped floating gates and a method for forming the same. A gate electrode of the select transistor adjacent to a memory transistor has substantially an inverted T-shaped figure, whereas the gate electrode of the select transistor opposite to the memory transistor has nearly a box-shaped figure. In order to form the floating gate of the memory transistor in shape of the inverted T, a region for the select transistor is closed when opening a region for the memory transistor.

Abstract: A silicon carbide metal semiconductor field-effect transistor includes a bi-layer silicon carbide buffer for improving electron confinement in the channel region and/or a layer disposed over at least the channel region of the transistor for suppressing surface effects caused by dangling bonds and interface states. Also, a sloped MESA fabrication method which utilizes a dielectric etch mask that protects the MESA top surface during MESA processing and enables formation of sloped MESA sidewalls.

Abstract: Provided are a method of fabricating a multilayered thin film transistor using a plastic substrate and an active matrix display device including the thin film transistor fabricated by the method. The method includes: preparing a substrate formed of plastic; forming a buffer insulating layer on the plastic substrate; forming a silicon layer on the buffer insulating layer; patterning the silicon layer to form an active layer; forming a gate insulating layer on the active layer; stacking a plurality of gate metal layers on the gate insulating layer; patterning the plurality of gate metal layers; and etching a corner region of the lowest gate metal layer formed on the gate insulating layer of the patterned gate metal layers. Accordingly, a gate metal is formed which includes a multilayered gate metal layer and has an etched corner region, thereby reducing an electric field of the corner to reduce a leakage current of the TFT.

Abstract: A field effect transistor having a T-shaped gate electrode is formed on a GaAs substrate, and the T-shaped gate electrode of the field effect transistor is coated with a SiO2 film. A lower electrode of a MIM capacitor is formed on the GaAs substrate. The active portion of the field effect transistor is coated with a fluorine-containing polymer layer. A SiN film, which is a capacity insulating film of the MIM capacitor, is formed on the fluorine-containing polymer layer and the lower electrode. After removing the SiN film from the fluorine-containing polymer layer, the fluorine-containing polymer layer is selectively removed from the SiO2 film and the SiN film. An upper electrode of the MIM capacitor is formed opposite the lower electrode on the SiN film.

Abstract: A semiconductor process and apparatus provide a T-shaped structure (96) formed from a polysilicon structure (10) and an epitaxially grown polysilicon layer (70) and having a narrower bottom critical dimension (e.g., at or below 40 nm) and a larger top critical dimension (e.g., at or above 40 nm) so that a silicide may be formed from a first material (such as CoSi2) in at least the upper region (90) of the T-shaped structure (96) without incurring the increased resistance caused by agglomeration and voiding that can occur with certain silicides at the smaller critical dimensions.

Abstract: A method for manufacturing a semiconductor device using a polymer is provided, wherein a first insulating layer is formed on a substrate, and a first photoresist pattern is formed over the first insulating layer. A polymer is formed around the first photoresist pattern, the polymer having an opening exposing a portion of the first insulating layer, the opening having a predetermined width, the first insulating layer is etched using the polymer as a mask to expose a portion of the substrate, and the first photoresist pattern and the polymer are removed. A gate insulating layer is formed on the exposed portion of the substrate, and a polysilicon layer is formed on the gate insulating layer and the etched first insulating layer. The polysilicon layer is planarized until the first insulating layer is exposed, to form a gate, and the exposed first insulating layer is removed.

Abstract: A method for fabricating a tiered structure includes forming a gate on a semiconductor substrate. Formation of the gate includes depositing a gate foot using a gate foot mask having an opening through it to define the gate foot over the substrate. After forming the gate foot, the gate foot mask is stripped and a passivation layer is formed over the gate foot and the substrate. A gate head mask is formed over the gate foot with the gate head mask exposing a portion of the passivation layer on a top portion of the gate foot. The portion of the passivation layer on the top portion of the gate foot is removed to expose the top portion of the gate foot. A gate head is formed on the top portion of the gate foot using the gate head mask. A lift-off process is performed, removing the gate head mask.

Abstract: Transistors are fabricated by forming a protective layer having an opening extending therethrough on a substrate, and forming a gate electrode in the opening. A first portion of the gate electrode laterally extends on surface portions of the protective layer outside the opening, and a second portion of the gate electrode is spaced apart from the protective layer and laterally extends beyond the first portion. Related devices and fabrication methods are also discussed.