Abstract: A field effect transistor and method for making the same is described wherein the field effect transistor incorporates a T-shaped gate and source and drain contacts self-aligned with preexisting shallow junction regions. The present invention provides a low resistance gate electrode and self-aligned low resistance source/drain contacts suitable for submicron FET devices, and scalable to smaller device dimensions.

Abstract: An improved method for forming a T-gate structure in a MESFET includes dielectric lift-off steps.

Abstract: Method for manufacturing a T-gate useful for reducing a gate resistance, improving through-put, and simplifying an MMIC (monolithic microwave integrated circuit) process is disclosed, the method including the steps of depositing a first photoresist layer on a semiconductor substrate and patterning the first photoresist layer so as to expose a predetermined portion of the surface of the substrate; successively forming a seed metal layer and a second photoresist layer on the entire surface inclusive of the exposed substrate and patterning the second photoresist layer so as to define a gate electrode region; plating Au on the seed metal layer on the gate electrode region so as to form a gate electrode; and removing the first and second photoresist layers and the seed metal layer except the gate electrode.

Abstract: A silicon carbide MESFET (10) is formed to have a source (21) and a drain (22) that are self-aligned to a gate (16) of the MESFET (10). The gate (16) is formed to have a T-shaped structure with a gate-to-source spacer (18) and gate-to-drain spacer (19) along each side of a base of the gate (16). The gate (16) is used as a mask for implanting dopants to form the source (21) and drain (22). A laser annealing is performed after the implantation to activate the dopants. Because the laser annealing is a low temperature operation, the gate (16) is not detrimentally affected during the annealing.

Abstract: In a method of manufacturing a semiconductor device, an operating layer and a light-shielding film are sequentially formed to form a recess step on a semiconductor substrate. A first photoresist film is formed on the light-shielding film. The light-shielding film is patterned using the photoresist film as a mask to form a gate electrode formation opening portion. A metal film is formed on the entire surface including the opening portion. The metal film is selectively etched using, as a mask, a second photoresist film formed on the metal film, thereby forming a gate electrode having a T shape in the longitudinal section. The second photoresist film is removed. The light-shielding film is removed.

Abstract: A method is provided for forming a transistor in which capacitive coupling between the gate conductors and adjacent structures employed by the integrated circuit is reduced. According to an embodiment, a gate conductor is dielectrically spaced above a semiconductor substrate, and a masking structure is arranged upon an upper surface of the gate conductor. A source/drain implant self-aligned to opposed lateral sidewalls of the masking structure is performed to form source/drain implant areas within the substrate. Select portions of the gate conductor are removed such that opposed ends of the masking structure extend beyond opposed sidewall surfaces of the gate conductor. A lightly doped drain implant self-aligned to the opposed sidewall surfaces of the narrowed gate conductor is performed to form lightly doped drain implant areas within the substrate.

Abstract: A fabrication method of a semiconductor device is disclosed. A T-shaped gate used for decreasing the gate resistance is adopted in fabricating an ultrahigh frequency and low-noise device. According to the present invention, a gate pattern is formed by a dual exposure technique, a thin metal film is formed, a pattern for plating is formed, and a gate is formed by electroplating, whereby decreasing a gate length and gate resistance. Therefore, the cost of production is decreased, the yield is improved, and the noise figure is minimized.

Abstract: A dielectric film is formed on a semiconductor substrate, and on the dielectric film an inorganic dielectric mask film is deposited by CVD. The mask film comprises a first component which is relatively high in etch rate by isotropic plasma etching and a second component relatively low in etch rate, and the content of the first component is linearly gradient in the film thickness direction so as to become lowest at the interface between the mask film and the underlying dielectric film. For example, the mask film is a phosphosilicate glass (P.sub.2 O.sub.5 --SiO.sub.2) film. A resist film is formed on the mask film, and a window is opened in the resist film by electron beam lithography. Then a window is opened in the mask film by isotropic plasma etching, and the underlying dielectric film is also etched to form a window under the window in the mask film.

Abstract: A device having, at least, a first film having a surface on which neither a natural oxide film nor impurity grains caused by a resist residue is or are present, and a conductive material layer formed on a surface adjacent to the surface of the first film, wherein an insulative compound film is formed on a surface of the conductive material layer by a surface reaction with the conductive material layer, and a predetermined second film required for an arrangement is formed on the surface of the first film.

Abstract: A method for forming a V-shaped gate electrode on a semiconductor substrate includes the following steps: A first gate opening is formed in a first resist between a source and a drain formed on a semiconductor substrate, and dummy openings are formed near both sides of the first gate opening. By baking the first resist, convex portions thereof which rise steeply are formed between the first gate opening and the dummy openings. A second resist is formed to overlay the first resist convex portions and the first gate opening. The second resist is removed from the first gate opening, and a second gate opening larger than the first gate opening is formed in the second resist above the first gate opening. Metal for the V-shaped gate electrode is deposited through the second gate opening on the sides of the first resist convex portions rising steeply from the bottom of the first gate opening.

Abstract: Method for manufacturing a metal semiconductor field-effect transistor (MESFET) in which a gate area contacting a semiconductor surface is diminished and a gate cross area is increased, to improve frequency characteristics of a device is disclosed, including the steps of: forming an n-type GaAs layer and a heavily doped n.sup.+ -type GaAs layer on a substrate, sequentially; forming a first insulating layer on the heavily doped n.sup.

Abstract: Method for manufacturing a self-aligned T-type gate in which an ohmic electrode and a T-type gate electrode are simultaneously disposed and its excellent reproductivity is obtained and the overall process is simplified is disclosed, including the steps of: forming an insulating layer, a first metal layer, and a first photoresist layer and patterning the first photoresist layer; selectively removing the first metal layer such that the first metal layer under a pattern of the first photoresist layer is under-cut in a mesa form to form a gate pattern, and selectively removing the insulating layer such that the insulating layer under the first metal layer is under-cut in a same form as the first metal layer so as to pattern ohmic electrode regions; forming a second metal layer on the ohmic electrode regions to form ohmic electrodes and selectively removing the insulating layer to be unsymmetrical with respect to the center of the first metal layer; forming a second photoresist layer on the entire surface inclusiv

Abstract: A semiconductor device is manufactured by a process comprising the steps of forming a cover film on a surface of a semiconductor substrate such that the cover film exposes a portion of the surface, covers a remaining portion thereof and has an edge along a boundary between the exposed portion and the covered portion, forming a first conductor film in a range from the cover film formed in the cover film forming step through the edge to the exposed surface portion of the semiconductor substrate, removing the first conductor film formed in the first conductor film forming step other than a portion formed along the edge such that the first conductor film is left along the edge, forming an insulating film on the opposite sides of the first conductor film left along the edge in the removing step such that a top edge of the left first conductor film is exposed, and forming a second conductor film on the surface of the insulating film formed in the insulating film forming step along the exposed top edge of the first

Abstract: A method of fabricating semiconductor devices with a passivated surface includes providing first cap and etch stop layers and second cap and etch stop layers with a contact layer thereon so as to define an inter-electrode surface area. A first layer and an insulating layer, which are selectively etchable relative to each other, are deposited on the contact layer and the inter-electrode surface area. The insulating layer and the first layer are individually etched to define an electrode contact area and to expose the inter-electrode surface area. Portions of the first etch stop and cap layers remaining in the contact area are selectively removed and a metal contact is formed in the contact area in abutting engagement with the insulating layer so as to seal the inter-electrode surface area.