Doping Of Semiconductive Region Patents (Class 438/181)
  • Patent number: 10049994
    Abstract: A chip contact pad and a method of making a chip contact pad are disclosed. An embodiment of the present invention includes forming a plurality of contact pads over a workpiece, each contact pad having lower sidewalls and upper sidewalls and reducing a lower width of each contact pad so that an upper width of each contact pad is larger than the lower width. The method further includes forming a photoresist over the plurality of contact pads and removing portions of the photoresist thereby forming sidewall spacers along the lower sidewalls.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: August 14, 2018
    Assignee: Infineon Technologies AG
    Inventors: Johann Gatterbauer, Bernhard Weidgans
  • Patent number: 9391160
    Abstract: One embodiment of the invention relates to an unguarded Schottky barrier diode. The diode includes a cathode that has a recessed region and a dielectric interface surface that laterally extends around a perimeter of the recessed region. The diode further includes an anode that conforms to the recessed region. A dielectric layer extends over the dielectric interface surface of the cathode and further extends over a portion of the anode near the perimeter. Other devices and methods are also disclosed.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: July 12, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Vladimir Frank Drobny
  • Patent number: 9018083
    Abstract: In an example of a method for controlling the formation of dopants in an electrically actuated device, a predetermined concentration of a dopant initiator is selected. The predetermined amount of the dopant is localized, via diffusion, at an interface between an electrode and an active region adjacent to the electrode. The dopant initiator reacts with a portion of the active region to form the dopants.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: April 28, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jianhua Yang, Duncan Stewart, Philip J. Kuekes, William Tong
  • Patent number: 8846464
    Abstract: An approach for controlling a critical dimension (CD) of a RMG of a semiconductor device is provided. Specifically, embodiments of the present invention allow for CD consistency between a dummy gate and a subsequent RMG. In a typical embodiment, a dummy gate having a cap layer is formed over a substrate. A re-oxide layer is then formed over the substrate and around the dummy gate. A set of doping implants will then be implanted in the substrate, and the re-oxide layer will subsequently be removed (after the set of doping implants have been implanted). A set of spacers will then be formed along a set of side walls of the dummy gate and an epitaxial layer will be formed around the set of side walls. Thereafter, the dummy gate will be replaced with a metal gate (e.g., an aluminum or tungsten body having a high-k metal liner there-around).
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 30, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Bingwu Liu, Baofu Zhu, Nam Sung Kim
  • Publication number: 20140227836
    Abstract: Disclosed herein is a nitride based semiconductor device including: a base substrate; an epitaxial growth layer disposed on the base substrate and generating a 2-dimensional electron gas in an inner portion thereof; and an electrode structure disposed on the epitaxial growth layer, wherein the electrode structure includes: a gate electrode; a source electrode disposed at one side of the gate electrode; and a drain electrode disposed at the other side of the gate electrode and having an extension part extended to the inner portion of the epitaxial growth layer to contact the 2-dimensional electron gas.
    Type: Application
    Filed: April 22, 2014
    Publication date: August 14, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Kiyeol PARK, Woochul JEON, Younghwan PARK
  • Patent number: 8803148
    Abstract: A thin film transistor may include a substrate, a buffer layer on the substrate, a semiconductor layer formed on the buffer layer, a gate insulating pattern on the semiconductor layer, a gate electrode on the gate insulating pattern, an interlayer insulating layer covering the gate electrode and the gate insulating pattern, the interlayer insulating layer having a contact hole and an opening extending therethrough, the contact hole exposing a source area and a drain area of the semiconductor layer, and the opening exposing a channel area of the semiconductor layer, and a source electrode and a drain electrode formed on the interlayer insulating layer, the source electrode being connected with the source area and the drain electrode being connected with the drain area of the semiconductor layer.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: August 12, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung-Keon Park, Jong-Ryuk Park, Tak-Young Lee, Jin-Wook Seo, Ki-Yong Lee, Heung-Yeol Na
  • Patent number: 8790969
    Abstract: A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake step at a temperature lower or equal than 800° C., a subsequent deposition step of Si or SiGe will not lead to a layer deposition in the first surface region. This effect is used for selective deposition of Si or SiGe in the second surface region, which is not doped with Boron in the suitable concentration range, or doped with another dopant, or not doped. Several devices are, thus, provided. The method thus saves a usual photolithography sequence required for selective deposition of Si or SiGe in the second surface region according to the prior art.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: July 29, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexandre Mondo, Markus Gerhard Andreas Muller, Thomas Kormann
  • Patent number: 8791445
    Abstract: A nonvolatile resistive memory element includes a host oxide formed from an interfacial oxide layer. The interfacial oxide layer is formed on the surface of a deposited electrode layer via in situ or post-deposition surface oxidation treatments.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: July 29, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Randall Higuchi, Tony P. Chiang, Ryan Clarke, Vidyut Gopal, Imran Hashim, Robert Huertas, Yun Wang
  • Patent number: 8759186
    Abstract: A method for manufacturing a semiconductor device includes forming a metal oxide semiconductor layer and a first insulating layer on a substrate. A gate is formed on the first insulating layer. The first insulating layer is patterned by using the gate as an etching mask so as to expose the metal oxide semiconductor layer to serve as a source region and a drain region. A dielectric layer is formed on the substrate to cover the gate and the oxide semiconductor layer, where the dielectric layer has at least one of hydrogen group and hydroxyl group. A heating treatment is performed so that the at least one of hydrogen group and hydroxyl group reacts with the source region and the drain region. A source electrode and a drain electrode electrically connected to the source region and the drain region respectively are formed on the dielectric layer.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: June 24, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Yung-Hui Yeh, Chih-Ming Lai
  • Patent number: 8735234
    Abstract: An improved method of doping a substrate is disclosed. The method is particularly beneficial to the creation of interdigitated back contact (IBC) solar cells. A paste having a dopant of a first conductivity is applied to the surface of the substrate. This paste serves as a mask for a subsequent ion implantation step, allowing ions of a dopant having an opposite conductivity to be introduced to the portions of the substrate which are exposed. After the ions are implanted, the mask can be removed and the dopants may be activated. Methods of using an aluminum-based and phosphorus-based paste are disclosed.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: May 27, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Atul Gupta, Nicholas Bateman
  • Patent number: 8685806
    Abstract: A method of forming a SOI substrate, diodes in the SOI substrate and electronic devices in the SOI substrate and an electronic device formed using the SOI substrate. The method of forming the SOI substrate includes forming an oxide layer on a silicon first substrate; ion-implanting hydrogen through the oxide layer into the first substrate, to form a fracture zone in the substrate; forming a doped dielectric bonding layer on a silicon second substrate; bonding a top surface of the bonding layer to a top surface of the oxide layer; thinning the first substrate by thermal cleaving of the first substrate along the fracture zone to form a silicon layer on the oxide layer to formed a bonded substrate; and heating the bonded substrate to drive dopant from the bonding layer into the second substrate to form a doped layer in the second substrate adjacent to the bonding layer.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Dyer, Junedong Lee, Dominic J. Schepis
  • Patent number: 8481378
    Abstract: A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake at a temperature lower or equal to 800° C., a subsequent deposition step will prevent deposition in the first surface region. This allows selective deposition in the second surface region, which is not doped with the Boron (or doped with another dopant or not doped). Several devices are, thus, provided. The method saves a usual photolithography sequence, which according to prior art is required for selective deposition of Si or SiGe in the second surface region.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: July 9, 2013
    Assignees: STMicroelectronics (Crolles 2) SAS, NXP B.V.
    Inventors: Alexandre Mondot, Markus Gerhard Andreas Muller, Thomas Kormann
  • Patent number: 8481377
    Abstract: It is an object to provide a semiconductor device including an oxide semiconductor, in which miniaturization of a transistor is achieved and the concentration of an electric field is relieved. The width of a gate electrode is reduced and a space between a source electrode layer and a drain electrode layer is shortened. By adding a rare gas in a self-alignment manner with the use of a gate electrode as a mask, a low-resistance region in contact with a channel formation region can be provided in an oxide semiconductor layer. Accordingly, even when the width of the gate electrode, that is, the line width of a gate wiring is small, the low-resistance region can be provided with high positional accuracy, so that miniaturization of a transistor can be realized.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: July 9, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Ryosuke Watanabe, Masashi Tsubuku, Shunpei Yamazaki
  • Patent number: 8476154
    Abstract: The present invention provides a charge trapping non-volatile semiconductor memory device and a method of making the device. The charge trapping non-volatile semiconductor memory device comprises a semiconductor substrate, a source region, a drain region, and, consecutively formed over the semiconductor substrate, a channel insulation layer, a charge trapping layer, a blocking insulation layer, and a gate electrode. The drain region includes a P-N junction, and the source region includes a metal-semiconductor junction formed between the semiconductor substrate and a metal including titanium, cobalt, nickel, platinum or one of their various combinations. The charge trapping non-volatile semiconductor memory device according to the present disclosure has low programming voltage, fast programming speed, low energy consumption, and relatively high device reliability.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: July 2, 2013
    Assignee: Fudan University
    Inventors: Dongping Wu, Shi-Li Zhang
  • Patent number: 8445351
    Abstract: The present invention provides a floating-gate non-volatile semiconductor memory device and a method of making the same. The floating-gate non-volatile semiconductor memory device comprises a semiconductor substrate, a source, a drain, a first insulator layer, a first polysilicon layer, a second insulator layer, a second polysilicon layer, a protective layer and sidewalls. The source and drain are disposed on the semiconductor substrate. The first insulator layer is disposed over a region of the semiconductor substrate other than regions corresponding to the source and drain. The first polysilicon layer is disposed over the first insulator layer, forming a floating gate. The second insulator layer is disposed over the first polysilicon layer. The second polysilicon layer is disposed over the second insulator layer, forming a control gate and a wordline. The sidewalls are disposed on two sides of the wordline, and the protective layer is disposed over the second polysilicon layer.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: May 21, 2013
    Assignee: Fudan University
    Inventors: Dongping Wu, Shi-Li Zhang
  • Patent number: 8324014
    Abstract: The present invention relates to a process for depositing films on a substrate by chemical vapour deposition (CVD) or physical vapour deposition (PVD), said process employing at least one boron compound. This process is particularly useful for fabricating photovoltaic solar cells. The invention also relates to the use of boron compounds for conferring optical and/or electrical properties on materials in a CVD or PVD deposition process. This process is also particularly useful for fabricating a photovoltaic solar cell.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: December 4, 2012
    Assignee: L'Air Liquide Societe Anonyme pour l'Etude et l'Exploitation des Procedes Georges Claude
    Inventors: Audrey Pinchart, Denis Jahan
  • Patent number: 8325516
    Abstract: A split gate memory cell. First and second well regions of respectively first and second conductivity types are formed in the substrate. A floating gate is disposed on a junction of the first and second well regions and insulated from the substrate. A control gate is disposed over the sidewall of the floating gate and insulated from the substrate and the floating gate and partially extends to the upper surface of the floating gate. A doping region of the first conductivity type is formed in the second well region. The first well region and the doping region respectively serve as source and drain regions of the split gate memory cell.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: December 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yue-Der Chih, Shine Chung, Wen-Ting Chu
  • Patent number: 8211322
    Abstract: A method of patterning a metal layer includes forming a first mask on a surface of the metal layer, the first mask having an opening through the first mask that exposes the metal layer, and forming a nanogap in the exposed metal layer using an ion beam directed through the opening. The first mask limits a lateral extent of the ion beam, and the nanogap has a width that is less than a width of the opening.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: July 3, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Gun Park, Dong-Won Kim, Sung-Young Lee, Yang-Kyu Choi, Chang-Hoon Kim, Ju-Hyun Kim
  • Patent number: 8123964
    Abstract: An image sensor and a method for fabricating the same are provided. The image sensor includes a first conductive type substrate including a trench formed in a predetermined portion of the first conductive type substrate, a second conductive type impurity region for use in a photodiode, formed below a bottom surface of the trench in the first conductive type substrate, and a first conductive type epitaxial layer for use in the photodiode, buried in the trench.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: February 28, 2012
    Assignee: Intellectual Ventures II LLC
    Inventors: Hee Jeen Kim, Han Seob Cha
  • Patent number: 8110456
    Abstract: A self aligning memory device, with a memory element switchable between electrical property states by the application of energy, includes a substrate and word lines, at least the sides of the word lines covered with a dielectric material which defines gaps. An access device within a substrate has a first terminal under a second gap and second terminals under first and third gaps. First and second source lines are in the first and third gaps and are electrically connected to the second terminals. A first electrode in the second gap is electrically connected to the first terminal. A memory element in the second gap is positioned over and electrically connected to the first electrode. A second electrode is positioned over and contacts the memory element. The first contact, the first electrode, the memory element and the second electrode are self aligning. A portion of the memory element may have a sub lithographically dimensioned width.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: February 7, 2012
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang-Lan Lung
  • Patent number: 8105889
    Abstract: Methods of forming Group III-nitride transistor device include forming a protective layer on a Group III-nitride semiconductor layer, forming a via hole through the protective layer to expose a portion of the Group III-nitride semiconductor layer, and forming a masking gate on the protective layer. The masking gate includes an upper portion having a width that is larger than a width of the via hole and having a lower portion extending into the via hole. The methods further include implanting source/drain regions in the Group III-nitride semiconductor layer using the masking gate as an implant mask.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: January 31, 2012
    Assignee: Cree, Inc.
    Inventors: R. Peter Smith, Scott T. Sheppard
  • Patent number: 8093107
    Abstract: A thyristor based semiconductor device includes a thyristor having cathode, P-base, N-base and anode regions disposed in electrical series relationship. The N-base region for the thyristor has a cross-section that defines an inverted “T” shape, wherein a buried well in semiconductor material forms is operable as a part of the N-base. The stem to the inverted “T” shape extends from the upper surface of the semiconductor material to the buried well. The P-base region for the thyristor extends laterally outward from a side of the stem that is opposite the anode region of the thyristor, and is further bounded between the buried well and a surface of the semiconductor material. A thinned portion for the N-base is defined between the cathode region of the thyristor and the buried well, and may include supplemental dopant of concentration greater than that for some other portion of the N-base.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: January 10, 2012
    Assignee: T-RAM Semiconductor, Inc.
    Inventors: Farid Nemati, Scott Robins, Kevin J. Yang
  • Patent number: 8080452
    Abstract: The invention relates to a method for selective deposition of Si or SiGe on a Si or SiGe surface. The method exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake step at a temperature lower or equal than 800° C., a subsequent deposition step of Si or SiGe will not lead to a layer deposition in the first surface region. This effect is used for selective deposition of Si or SiGe in the second surface region, which is not doped with Boron in the suitable concentration range, or doped with another dopant, or not doped. The method thus saves a usual photolithography sequence required for selective deposition of Si or SiGe in the second surface region according to the prior art.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: December 20, 2011
    Assignees: NXP, B.V., STMicroelectronics (Crolles 2) SAS
    Inventors: Alexandre Mondot, Markus Gerhard Andreas Muller, Thomas Kormann
  • Patent number: 7955918
    Abstract: A semiconductor device, and particularly a high electron mobility transistor (HEMT), having a plurality of epitaxial layers and experiencing an operating (E) field. A negative ion region in the epitaxial layers to counter the operating (E) field. One method for fabricating a semiconductor device comprises providing a substrate and growing epitaxial layers on the substrate. Negative ions are introduced into the epitaxial layers to form a negative ion region to counter operating electric (E) fields in the semiconductor device. Contacts can be deposited on the epitaxial layers, either before or after formation of the negative ion region.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: June 7, 2011
    Assignee: Cree, Inc.
    Inventors: Yifeng Wu, Marcia Moore, Tim Wisleder, Primit Parikh
  • Patent number: 7902008
    Abstract: A method for fabricating a stressed MOS device in and on a semiconductor substrate is provided. The method comprises the steps of forming a gate electrode overlying the semiconductor substrate and etching a first trench and a second trench in the semiconductor substrate, the first trench and the second trench formed in alignment with the gate electrode. A stress inducing material is selectively grown in the first trench and in the second trench and conductivity determining impurity ions are implanted into the stress inducing material to form a source region in the first trench and a drain region in the second trench. To preserve the stress induced in the substrate, a layer of mechanically hard material is deposited on the stress inducing material after the step of ion implanting.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: March 8, 2011
    Assignee: GlobalFoundries Inc.
    Inventors: Igor Peidous, Mario M. Pelella
  • Patent number: 7902013
    Abstract: An electrically floating region is formed in the top surface of a semiconductor wafer to implement a radio frequency (RF) blocking structure. The RF blocking structure lies below the metal pads and traces that carry an RF signal in a metal interconnect structure to substantially reduces the attenuation of the RF signal.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: March 8, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Jeffrey A. Babcock, Yongseon Koh
  • Patent number: 7875915
    Abstract: An integrated circuit includes at least one photodiode associated with a read transistor. The photodiode is formed from a stack of three semiconductor layers comprising a buried layer, an floating substrate layer and an upper layer. The drain region and/or the source region of the transistor are incorporated within the upper layer. The buried layer is electrically isolated from the upper layer so as to allow the buried layer to be biased independently of the upper layer.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: January 25, 2011
    Assignee: STMicroelectronics S.A.
    Inventors: François Roy, Arnaud Tournier
  • Patent number: 7799590
    Abstract: The aperture ratio of a pixel of a reflecting type display device is improved without increasing the number of masks and without using a black mask. Locations for light shielding between pixels are arranged such that a pixel electrode overlaps with a portion of a gate wiring and a source wiring. In locations for shielding TFTs, a high pixel aperture ratio is realized by forming a color filter (red, or lamination of red and blue), formed on an opposing substrate.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: September 21, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 7754551
    Abstract: This invention proposes a method for making very low threshold voltage (Vt) metal-gate/high-? CMOSFETs using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with VLSI. At 1.2 nm equivalent-oxide thickness (EOT), good effective work-function of 5.3 and 4.1 eV, low Vt of +0.05 and 0.03 V, high mobility of 90 and 243 cm2/Vs, and small 85° C. bias-temperature-instability <32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: July 13, 2010
    Assignee: National Chiao Tung University
    Inventor: Albert Chin
  • Patent number: 7727827
    Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: June 1, 2010
    Assignee: GlobalFoundries Inc.
    Inventors: Frank Wirbeleit, Rolf Stephan, Manfred Horstmann
  • Patent number: 7645652
    Abstract: A CMOS image sensor and a method of fabricating the same are provided. The CMOS image sensor includes: a semiconductor substrate of a first conductivity type having a photodiode region and a transistor region defined therein; a gate electrode formed above the transistor region of the semiconductor substrate with a gate insulating layer interposed therebetween; a first impurity region formed of the first conductivity type in the semiconductor substrate below the gate electrode and having a higher concentration of first conductivity type ions than the semiconductor substrate; and a second impurity region formed of a second conductivity type in the photodiode region of the semiconductor substrate.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: January 12, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Lim Keun Hyuk
  • Patent number: 7608192
    Abstract: An image sensor and a method for fabricating the same are provided. The image sensor includes a first conductive type substrate including a trench formed in a predetermined portion of the first conductive type substrate, a second conductive type impurity region for use in a photodiode, formed below a bottom surface of the trench in the first conductive type substrate, and a first conductive type epitaxial layer for use in the photodiode, buried in the trench.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: October 27, 2009
    Inventors: Hee Jeen Kim, Han Seob Cha
  • Patent number: 7605017
    Abstract: Methods of manufacturing a semiconductor device and resulting products. The semiconductor device includes a semiconductor substrate, a hetero semiconductor region hetero-adjoined with the semiconductor substrate, a gate insulation layer contacting the semiconductor substrate and a heterojunction of the hetero semiconductor region, a gate electrode formed on the gate insulation layer, an electric field alleviation region spaced apart from a heterojunction driving end of the heterojunction that contacts the gate insulation layer by a predetermined distance and contacting the semiconductor substrate and the gate insulation layer, a source electrode contacting the hetero semiconductor region and a drain electrode contacting the semiconductor substrate. A mask layer is formed on the hetero semiconductor region, and the electric field alleviation region and the heterojunction driving end are formed by using at least a portion of the first mask layer.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: October 20, 2009
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Tetsuya Hayashi, Masakatsu Hoshi, Hideaki Tanaka, Shigeharu Yamagami
  • Patent number: 7592212
    Abstract: Methods of determining a total impurity dose for a plasma doping process, and an apparatus configured to determine same. A total ion dose implanted in a semiconductor substrate is directly measured, such as by utilizing a Faraday cup. A ratio of impurity-based ion species to non-impurity-based ion species in a plasma generated by the plasma doping process and a ratio of each impurity-based ion species to a total impurity-based ion species in the plasma are directly measured. The ratios may be directly measured by ion mass spectroscopy. The total ion dose and the ratios are used to determine the total impurity dose. The apparatus includes an ion detector, an ion mass spectrometer, a dosimeter, and software.
    Type: Grant
    Filed: April 6, 2007
    Date of Patent: September 22, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Shu Qin, Allen McTeer
  • Patent number: 7585714
    Abstract: It is an object of the present invention to provide a laser irradiation apparatus being able to crystallize the semiconductor film homogeneously while suppressing the variation of the crystallinity in the semiconductor film and the unevenness of the state of the surface thereof. It is another object of the present invention to provide a method for manufacturing a semiconductor device using the laser irradiation apparatus which can suppress the variation of on-current, mobility, and threshold of TFT, and to further provide a semiconductor device manufactured with the manufacturing method.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: September 8, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Osamu Nakamura, Hironobu Shoji
  • Patent number: 7550358
    Abstract: A method to create piezoresistive sensing elements and electrostatic actuator elements on trench sidewalls is disclosed. P-type doped regions are formed in the upper surface of an n-type substrate. A trench is formed in the substrate (e.g. by DRIE process) intersecting with the doped regions and defining a portion of the substrate which is movable in the plane of the substrate relative to the rest of the substrate. Then diffusion of P-type dopant into the trench side-walls creates piezoresistive elements and electrode elements for electrostatic actuation. Owing to the intersection of two doped regions, there are good electrical paths between the electrical elements on the trench side-walls and the previously P-type doped portions on the wafer surface. The trench intersects with insulating elements, so that insulating elements mutually insulate adjacent electrical elements. P-n junctions between the electrical elements and the substrate insulate the electrical elements from the substrate.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: June 23, 2009
    Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
    Inventors: Xinxin Li, Heng Yang, Yuelin Wang, Songlin Feng
  • Patent number: 7537971
    Abstract: A method for fabricating a complementary metal-oxide semiconductor (CMOS) image sensor includes performing an ion implantation process onto a photodiode region in a first conductivity type semiconductor layer to form a second conductivity type first impurity region, and performing an annealing process in a gas atmosphere including first conductivity type impurity atoms to form a first conductivity type second impurity region underneath a surface of the first conductivity type semiconductor layer in the second conductivity type first impurity region, wherein the first conductivity type second impurity region is doped with the diffused first conductivity impurity atoms.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: May 26, 2009
    Assignee: MagnaChip Semiconductor Ltd.
    Inventor: Han-Seob Cha
  • Patent number: 7528410
    Abstract: A semiconductor device that can be manufactured with a reduced cost by decreasing the number of masks is disclosed, and a method for manufacturing the semiconductor device is disclosed.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: May 5, 2009
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Tatsuya Arao, Takeshi Noda, Takuya Matsuo, Hidehito Kitakado, Masanori Kyoho
  • Patent number: 7501317
    Abstract: A junction leak current of a transistor including a silicide layer provided on a source/drain region is to be suppressed. After forming a gate electrode over a chip-side surface of a silicon substrate, an insulating layer is formed over the gate electrode. The insulating layer is etched back so as to form a sidewall that covers the sidewall of the gate electrode, and a region adjacent to the sidewall on the chip-side surface of the silicon substrate, where a source/drain region is to be formed, is etched so as to form a generally horizontal scraped section on the chip-side surface. Then a dopant is implanted to the silicon substrate around the gate electrode, to thereby form the source/drain region. On the chip-side surface of the silicon substrate where the gate electrode is provided, a Ni layer is formed, so that the Ni layer is reacted with the silicon substrate thus to form a Ni-silicide layer.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: March 10, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Tomoko Matsuda, Hiroshi Kitajima
  • Patent number: 7432144
    Abstract: A method of forming a transistor including: forming a gate oxide layer pattern and gate polysilicon layer pattern on a silicon substrate; forming a low energy ion implantation region aligned with both sidewalls of the gate polysilicon layer pattern; forming an amorphous region at a lower part of both sidewalls of the gate polysilicon layer pattern; reducing a channel length by removing the amorphous region so as to form a notch at a lower part of both sidewalls of the gate polysilicon layer pattern; forming a gate spacer at both sidewalls of the gate polysilicon layer pattern; and forming a high energy ion implantation region by high energy ion implantation of source/drain impurities into an entire surface of the silicon substrate including the gate polysilicon layer pattern and gate spacer.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: October 7, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Kye-Nam Lee
  • Patent number: 7348227
    Abstract: A TFT having a high threshold voltage is connected to the source electrode of each TFT that constitutes a CMOS circuit. In another aspect, pixel thin-film transistors are constructed such that a thin-film transistor more distant from a gate line drive circuit has a lower threshold voltage. In a further aspect, a control film that is removable in a later step is formed on the surface of the channel forming region of a TFT, and doping is performed from above the control film.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: March 25, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Naoto Kusumoto, Hideto Ohnuma, Koichiro Tanaka
  • Patent number: 7244642
    Abstract: The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a spacer material (415) located over gate electrodes (250) and a doped region (255) located between the gate electrodes (250), removing a portion of the spacer material (415) and the protective layer (510) located over the gate electrodes (250). A remaining portion of the spacer material (415) remains over the top surface of the gate electrodes (250) and over the doped region (255), and a portion of the protective layer (510) remains over the doped region (255). The method further comprises removing the remaining portion of the spacer material (415) to form spacer sidewalls on the gate electrodes (250), expose the top surface of the gate electrodes (250), and leave a remnant of the spacer material (415) over the doped region (255).
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: July 17, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Steven A. Vitale, Hyesook Hong, Freidoon Mehrad
  • Patent number: 7238577
    Abstract: A method is provided for obtaining extremely fine pitch N-type and P-type stripes that form the voltage blocking region of a superjunction power device. The stripes are self-aligned and do not suffer from alignment tolerances. The self-aligned, fine pitch of the alternating stripes enables improvements in on-state resistance, while ensuring that the superjunction device is fully manufacturable. Only one masking step is required to fabricate the alternating N-type and P-type stripes.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: July 3, 2007
    Assignee: National Semiconductor Corporation
    Inventor: Zia Alan Shafi
  • Patent number: 7226824
    Abstract: Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: June 5, 2007
    Assignee: Intel Corporation
    Inventors: Cory E. Weber, Mark Armstrong, Harold Kennel, Tahir Ghani, Paul A. Packan, Scott Thompson
  • Patent number: 7198967
    Abstract: There is provided an active matrix type semiconductor display device which realizes low power consumption and high reliability. In the active matrix type semiconductor display device of the present invention, a counter electrode is divided into two, different potentials are applied to the two counter electrodes, respectively and inversion driving is carried out each other. Since a potential of an image signal can be made low by doing so, it is possible to lower a voltage necessary for operation of a driver circuit. As a result, it is possible to realize improvement of reliability of an element such as a TFT and reduction of consumed electric power. Moreover, since it is possible to lower a voltage of a timing pulse supplied by the driver circuit, a booster circuit can be omitted, and reduction of an area of the driver circuit can be realized.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: April 3, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yukio Tanaka, Shou Nagao
  • Patent number: 7160762
    Abstract: It is an object of the present invention to provide a laser irradiation apparatus being able to crystallize the semiconductor film homogeneously while suppressing the variation of the crystallinity in the semiconductor film and the unevenness of the state of the surface thereof. It is another object of the present invention to provide a method for manufacturing a semiconductor device using the laser irradiation apparatus which can suppress the variation of on-current, mobility, and threshold of TFT, and to further provide a semiconductor device manufactured with the manufacturing method.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: January 9, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Osamu Nakamura, Hironobu Shoji
  • Patent number: 7157321
    Abstract: A semiconductor device that can be manufactured with a reduced cost by decreasing the number of masks is disclosed, and a method for manufacturing the semiconductor device is disclosed.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: January 2, 2007
    Assignees: Sharp Kabushiki Kaisha, Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Arao, Takeshi Noda, Takuya Matsuo, Hidehito Kitakado, Masanori Kyoho
  • Patent number: 7122408
    Abstract: A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow highly-doped surface layer has a thickness of about 100 Angstroms to about 500 Angstroms and a dopant concentration of about 5×1017 atoms per cm3 to about 1×1019 atoms per cm3. The ultra-shallow highly-doped surface layer is formed by diffusion of ions from a doped layer into the substrate or by a plasma doping process. The ultra-shallow pinned layer is in contact with a charge collection region of a second conductivity type.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: October 17, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Chandra Mouli, Howard E. Rhodes, Richard A. Mauritzson
  • Patent number: 7063991
    Abstract: Disclosed herein are various methods of determining characteristics of doped regions on device wafers, and a system for accomplishing same. In one illustrative embodiment, the method includes providing a device substrate comprising a plurality of masked areas, a plurality of unmasked areas, and at least one doped region formed in the substrate, determining a ratio between the unmasked areas and the masked areas for the device substrate, illuminating an area of the device substrate comprising the masked areas, the unmasked areas, and at least one doped region, and measuring an induced surface photovoltage of the device substrate while accounting for the ratio of the unmasked areas and the masked areas of the device substrate.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: June 20, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Zhiyong Zhao, Christian Krueger
  • Patent number: 6960498
    Abstract: A doping method capable of controlling a dose amount in response to a change the ratio in ion species during a doping process, a control system for controlling a doping amount, and a doping apparatus having a control system are provided. An ion current value of a specific ion in an ion beam is measured. There is an ion detector that measures an ion current value of a specific ion in an ion beam and enters the obtained monitor signal into a control means. Set data for setting a predetermined dose amount is entered into the control means, convert data for obtaining an actual dose amount from the monitor signal is entered into the control means by a memory means. The control means performs data processing on the basis of the input monitor signal and the convert data, a control signal for obtaining the predetermined dose amount is entered from the control means to the dose amount control system to dope the controlled ion beam into the target material.
    Type: Grant
    Filed: July 2, 2003
    Date of Patent: November 1, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Osamu Nakamura