Abstract: An embodiment device includes a first source/drain region over a semiconductor substrate and a dummy fin adjacent the first source/drain region. The dummy fin comprising: a first portion comprising a first film and a second portion over the first portion, wherein the second portion comprises: a second film; and a third film. The third film is between the first film and the second film, and the third film is made of a different material than the first film and the second film. A width of the second portion is less than a width of the first portion. The device further comprises a gate stack along sidewalls of the dummy fin.

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of isolation structures on the semiconductor substrate, and a plurality of blocking structures disposed directly over the isolation structures. The blocking structures have a lower reflectivity than the isolation structures.

Abstract: A semiconductor device includes a gate stack over a substrate. The semiconductor device further includes an interlayer dielectric (ILD) at least partially enclosing the gate stack. The ILD includes a first portion doped with an oxygen-containing material. The ILD further includes a second portion doped with a large species material, wherein the second portion includes a first sidewall substantially perpendicular to a top surface of the substrate, and the second portion includes a second sidewall having a positive angle with respect to the first sidewall.

Abstract: A semiconductor device includes a substrate, a first gate structure, a plurality of first gate spacers, a second gate structure, and a plurality of second gate spacers. The substrate has a first fin structure and a second fin structure. The first gate structure is over the first fin structure, in which the first gate structure includes a first high dielectric constant material and a first metal. A bottom surface of the first high dielectric constant material is higher than bottom surfaces of the first gate spacers. The second gate structure is narrower than the first gate structure and over the second fin structure, in which the second gate structure includes a second high dielectric constant material and a second metal. A bottom surface of the second high dielectric constant material is lower than bottom surfaces of the second gate spacers.

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of isolation structures on the semiconductor substrate, and a plurality of blocking structures disposed directly over the isolation structures. The blocking structures have a lower reflectivity than the isolation structures.

Abstract: In a gate last metal gate process for forming a transistor, a dielectric layer is formed over an intermediate transistor structure, the intermediate structure including a dummy gate electrode, typically formed of polysilicon. Various processes, such as patterning the polysilicon, planarizing top layers of the structure, and the like can remove top portions of the dielectric layer, which can result in decreased control of gate height when a metal gate is formed in place of the dummy gate electrode, decreased control of fin height for finFETs, and the like. Increasing the resistance of the dielectric layer to attack from these processes, such as by implanting silicon or the like into the dielectric layer before such other processes are performed, results in less removal of the top surface, and hence improved control of the resulting structure dimensions and performance.

Abstract: A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.

Abstract: A semiconductor structure and a method of forming the same are provided. According to an aspect of the disclosure, a semiconductor structure includes a first layer having a bottom portion and a sidewall connected to the bottom portion, a metal layer disposed above the bottom portion of the first layer, and a second layer disposed above the metal layer and laterally surrounded by the sidewall of the first layer. The metal layer includes a periphery and a middle portion surrounded by the periphery, the middle portion being thicker than the periphery, and a first etch rate of an etchant with respect to the metal layer is uniform throughout the metal layer and is greater than a second etch rate of the etchant with respect to the second layer.

Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.

Abstract: A method for producing a microelectronic device with one or more transistor(s) including forming a first gate on a region of a semiconductor layer, forming a first cavity in the semiconductor layer, the first cavity having a wall contiguous with the given region, filling the first cavity in such a way as to form a first semiconductor block wherein a source or drain region of the first transistor is capable of being produced, by epitaxial growth of a first semiconductor material in the first cavity, the growth being carried out such that a first zone of predetermined thickness of the layer of first semiconductor material lines the wall contiguous with the given region, epitaxial growth of a second zone made of a second semiconductor material on the first zone.

Abstract: The present disclosure provides a fin-like field effect transistor (FinFET) device and a method of fabrication thereof. The method includes forming a fin on a substrate and forming a gate structure wrapping the fin. A pair of spacers is formed adjacent to the gate structure and the gate structure is removed. Afterwards, a pair of oxide layers is deposited adjacent to the pair of spacers. A pair of gate dielectric layers is deposited next to the pair of oxide layers. Finally, a metal gate is formed between the pair of gate dielectric layers.

Abstract: An exemplary integrated circuit comprises: a first device gate disposed over the first device region, the first device gate comprising a first interfacial layer and a first dielectric layer; a second device gate disposed over the second device region, the second device gate comprising a second interfacial layer and a second dielectric layer; and a third device gate disposed over the third device region, the third device gate comprising a third interfacial layer and a third dielectric layer, wherein the first interfacial layer, the second interfacial layer, and the third interfacial layer are different from each other in at least one of a thickness and an interfacial material.

Abstract: A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.

Abstract: A semiconductor structure includes a first layer having a recessed surface, a metal layer disposed above the first layer, and a second layer disposed above the metal layer and confined by the recessed surface. The second layer includes a first lateral side and a second lateral side. A first thickness of the second layer in a middle portion between the first lateral side and the second lateral side is less than a second thickness of at least one of the first lateral side and the second lateral side of the second layer. The metal layer has a same material across an entire range covered by the second layer.

Abstract: A method for making a semiconductor device may include forming at least one double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, and forming a first barrier layer on the first doped semiconductor layer and including a superlattice. The superlattice may include stacked groups of layers, each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming an intrinsic semiconductor layer on the first barrier layer, forming a second barrier layer on the intrinsic semiconductor layer, and forming a second doped semiconductor layer on the second superlattice layer.

Abstract: Methods and apparatuses for forming high modulus silicon oxide spacers using atomic layer deposition are provided. Methods involve depositing at high temperature, using high plasma energy, and post-treating deposited silicon oxide using ultraviolet radiation. Such silicon oxide spacers are suitable for use as masks in multiple patterning applications to prevent pitch walking.

Abstract: Processes and overturned thin film device structures generally include a metal gate having a concave shape defined by three faces. The processes generally include forming the overturned thin film device structures such that the channel self-aligns to the metal gate and the contacts can be self-aligned to the sacrificial material.

Abstract: The disclosure is directed to methods of planarizing an integrated circuit structure including: forming a dielectric over a first nitride layer; planarizing the dielectric to a top surface of a set of nitride fins in a first region and removing the dielectric from a second region to expose the substantially planar upper surface in a second region; forming a second nitride layer over the dielectric and the top surface of the set of nitride fins and over the substantially planar upper surface; planarizing the second nitride layer such that the second nitride layer in the second region is planar with the top surface of the dielectric and the set of nitride fins, and such that the second nitride layer is removed from the first region; and performing an etch such that the first nitride layer in the first region is planar with the first nitride layer in the second region.

Abstract: One illustrative method disclosed herein includes, among other things, forming first and second vertically-oriented channel (VOC) semiconductor structures for, respectively, first and second vertical transistor devices, and forming first and second top spacers, respectively, around the first and second VOC structures, wherein the first spacer thickness is greater than the second spacer thickness. In this example, the method also includes performing at least one epitaxial deposition process to form a first top source/drain structure around the first VOC structure and above the first top spacer and a second top source/drain structure around the second VOC structure and above the second top spacer, and performing an anneal process so as to cause dopants in the first and second doped top source/drain structures to migrate into, respectively, the first and second VOC structures.

Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.

Abstract: The present disclosure relates to a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to a channel region. In some embodiments, the transistor device has an epitaxial source region arranged within a substrate. An epitaxial drain region is arranged within the substrate and is separated from the epitaxial source region by a channel region. A first DSM region, which has a stressed lattice configured to generate stress within the channel region, extends from below the epitaxial source region to a location within the epitaxial source region. A second DSM region, which has a stressed lattice configured to generate stress within the channel region, extends from below the epitaxial drain region to a location within the epitaxial drain region.

Abstract: A semiconductor structure comprising a first layer, a metal layer and a second layer is disclosed. The first layer comprises a recessed surface. The metal layer is above a portion of the recessed surface. The second layer is above the metal layer and confined by the recessed surface. The second layer comprises a top surface, a first lateral side and a second lateral side. The etch rate of an etchant with respect to the metal layer is greater than the etch rate of the etchant with respect to the second layer. The thickness of the second layer in the middle of the second layer is less than the thickness of the second layer at the first lateral side or the second lateral side. A method of forming a semiconductor structure is disclosed.

Abstract: A method of manufacturing a semiconductor device according to one or more exemplary embodiments of the present inventive concept includes forming a plurality of dummy gates on a substrate. Each of the dummy gates includes a gate mask disposed on an upper surface of each of the dummy gates. A spacer is disposed on at least two sides of the dummy gates. An insulating interlayer is formed on the gate mask and the spacer. A first polishing including chemical mechanical polishing is performed on portions of the gate mask and the insulating interlayer by using a slurry composite having a first mixing ratio. A second polishing including chemical mechanical polishing is formed on remaining portions of the gate mask and the insulating interlayer to expose upper surfaces of the plurality of dummy gates, by using a slurry composite having a second mixing ratio.

Abstract: An integrated circuit includes a cell and a first plurality of conductive segments. Each of the first plurality of conductive segments has a first predetermined width, and the first plurality of conductive segments includes a first conductive segment, and a second conductive segment. The first conductive segment and the second conductive segment are coupled to the cell to transmit a signal, and a distance between the first conductive segment and the second conductive segment is greater than the first predetermined width.

Abstract: A method for forming transistors includes providing a substrate having at least a dummy gate structure having at least dummy gate layer; forming a first dielectric layer on the substrate; thinning the first dielectric layer with a pre-determined depth to cause a top surface of the dielectric layer to be lower than a top surface of the dummy gate structure and expose top portions of side surfaces of the dummy gate structure; forming a stress layer on the exposed portions of the side surfaces of the dummy gate structure; forming a second dielectric layer on the thinned first dielectric layer; removing the dummy gate layer to form an opening with an enlarged top size caused by releasing stress in the stress layer previously formed on the exposed portions of the side surfaces of the dummy gate structure; and forming a gate electrode layer in the opening.

Abstract: A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the high dielectric constant layer. An aluminum doped TiC layer has a thickness greater than 5 nm wherein the configuration of layers is employed between two regions as a diffusion barrier to prevent mass diffusion between the two regions.

Abstract: An embodiment device includes a gate stack extending over a semiconductor substrate, a hard mask disposed on a top surface of the gate stack, and a low-k dielectric spacer on a side of the gate stack. A top of the low-k dielectric spacer is lower than an upper surface of the hard mask. The device further includes a contact electrically connected to a source/drain region adjacent the gate stack. The contact extends laterally over the low-k dielectric spacer, and a dielectric material is disposed between the contact and the low-k dielectric spacer. The dielectric material has a higher selectivity to etching than the low-k dielectric spacer.

Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising the steps of: forming a dummy gate stack structure on a substrate, wherein the dummy gate stack structure contains carbon-based materials; forming source/drain region in the substrate on both sides of the dummy gate stack structure; performing etching to remove the dummy gate stack structure until the substrate is exposed, resulting in a gate trench; and forming a gate stack structure in the gate trench. In accordance with the method for manufacturing a semiconductor device of the present invention, the dummy gate made of carbon-based materials is used to substitute the dummy gate made of silicon-based materials, then no oxide liner and/or etch blocking layer needs be added while the dummy gate is removed by etching in the gate last process, thus the reliability of device is ensured while the process is simplified and the cost is reduced.

Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is selectively formed to cover the exposed portion of the semiconductor fin, wherein a thickness of the dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed between the spacers to cover the second dielectric layer, the sidewalls of the spacers and the exposed portions of the insulators.

Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. The present disclosure relates to a method of forming a strain inducing layer or cap layer at the RPG (replacement poly silicon gate) stage of a finFET device formation process. In some embodiments, the strain inducing layer is doped to reduce the external resistance.

Abstract: Embodiments of the present invention provide a fin type field effect transistor (FinFET) and methods of fabrication. A punchthrough stopper region is formed on a semiconductor substrate. An insulator layer, such as silicon oxide, is formed on the punchthrough stopper. Fins and gates are formed on the insulator layer. The insulator layer is then removed from under the fins, exposing the punchthrough stopper. An epitaxial semiconductor region is grown from the punchthrough stopper to envelop the fins, while the insulator layer remains under the gate. By growing the fin merge epitaxial region mainly from the punchthrough stopper, which is part of the semiconductor substrate, it provides a higher growth rate then when growing from the fins. The higher growth rate provides better epitaxial quality and dopant distribution.

Abstract: A semiconductor device includes an interlayer insulating film formed on a substrate and including a trench, a gate insulating film formed in the trench, a work function adjusting film formed on the gate insulating film in the trench along sidewalls and a bottom surface of the trench, and including an inclined surface having an acute angle with respect to the sidewalls of the trench, and a metal gate pattern formed on the work function adjusting film in the trench to fill up the trench.

Abstract: A semiconductor device and a method for manufacturing the same. The method includes steps hereinafter. A substrate is provided with a first dielectric layer thereon. The first dielectric layer is provided with a trench. Then, a metal layer is formed to fill the trench and to cover the surface of the first dielectric layer. The metal layer is partially removed so that a remaining portion of the metal layer covers the first dielectric layer. A treatment process is performed to transform the remaining portion of the metal layer into a passivation layer on the top portion and a gate metal layer on the bottom portion. A chemical-mechanical polishing process is performed until the first dielectric layer is exposed so that a remaining portion of the passivation layer remains in the trench.

Abstract: A method for fabricating a metal gate structure includes providing a substrate on which a dielectric layer, a first trench disposed in the dielectric layer, a first metal layer filling up the first trench, a second trench disposed in the dielectric layer, a second metal layer filling up the second trench are disposed, and the width of the first trench is less than the width of the second trench; forming a mask layer to completely cover the second trench; performing a first etching process to remove portions of the first metal layer when the second trench is covered by the mask layer; and performing a second etching process to concurrently remove portions of the first metal layer and portions of the second metal layer after the first etching process.

Abstract: A manufacturing process of an etch stop layer is provided. The manufacturing process includes steps of providing a substrate; forming a gate stack structure over the substrate, wherein the gate stack structure at least comprises a dummy polysilicon layer and a barrier layer; removing the dummy polysilicon layer to define a trench and expose a surface of the barrier layer; forming a repair layer on the surface of the barrier layer and an inner wall of the trench; and forming an etch stop layer on the repair layer. In addition, a manufacturing process of the gate stack structure with the etch stop layer further includes of forming an N-type work function metal layer on the etch stop layer within the trench, and forming a gate layer on the N-type work function metal layer within the trench.

Abstract: A semiconductor structure includes a source region, a drain region, a channel region and a gate region over a bulk silicon substrate. The gate region further includes a dielectric layer and one or more work function layers disposed over the dielectric layer. A first filler material, such as a flowable oxide is provided over the source region and the drain region. A second filler material, such as an organic material, is provided within the gate region. The first filler material and the second filler material are selectively removed to create, source, drain and gate openings. The gate, source and drain openings are filled simultaneously with a metal, such as tungsten, to create a metal gate structure, source contact and drain contact.

Abstract: At least one doped semiconductor material region is formed over a crystalline insulator layer. A disposable gate structure and a planarization dielectric layer laterally surrounding the disposable gate structure are formed over the at least one doped semiconductor material region. The disposable gate structure is removed selective to the planarization dielectric layer to form a gate cavity. Portions of the at least one doped semiconductor material region are removed from underneath the gate cavity. Remaining portions of the at least one doped semiconductor material region constitute a source region and a drain region. A faceted crystalline dielectric material portion is grown from a physically exposed surface of the crystalline insulator layer. A contoured channel region is epitaxially grown on the faceted crystalline dielectric material portion. The contoured channel region increases the distance that charge carriers travel relative to a separation distance between the source region and the drain region.

Abstract: A semiconductor apparatus and a manufacturing method therefor is described. The semiconductor apparatus comprises a substrate and a gate structure for a N-channel semiconductor device above the substrate. A recess is formed at a lower end portion of at least one of two sides of the gate where it is adjacent to a source region and a drain region, of the N-channel semiconductor. The channel region of the N-channel semiconductor device has enhanced strain. The apparatus can further have a gate structure for a P-channel semiconductor device above the substrate.

Abstract: In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET having complete middle of line integration. Specifically, a hard mask layer and set of spacers are removed from the gate stacks leaving behind (among other things) a set of dummy gates. A liner layer is formed over the set of dummy gates and over a source-drain region adjacent to the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates and the source-drain region. An inter-layer dielectric (ILD) is then deposited over the set of dummy gates and over the source-drain region, and the set of dummy gates are then removed. The result is an environment in which a self-aligned contact to the source-drain region can be deposited.

Abstract: A solid state detector with alpha rhombohedral red boron is disclosed. The solid state detector detects neutrons, especially thermal neutrons. The detector may include a body of alpha rhombohedral red boron disposed between electrodes, a power supply for applying a voltage to said electrodes, and a detecting device that detects and measures a current pulse emitted from said body of alpha rhombohedral red boron to detect the neutrons.

Abstract: A semiconductor structure may be formed by forming a sacrificial gate above a substrate covered by a hard mask, depositing a first interlevel dielectric (ILD) layer above the sacrificial gate, recessing the first ILD layer to a thickness less than the height of the sacrificial gate, depositing an etch barrier layer above the first ILD layer, depositing a second ILD layer above the etch barrier layer, planarizing the second ILD layer and the etch barrier layer to expose the hard mask using the hard mask as a planarization stop, removing the hard mask and sacrificial gate to form a gate cavity, forming a replacement metal gate in the gate cavity, removing the second ILD layer, and planarizing the replacement metal gate using the etch barrier layer as a planarization stop. A supplementary electrode layer may be formed above the replacement metal gate prior to planarizing the replacement metal gate.

Abstract: The present disclosure provides a method for forming a semiconductor device that includes forming a replacement gate structure overlying a channel region of a substrate. A mandrel dielectric layer is formed overlying source and drain regions of the substrate. The replacement gate structure is removed to provide an opening exposing the channel region of the substrate. A functional gate structure is formed over the channel region including a work function metal layer. A protective cap structure is formed over the functional gate structure. At least one via is etched through the mandrel dielectric layer selective to the protective cap structure to expose a portion of at least one of the source region and the drain region. A conductive fill is then formed in the vias to provide a contact to the at least one of the source region and the drain region.

Abstract: A device includes a semiconductor substrate. A gate stack on the semiconductor substrate includes a gate dielectric layer and a gate conductor layer. Low-k spacers are adjacent to the gate dielectric layer. Raised source/drain (RSD) regions are adjacent to the low-k spacers. The low-k spacers are embedded in an ILD on the RSD regions.

Abstract: A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally formed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench.

Abstract: A method of forming a semiconductor device comprising a dummy gate interconnect includes forming a dummy gate on a substrate, the dummy gate comprising a dummy gate metal layer located on the substrate, and a dummy gate polysilicon layer located on the dummy gate metal layer; forming an active gate on the substrate, the active gate comprising an active gate metal layer located on the substrate, and an active gate polysilicon layer located on the active gate metal layer; and etching the dummy gate polysilicon layer to remove at least a portion of the dummy gate polysilicon layer to form the dummy gate interconnect, wherein the active gate polysilicon layer is not etched during the etching of the dummy gate polysilicon layer.

Abstract: A method is provided for fabricating an MOS transistor. The method includes providing a semiconductor substrate; and forming a ploy silicon dummy gate structure having a high-K gate dielectric layer, a high-K gate dielectric protection layer containing nitrogen and a poly silicon dummy gate on the semiconductor substrate. The method also includes forming a source region and a drain region in the semiconductor substrate at both sides of the poly silicon dummy gate structure. Further, the method includes removing the poly silicon dummy gate to form a trench exposing the high-K gate dielectric protection layer containing nitrogen and performing a nitrogen treatment process to repair defects in the high-K gate dielectric protection layer containing nitrogen caused by removing the poly silicon dummy gate. Further, the method also includes forming a metal gate structure in the trench.

Abstract: A method for enabling fabrication of RMG devices having a low gate height variation and a substantially planar topography and resulting device are disclosed. Embodiments include: providing on a substrate two dummy gate electrodes, each between a pair of spacers; providing a source/drain region between the two dummy gate electrodes; and forming a first nitride layer over the two dummy gate electrodes and the source/drain region, wherein the first nitride layer comprises a first portion over the dummy gate electrodes and a second portion over the source/drain region, and the second portion has an upper surface substantially coplanar with an upper surface of the dummy gate electrodes.

Abstract: A self-aligned carbon nanostructure transistor is formed by a method that includes providing a material stack including a gate dielectric material having a dielectric constant of greater than silicon oxide and a sacrificial gate material. Next, a carbon nanostructure is formed on an exposed surface of the gate dielectric material. After forming the carbon nanostructure, metal semiconductor alloy portions are formed self-aligned to the material stack. The sacrificial gate material is then replaced with a conductive metal.

Abstract: A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device.

Abstract: The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET is formed on an SOI wafer, comprising: a shallow trench isolation for defining an active region in the semiconductor layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; a channel region in the semiconductor layer and sandwiched by the source region and the drain region; a back gate in the semiconductor substrate; a first dummy gate stack overlapping with a boundary between the semiconductor layer and the shallow trench isolation; and a second dummy gate stack on the shallow trench isolation, wherein the MOSFET further comprises a plurality of conductive vias which are disposed between the gate stack and the first dummy gate stack and electrically connected to the source region and the drain region respectively, and between the first dummy gate stack and the second dummy gate stack and electrically connected to the back gate.