Abstract: A method of manufacturing a semiconductor device includes forming a trench in an interlayer dielectric film on the semiconductor substrate, the trench reaching a semiconductor substrate and having a sidewall made of silicon nitride film; depositing a gate insulation film made of a HfSiO film at a temperature within a range of 200 degrees centigrade to 260 degrees centigrade, so that the HfSiO film is deposited on the semiconductor substrate which is exposed at a bottom surface of the trench without depositing the HfSiO film on the silicon nitride film; and filling the trench with a gate electrode made of metal.

Abstract: Methods are provided for fabricating a stress enhanced MOS transistor. One such method comprises the steps of depositing and patterning a layer of sacrificial material to form a dummy gate electrode and replacing the dummy gate electrode with a stressed gate electrode. After the stressed gate electrode has been formed by a replacement process, a stress liner is deposited overlying the stressed gate electrode.

Abstract: The invention provides isolated NUE (nitrogen utilization efficiency) nucleic acids and their encoded proteins. The present invention provides methods and compositions relating to altering nitrogen utilization and/or uptake in plants. The invention further provides recombinant expression cassettes, host cells, and transgenic plants.

Abstract: The present invention provides a high-k gate dielectric/metal gate MOSFET that has a reduced parasitic capacitance. The inventive structure includes at least one metal oxide semiconductor field effect transistor (MOSFET) 100 located on a surface of a semiconductor substrate 12. The least one MOSFET 100 includes a gate stack including, from bottom to top, a high-k gate dielectric 28 and a metal-containing gate conductor 30. The metal-containing gate conductor 30 has gate corners 31 located at a base segment of the metal-containing gate conductor. Moreover, the metal-containing gate conductor 30 has vertically sidewalls 102A and 102B devoid of the high-k gate dielectric 28 except at the gate corners 31. A gate dielectric 18 laterally abuts the high-k gate dielectric 28 present at the gate corners 31 and a gate spacer 36 laterally abuts the metal-containing gate conductor 30.

Abstract: When an STI element isolation structure is formed, it is formed in such a manner that its upper portion protrudes further than the surface of a substrate than by a normal STI method, and a dummy electrode pattern is formed in a gate electrode forming portion. After a source/drain is formed in alignment with a gap portion, a conductive layer formed by filling the gap portion with W is formed, the dummy electrode pattern is removed, and a gate insulating film and a gate electrode are formed.

Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the-removal of a nitride etch stop layer.

Abstract: A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained layer on the strain-inducing substrate layer. The compressively strained layer has a germanium concentration at least approximately 30 percentage points greater than the germanium concentration of the strain-inducing substrate layer, and has a thickness less than its critical thickness. The semiconductor structure also includes a tensilely strained layer on the compressively strained layer. The tensilely strained layer may be formed from silicon having a thickness less than its critical thickness.

Abstract: A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETs. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin silicon on insulator (SOI) chip. Isolation trenches at each end of the FETs, i.e., at the end of the RSD regions, isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on the RSD regions and, optionally, on the gates reduce device resistances.

Abstract: The present invention relates to a thin film transistor (TFT) substrate and method of making such a TFT substrate. The structure of the TFT substrate helps prevent damage to signal lines in non-display areas.

Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

Abstract: A method for fabricating a flash memory device is disclosed that improves hot carrier injection efficiency by forming a gate after forming source and drain implants using a sacrificial insulating layer pattern, which includes forming a sacrificial insulating pattern layer over a flash memory channel region of a semiconductor substrate; forming source and drain regions in the semiconductor substrate by ion implantation using the sacrificial insulating pattern layer as a mask; removing portions of the sacrificial insulating pattern layer; sequentially forming an ONO-type dielectric layer and a gate material layer; selectively etching the gate material layer and at least part of the gate dielectric layer to form a gate; and forming gate sidewall spacers at sides of the gate.

Abstract: A pattern forming method includes determining an allowable value of an etching conversion difference, obtaining a maximum distance between patterns generating the etching conversion difference within the allowable value, the patterns including main patterns or both main patterns and a dummy pattern, preparing a first design layout in which a first distance between the main patterns is smaller than the maximum distance, or a second design layout in which a second distance between the main patterns and the dummy pattern is smaller than the maximum distance, performing a design data conversion based on the first or second design layout to form first or second design data, and forming the main patterns by using the first design data, or forming both the main patterns and the dummy pattern by using the second design data.

Abstract: The present invention provides a method of forming a thin channel MOSFET having low external resistance. The method comprises forming a dummy gate region atop a substrate; implanting oxide forming dopant through said dummy gate to create a localized oxide region in a portion of the substrate aligned to the dummy gate region that thins a channel region; forming source/drain extension regions abutting said channel region; and replacing the dummy gate with a gate conductor.

Abstract: A method for making a semiconductor structure that overcome the dual stress liner boundary problem, without significantly increasing the overall size of the integrated circuit, is provided. In accordance with embodiments of the present invention, the dual stress liner boundary or gap therebetween is forced to land on a neighboring dummy gate region. By forcing the dual stress liner boundary or gap between the liners to land on the dummy gate region, the large stresses associated with the dual stress liner boundary or gap are transferred to the dummy gate region, not the semiconductor substrate. Thus, the impact of the dual stress liner boundary on the nearest neighboring FET is reduced. Additionally, benefits of device variability and packing density are achieved utilizing the present invention.

Abstract: A method for fabricating a gallium arsenide MOSFET device is presented. A dummy gate is formed over a gallium arsenide substrate. Source-drain extensions are implanted into the substrate adjacent the dummy gate. Dummy spacers are formed along dummy gate sidewalls and over a portion of the source-drain extensions. Source-drain regions are implanted. Insulating spacers are formed on dummy oxide spacer sidewalls. A conductive layer is formed over the source-drain regions. The conductive layer is annealed to form contacts to the source-drain regions. The dummy gate and the dummy oxide spacers are removed to form a gate opening. A passivation layer is in-situ deposited in the gate opening. The surface of the passivation layer is oxidized to create an oxide layer. A dielectric layer is ex-situ deposited over the oxide layer. A gate metal is deposited over the dielectric layer to form a gate stack in the gate opening.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are described. There is provided the semiconductor device including, a semiconductor substrate, a gate insulating layer on the semiconductor substrate, a two-step gate electrode formed on the gate insulating layer, the two-step gate electrode having a first gate electrode layer formed on the gate insulating layer and a second gate electrode layer formed on the first gate electrode layer, the gate length of the second gate electrode layer being longer than that of the first gate electrode layer, extension regions formed in the semiconductor substrate to interpose a channel region of the semiconductor substrate beneath the second gate electrode layer, and source-drain regions formed in the outside of the extension regions toward the channel region, the source-drain regions adjoining the extension regions.

Abstract: Replacement metal gates may be formed by removing a polysilicon layer from a gate structure. The gate structure may be formed by patterning the polysilicon layer and depositing a spacer layer over the gate structure such that the spacer layer has a first polish rate. The spacer layer is then etched to form a sidewall spacer. An interlayer dielectric is applied over the gate structure with the sidewall spacer. The interlayer dielectric has a second polish rate higher than the first polish rate. A hard mask may also be applied over the gate structure and implanted so that the hard mask may be more readily removed.

Abstract: A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.

Abstract: An electronic device can include an NVM array, wherein portions of word lines are formed within trenches. Insulating features are formed over heavily doped regions within the substrate. In one embodiment, charge storage stacks and a control gate electrode layer can be formed and substantially fill the trench. The insulating features help to reduce capacitive coupling between the heavily doped regions and the control gate electrode layer. In a particular embodiment, the insulating features are recessed from a top surface of a layer outside the trenches. The control gate electrode layer can form a substantially continuous electrical path along the lengths of the word lines. This particular embodiment substantially eliminates the formation of stringers or other residual etching artifacts from the control gate electrode layer within the array. A process can be performed to form the electronic device.

Abstract: Integrated circuit devices include an integrated circuit substrate having a channel region therein. A gate pattern is disposed on a top surface of the channel region. A depletion barrier layer covers a surface of the integrated circuit substrate adjacent opposite sides of the gate pattern and extending along a portion of a lateral face of the channel region. A source/drain layer is disposed on the depletion barrier layer and electrically contacting the lateral face of the channel region in a region not covered by the depletion barrier layer. The channel region may protrude from a surface of the substrate. The depletion barrier layer may be an L-shaped depletion barrier layer and the device may further include a device isolation layer disposed at a predetermined portion of the substrate through the source/drain layer and the depletion barrier layer. The depletion barrier layer and the device isolation layer may be formed of the same material.

Abstract: A semiconductor device includes a memory array having a plurality of non-volatile memory cells. Each non-volatile memory cell of the plurality of non-volatile memory cells has a gate stack. The gate stack includes a control gate and a discrete charge storage layer such as a floating gate. A dummy stack ring is formed around the memory array. An insulating layer is formed over the memory array. The dummy stack ring has a composition and height substantially the same as a composition and height of the gate stack to insure that a CMP of the insulating layer is uniform across the memory array.

Abstract: A semiconductor power device includes a substrate of a first conductivity type and an epitaxial layer of the first conductivity type over and in contact with the substrate. A first trench extends into and terminates within the epitaxial layer. A sinker trench extends from the top surface of the epitaxial layer through the epitaxial layer and terminates within the substrate. The sinker trench is laterally spaced from the first trench, and is wider and extends deeper than the first trench. The sinker trench is lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the sinker trench makes electrical contact with the substrate along the bottom of the trench and makes electrical contact with an interconnect layer along the top of the trench.

Abstract: A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable.

Abstract: A tape circuit substrate and semiconductor apparatus employing the same, and a method for forming a tape circuit substrate may reduce or eliminate electromagnetic interference (EMI) and provide a substrate or apparatus which can supply a more stable power supply voltage. The tape circuit substrate may include an insulation film and a wiring pattern formed on the insulation film to define an electronic device-mounting region and including a ground electrode. The tape circuit substrate may include a ground electrode pattern formed at the electronic device-mounting region so as to be insulated from the wiring pattern, except where the ground electrode pattern is connected to the ground electrode.

Abstract: An apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible conductive polymer bump, preferably a two-stage epoxy, on the palladium plated contact point, are provided. The present invention also relates to assemblies comprising one or more of these substrates.

Abstract: A method of manufacturing a semiconductor device includes forming a trench in an interlayer dielectric film on the semiconductor substrate, the trench reaching a semiconductor substrate and having a sidewall made of silicon nitride film; depositing a gate insulation film made of a HfSiO film at a temperature within a range of 200 degrees centigrade to 260 degrees centigrade, so that the HfSiO film is deposited on the semiconductor substrate which is exposed at a bottom surface of the trench without depositing the HfSiO film on the silicon nitride film; and filling the trench with a gate electrode made of metal.

Abstract: A method of fabricating a conductive metal oxide gate ferroelectric memory transistor includes forming an oxide layer a substrate and removing the oxide layer in a gate area; depositing a conductive metal oxide layer on the oxide layer and on the exposed gate area; depositing a titanium layer on the metal oxide layer; patterning and etching the titanium layer and the metal oxide layer to remove the titanium layer and the metal oxide layer from the substrate except in the gate area; depositing, patterning and etching an oxide layer to form a gate trench; depositing and etching a barrier insulator layer to form a sidewall barrier in the gate trench; removing the titanium layer from the gate area; depositing, smoothing and annealing a ferroelectric layer in the gate trench; depositing, patterning and etching a top electrode; and completing the conductive metal oxide gate ferroelectric memory transistor.

Abstract: Methods of stressing a channel of a transistor with a replaced gate and related structures are disclosed. A method may include providing an intrinsically stressed material over the transistor including a gate thereof; removing a portion of the intrinsically stressed material over the gate; removing at least a portion of the gate, allowing stress retained by the gate to be transferred to the channel; replacing (or refilling) the gate with a replacement gate; and removing the intrinsically stressed material. Removing and replacing the gate allows stress retained by the original gate to be transferred to the channel, with the replacement gate maintaining (memorizing) that situation. The methods do not damage the gate dielectric. A structure may include a transistor having a channel including a first stress that is one of a compressive and tensile and a gate including a second stress that is the other of compressive and tensile.

Abstract: A semiconductor device includes a gate insulating film formed on a semiconductor substrate between first diffusion layers, a gate electrode including a first gate portion formed on the gate insulating film and a second gate portion formed on the first gate portion, a first width in a channel direction of the first gate portion being substantially equal to a width in that of the gate insulating film, and a second width in the channel direction of the second gate portion being larger than the first width, a gate side wall insulating film including a first side wall portion formed on a side surface of the first gate portion and the gate insulating film and a second side wall portion formed on a side surface of the second gate portion, and a second diffusion layer formed apart from the first diffusion layers below the gate insulating film.

Abstract: The present invention discloses a semiconductor device having a pad structure for preventing a stress of a silicon nitride film. The semiconductor device includes a semiconductor substrate, a lower structure formed on the semiconductor substrate, a first insulation film formed on the lower structure, a first metal layer coupled to the lower structure through a first metal contact in the first insulation film, a second metal layer formed on the first metal layer, and a plurality of dummy gates having a concentric square structure formed at the lower portion of the pad region on the second metal layer.

Abstract: A method including forming a hard mask and an etch stop layer over a sacrificial material patterned as a gate electrode, wherein a material for the hard mask and a material for the etch stop layer are selected to have a similar stress property; removing the material for the hard mask and the material for the etch stop layer sufficient to expose the sacrificial material; replacing the sacrificial material with another material. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices, at least one of the plurality of transistor devices including a gate electrode formed on a substrate surface; a discontinuous etch stop layer conformally formed on the substrate surface and adjacent side wall surfaces of the gate electrode; and a dielectric material conformally formed over the etch stop layer.

Abstract: A method of fabricating an ultrathin SOI memory transistor includes preparing a substrate, including forming an ultrathin SOI layer of the substrate; adjusting the threshold voltage of the SOI layer; depositing a layer of silicon oxide on the SOI layer; patterning and etching the silicon oxide layer to form a sacrificial oxide gate in a gate region; depositing a layer of silicon nitride and forming the silicon nitride into a silicon nitride sidewall for the sacrificial oxide gate; depositing and smoothing a layer of amorphous silicon; selectively etching the sacrificial gate oxide; growing a layer of oxide in the gate region; depositing and smoothing a second layer of amorphous silicon; patterning and etching the second layer of amorphous silicon; implanting ion to form a source region and a drain region; annealing the structure; and depositing a layer of passivation oxide.

Abstract: An embodiment of the present invention includes a gate dielectric layer, a polysilicon layer, and a gate electrode. The gate dielectric layer is on a substrate. The substrate has a gate area, a source area, and a drain area. The polysilicon layer is on the gate dielectric layer at the gate area. The gate electrode is on the polysilicon layer and has arc-shaped sidewalls.

Abstract: Provided is a method of manufacturing a nano scale semiconductor device, such as a nano scale P-N junction device or a CMOS using nano particles without using a mask or a fine pattern. The method includes dispersing uniformly a plurality of nano particles on a semiconductor substrate, forming an insulating layer covering the nano particles on the semiconductor substrate, partly removing the upper surfaces of the nano particles and the insulating layer, selectively removing the nano particles from the insulating layer, and partly forming doped semiconductor layers in the semiconductor substrate by partly doping the semiconductor substrate through spaces formed by removing the nano particles.

Abstract: A method of manufacturing a capacitor and a metal gate on a semiconductor device comprises forming a dummy gate on a substrate, forming a trench layer on the substrate and adjacent the dummy gate, forming a capacitor trench in the trench layer, forming a bottom electrode layer in the capacitor trench, removing the dummy gate to provide a gate trench, forming a dielectric layer in the capacitor trench and the gate trench, and forming a metal layer over the dielectric layer in the capacitor trench and the gate trench.

Abstract: A method of making a reinforced semiconductor package includes forming a semiconductor interconnect tablet (24). Formation of the tablet includes providing a plurality of conductive metal tabs (10), positioning a first end (12) of the tabs (10) in a first section of a mold chase (14), positioning a second section of the mold chase (16) over a second end (18) of the tabs (10), such that the tabs (10) are anchored between the first and second sections (14, 16) of the mold chase, loading the first and second sections (14, 16) of the mold chase into a molding system (20) and performing a molding operation such that a plastic mold compound (22) is formed around the metal tabs (10) and an interconnect tablet (24) is formed. Then the first and second sections (14, 16) of the mold chase are removed from the molding system (20) and the interconnect tablet (24) is removed from the first and second sections (14, 16) of the mold chase.

Abstract: A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on the high-k gate dielectric layer, a second metal layer is formed on the first metal layer. At least part of the second metal layer is removed from above the dielectric layer using a polishing step, and additional material is removed from above the dielectric layer using an etch step.

Abstract: Method of manufacturing a semiconductor device, including a first baseline technology electronic circuit (1) and a second option technology electronic circuit (2) as functional parts of a system-on-chip, by: manufacturing the first electronic circuit (1) with a first conductive layer (6; 6) that is patterned by subjecting an exposed layer portion thereof to Reactive Ion Etching (RIE); manufacturing the second electronic circuit (2) with a second conductive layer (6; 8) that is patterned by subjecting an exposed layer portion thereof to RIE; providing a tile structure (25; 26); providing the tile structure (25; 26) with at least one dummy conductive layer (6; 8) produced in the same processing step as the second conductive layer (6; 8); and exposing the dummy conductive layer (6; 8), at least partially, to obtain an exposed dummy layer portion, and RIE-etching of that exposed portion too when the second (6; 8) conductive layer is subjected to RIE.

Abstract: A novel sequence of process steps is provided for forming void-free interlevel dielectric layers between closely spaced gate electrodes. Closely spaced gate electrodes having sidewall spacers are formed on a substrate. After using the sidewall spacers to form self-aligned source/drain contacts and self-aligned silicide contacts, the sidewall spacers are removed. By removing the sidewall spacers, the aspect ratio of the gap between adjacent closely spaced gate electrodes is substantially reduced (from greater than 5 to less than 2), thereby preventing voids during the subsequent deposition of an ILD layer.

Abstract: Disclosed is a semiconductor device having a plurality of memory cells arranged in a first direction and a second direction perpendicular to the first direction, each memory cell comprising a first insulating film formed on a semiconductor substrate, a floating gate formed on the first insulating film, a second insulating film which includes a first portion formed on a top surface of the floating gate and a second portion formed on that side surface of the floating gate which is parallel to the first direction, and a control gate which covers the first and second portions of the second insulating film, a width in the second direction of the floating gate increasing with increasing distance from its bottom, and a width in the second direction of the second portion of the second insulating film decreasing with increasing distance from its bottom.

Abstract: A semiconductor device with a replacement metal gate and the process for making the same removes a dummy gate from a semiconductor device. Within the recess left by the dummy gate is a silicon layer on a gate dielectric layer. A replacement metal is deposited on the thin silicon layer and then reacted with the silicon layer to form a metal-rich silicon layer on the gate dielectric layer.

Abstract: A method of manufacturing a semiconductor device comprises: forming a first pattern in a first region over a semiconductor substrate; forming a second pattern in a second region separated from the first region over the semiconductor substrate; depositing an interlayer insulation film to cover the first and second patterns; forming a photoresist film on the interlayer insulation film; treating the photoresist film in stepper exposure and development to form a photoresist pattern of a photomask having its device pattern matched with the first pattern and its alignment marks matched with the second pattern; selectively etching off the interlayer insulation film over the first and second patterns, with the photoresist pattern; and after removing the photoresist pattern, flattening the interlayer insulation film to expose the surfaces of the first and second patterns, respectively.

Abstract: Methods for forming notched gates and semiconductor devices utilizing the notched gates are provided. The methods utilize the formation of a dummy gate on a substrate. The dummy gate is etched to form notches in the dummy gate, and sidewall spacers are formed on the sidewalls of the notched dummy gate. The dummy gate is removed, and a notched gate is formed. The methods allow the height and depth of the notches to be independently controlled, and transistors having shorter channel lengths are formed.

Abstract: The present invention relates to the deposition of a layer above a transistor structure, causing crystalline stress within the transistor, and resulting in increased performance. The stress layer may be formed above a plurality of transistors formed on a substrate, or above a plurality of selected transistors.

Abstract: According to the present invention, there is provided a semiconductor device having: first and second fins formed on a semiconductor substrate to oppose each other, and made of a semiconductor layer; an active region which is formed on the semiconductor substrate so as to be connected to the first and second fins, and supplies a predetermined voltage to the first and second fins; and a gate electrode formed on an insulating film formed on the semiconductor substrate, in a position separated from the active region by a predetermined spacing, so as to cross the first and second fins, wherein in the active region, a predetermined portion between a first portion connected to the first fin and a second portion connected to the second fin is removed.

Abstract: The method for fabricating a semiconductor device comprises the steps of: forming a dummy electrode 22n and a dummy electrode 22p; forming a metal film 32 on the dummy electrode 22p; conducting a thermal treatment at a first temperature to substitute the dummy electrode 22n with an electrode 34a of a material containing the constituent material of the metal film 32; forming a metal film 36 on the dummy electrode 22n; and conducting a thermal treatment at a second temperature, which is lower than the first temperature and at which an interdiffusion of constituent materials between the electrode 34a and the metal film 36 does not take place, to substitute the second dummy electrode with an electrode 34b of a material containing the constituent material of the metal film 36.

Abstract: A high-voltage device structure disposed in a substrate of a first conductivity type includes a first well and a second well each of a second conductivity type, a source diffusion region and a drain diffusion region each of a first length located in the first well and the second well respectively, and a gate of a second length on the substrate surface. Since the gate of the second length is longer than the source diffusion region and the drain diffusion region of the first length, the two sides of the gate have two spare regions. Two windows are located in the spare regions.

Abstract: A surface region of a first base layer is formed with a second base layer. Trenches are formed over a range from the surface of the second base layer to the first base layer. The second base layer is divided into base layers. Each of first trenches is formed with a trench gate electrode. An emitter layer is formed in a surface region of the base layer intermittently selected from base layers positioned between first trenches, and contacts with the trench. Dummy trenches are formed over a range from the surface of the base region where the emitter layer is not formed to the first base layer at a position near to each of trenches. A diffusion region is formed in the first base layer to contact with the side portion of dummy trenches formed at the bottom of each trench and a position near thereto.

Abstract: In a semiconductor device including active areas where transistors are formed and a field area for isolating the active areas from each other, the field area has a plurality of dummy areas where dummy gates are formed.