Abstract: A transistor having an improved sidewall gate structure and method of construction is provided. The improved sidewall gate structure may include a semiconductor substrate (12) having a channel region (20). A gate insulation (36) may be adjacent the channel region (20) of the semiconductor substrate (12). A gate (38) may be formed adjacent the gate insulation (36). A sidewall insulation body (28) may be formed adjacent a portion of the gate (38). The sidewall insulation body (28) is comprised of a silicon oxynitride material. An epitaxial layer (30) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the semiconductor substrate (12) substantially outward of the channel region (20). A buffer layer (32) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the epitaxial layer (30).

Abstract: Multiple implants are performed in an integrated circuit substrate by implanting ions into a face thereof. Then, a gate insulating layer and a gate electrode are formed on the face of the integrated circuit substrate after performing the multiple implants in the integrated circuit substrate. Preferably, ions are not implanted into the integrated circuit substrate through the face after forming the gate insulating layer and the gate electrode on the face of the integrated circuit substrate. By preferably performing all implants prior to forming a gate insulating layer, the gate insulating layer is not degraded by implanting ions into the face of the integrated circuit substrate through the gate insulating layer.

Abstract: Gate to drain capacitance in a lateral DMOS and vertical DMOS field effect transistor is minimized by providing a conductive shield plate under the gate and between the gate and the drain of the transistor. In operation, the shield plate is preferably connected to a DC voltage potential and coupled to AC ground for RF power applications. The shield plate is readily fabricated in a conventional polysilicon gate process by adding one additional polysilicon deposition (or other suitable material), one additional mask, and one additional etch step. The shield plate can include a raised portion which provides lateral capacitive isolation between the gate and the drain. Alternatively, a shield contact can be provided above the shield plate and between the gate and drain to provide lateral isolation.

Abstract: A method is provided for fabricating a semiconductor device, the method including forming a first dielectric layer above a structure and forming an island of a sacrificial layer above the first dielectric layer. The method also includes introducing a first dopant into first portions of the structure, leaving a second portion of the structure protected by the island, and removing first portions of the island leaving a second portion of the island. The method further includes introducing a second dopant into the first portions and third portions of the structure, leaving a fourth portion of the structure protected by the second portion of the island. The method additionally includes forming a second dielectric layer adjacent the second portion of the island, removing the second portion of the island, forming a gate dielectric above the fourth portion of the structure and forming a gate conductor above the gate dielectric.

Abstract: A semiconductor processing method of forming a plurality of conductive lines includes, a) providing a substrate; b) providing a first conductive material layer over the substrate; c) providing a first insulating material layer over the first conductive layer; d) etching through the first insulating layer and the first conductive layer to the substrate to both form a plurality of first conductive lines from the first conductive layer and provide a plurality of grooves between the first lines, the first lines being capped by first insulating layer material, the first lines having respective sidewalls; e) electrically insulating the first line sidewalls; and f) after insulating the sidewalls, providing the grooves with a second conductive material to form a plurality of second lines within the grooves which alternate with the first lines. Integrated circuitry formed according to the method, and other methods, is also disclosed.

Abstract: A method for fabricating a MOSFET device is provided. The method includes a step of fining a gate oxide including first and second gate oxide materials. The first gate oxide material has a higher dielectric constant than the second gate oxide material. The first gate oxide material is formed to be over source/drain extension regions of the device; and the second gate oxide material is formed over a channel region of the device. The first gate oxide material has a low dielectric constant and provides for mitigating gate fringing field effects. The second gate oxide material has a high dielectric constant and provides for forming a thick gate oxide over a channel region of the device. Controlled uniform growth of the second gate oxide material is facilitated because of the thickness thereof.

Abstract: A method and structure are provided for an IGFET which has a replaceable gate electrode fabrication and dual polished fabrication technique to simultaneously form source, drain and gate regions. The IGFET provides a raised metal layer between the source/drain areas and subsequent metallization layers. The IGFET provides a second gate material formed from a refractory metal which creates a gate junction with low contact resistivity. The refractory metal gate and the metal layer are formed over the source and drain regions in the same process step. The metal layer and replaceable gate are scalable. Also, by first having a first gate material, which is subsequently removed, the fabrication process can continue to utilize self-aligned processing. An information handling system which incorporates the above method and structure is similarly provided.

Abstract: A method of fabricating a MOSFET transistor and resulting structure having a drain-gate feedback capacitance shield formed in a recess between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since one additional non-critical mask is required with selective etch used to create the recess.

Abstract: A process is disclosed for the fabrication of a MOS device with a T-shaped gate electrode, in which a selective CVD technique has been utilized to simplify the T-shaped gate process. After the formation of the gate oxide layer, no reactive ion etching step is applied, and that avoids the plasma charging damage to the gate oxide. The lightly-doped-drain structure and heavily-doped drain and source areas are formed in a self-aligned manner during the T-shaped gate process. The present invention provides a high yield rate and cost-saving in the T-shaped gate process for MOS devices.

Abstract: In order to suppress a reverse short-channel effect, a plurality of dummy gates, wherein gate electrodes are respectively to be formed, are formed in selective regions on the substrate. Further, the regions wherein first conductive type elements are to be formed are masked. Thereafter, a first conductive type well by ion planting a first conductive type impurity is formed. Further, a second conductive type source and drain region is formed by ion planting a second conductive type impurity. The resist covering the regions, wherein the first conductive type elements are to be formed, are removed. Following this, regions wherein second conductive type elements are to be formed, are masked by a resist. Further, a second conductive type well is formed by ion planting a second conductive type impurity. A first conductive type source and drain region is formed by ion planting a first conductive type impurity.

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dummy or sacrificial gate structure. Dopants are provided through the openings associated with sacrificial spacers to form the source and drain extensions. The openings can be filled with spacers The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).

Abstract: A method for fabricating a multi-level integrated circuit is disclosed which utilizes a grid pattern from which portions corresponding to the metal layer are selectively removed to form a mask which is subsequently used to deposit dummy features in the open areas between metal lines, thereby to allow the deposition of a substantially planar dielectric surface over the metal layers and dummy features.

Abstract: There are provided: an isolation protruding upward from a semiconductor substrate in an active region; a gate electrode formed in the active region; and a pair of dummy electrodes formed to extend over the active region and the isolation and substantially in parallel with the gate electrode. Each of the gate electrode and dummy electrodes is composed of a lower film and an upper film. The lower films of the dummy electrodes are formed flush with the isolation and in contact with the side edges of the isolation. With the dummy electrodes, any gate electrode can be formed in a line-and-space pattern, so that the finished sizes of the gate electrode become uniform. This enables a reduction in gate length and therefore provides a semiconductor device of higher integration which is operable at a higher speed and substantially free from variations in finished size resulting from the use of different gate patterns.

Abstract: A semiconductor device comprises a plurality of wiring formed on a lower insulating film to be spaced apart from each other, dummy patterns formed on the lower insulating layer between the plurality of wiring and spaced apart from each other, and an upper insulating layer formed to cover the plurality of wiring and the dummy patterns and having therein cavities formed in regions between the plurality of wiring and the dummy patterns.

Abstract: In order to reduce the thickness of an impurity diffusion region of a first conductivity type formed near the surface of a semiconductor substrate, a pocket region is formed under the impurity diffusion region. If the pocket region is large, a junction capacitance between the impurity diffusion region and the pocket region cannot be neglected. In order to reduce the size of the pocket region to the minimum permissible size, gates and dummy gates which are temporarily formed to suppress the non-uniformity of the gate dimensions by uniformly giving an influence of the optical proximity effect to a plurality of gates are used as a mask used for implanting an impurity into the surface portion of the semiconductor substrate to form the pocket regions. Thus, the pocket region can be formed in a limited area between the gate and the dummy gate.

Abstract: A MOS transistor including a gate electrode on a gate oxide over a channel region between a source region and a drain region also includes a shield electrode at least partially on the gate oxide adjacent to, self-aligned with, and at least partially coplanar with the gate electrode and between the gate electrode and drain region. Placing the shield electrode on the gate oxide improves the gate-drain shielding, reduces the gate-drain capacitance, Cgd, and reduces hot electron related reliability hazard.

Abstract: A method of forming a field effect transistor structure for making semiconductor integrated circuits is disclosed. The method utilizes a novel processing sequence where the high temperature processing steps are carried out prior to the formation of the gate dielectric and gate electrode. The process sequence proceeds as follows: A mask patterned in replication of a to-be-formed gate is deposited onto a substrate. Then, a high temperature step of forming doped regions is performed. Then, a high temperature step of forming a silicide is performed. Next, a planarization material is deposited over the mask and is planarized. The mask is removed selectively to the planarization material to form an opening within the planarization material. The gate dielectric and gate electrode are formed within the opening.

Abstract: A device having, at least, a first film having a surface on which neither a natural oxide film nor impurity grains caused by a resist residue is or are present, and a conductive material layer formed on a surface adjacent to the surface of the first film, wherein an insulative compound film is formed on a surface of the conductive material layer by a surface reaction with the conductive material layer, and a predetermined second film required for an arrangement is formed on the surface of the first film.

Abstract: A method for forming a self-aligned semiconductor device (10) having sidewall spacers (16,17) used to align the formation of a source region (23) and a drain region (24) along with the formation of a gate structure (35). Spacers (16,17) can be formed using a sacrificial structure process where a sacrificial structure (14) is formed which determines the location of a final gate structure (35). The deposition of a dielectric layer over the sacrificial structure (14) and subsequent etch will form spacers (16,17). A second method for forming spacers (18,19), uses a photolithographic process to pattern a dielectric layer without the use of a sacrificial structure process. The spacers (16,17) are used in conjunction with implant mask regions (22) to form the source and drain regions (23,24) which are aligned to the gate structure (35).