Multiple Doping Steps Patents (Class 438/185)
  • Patent number: 6020244
    Abstract: An improved well boosting implant which provides better characteristics than traditional halo implants particularly for short channel devices (e.g., 0.25 microns or less). In effect, an implant is distributed across the entire channel with higher concentrations occurring in the center of the channel of the devices having gate lengths less than the critical dimension. This is done by using very large tilt angles (e.g., 30-50.degree.) with a relatively light dopant species and by using a relatively high energy when compared to the traditional halo implants.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: February 1, 2000
    Assignee: Intel Corporation
    Inventors: Scott E. Thompson, Paul A. Packan, Tahir Ghani, Mark Stettler, Shahriar S. Ahmed, Mark T. Bohr
  • Patent number: 5953613
    Abstract: The ultimate shallow source drain junction depth for a transistor is achieved by removing or detaching a source from the semiconductor substrate and forming an electron source on the surface of the semiconductor substrate adjacent to the transistor gate. The removal or detachment of an electron source from the semiconductor substrate eliminates the heavily-doped source drain diffusion or implant into a source region of the substrate, thereby avoiding non-uniform doping profiles that degrade long-channel subthreshold characteristics of a device as well as the punchthrough behavior of short-channel devices. A metal plug is used as an electron source which is removed or detached from the from the semiconductor substrate. The metal plug is vastly superior to doped semiconductor materials as an electron source. A method of fabricating an integrated circuit includes forming a lightly-doped drain (LDD) MOSFET structure prior to source/drain doping.
    Type: Grant
    Filed: March 4, 1997
    Date of Patent: September 14, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, Frederick N. Hause
  • Patent number: 5900662
    Abstract: A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value. Under each body region a respective lightly doped region of the second conductivity type is provided having a second resistivity value higher than the first resistivity value.
    Type: Grant
    Filed: November 4, 1996
    Date of Patent: May 4, 1999
    Assignees: SGS Thomson Microelectronics S.r.l., Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Ferruccio Frisina, Giuseppe Ferla, Salvatore Rinaudo
  • Patent number: 5837568
    Abstract: To provide a manufacturing method of thin film transistors (TFT) using poly-silicone and having an LDD structure. In particular, the LDD sections of the TFTs are formed in an improved method so as to achieve a high throughput and stable performance of the TFTs. To be specific, the LD region is doped at a low concentration in the ion implantation method which includes mass spectrometry because high controllability over a dose is required. On the other hand, the source and drain regions are doped at a higher concentration than the LD region in the ion showering method which does not include mass spectrometry. Using the ion showering method, poly-crystal silicon can be doped such that less doping damage is caused thereto. This makes it possible to apply a lower temperature for annealing, such as RTA, to activate doped impurities so as to prevent the substrate from being curved.
    Type: Grant
    Filed: December 10, 1996
    Date of Patent: November 17, 1998
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kiyoshi Yoneda, Yoshihiro Morimoto, Kiichi Hirano, Koji Suzuki, Masaru Takeuchi