Including Isolation Structure Patents (Class 438/196)
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Patent number: 7939394Abstract: Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.Type: GrantFiled: March 28, 2008Date of Patent: May 10, 2011Assignee: Micron Technology, Inc.Inventors: Shubneesh Batra, Howard C. Kirsch, Gurtej S. Sandhu, Xianfeng Zhou, Chih-Chen Cho
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Patent number: 7915107Abstract: This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.Type: GrantFiled: June 26, 2009Date of Patent: March 29, 2011Assignee: SuVolta, Inc.Inventor: Ashok K. Kapoor
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Patent number: 7910453Abstract: The present disclosure provides a method of manufacturing a microelectronic device. The method includes forming recessed shallow trench isolation (STI) features in a semiconductor substrate, defining a semiconductor region between adjacent two of the recessed STI features; forming a tunnel dielectric feature within the semiconductor region; forming a nitride layer on the recessed STI features and the tunnel dielectric feature; etching the nitride layer to form nitride openings within the recessed STI features; partially removing the recessed STI features through the nitride openings, resulting in gaps between the nitride layer and the recessed STI features; and forming a first dielectric material on surfaces of the nitride layer, sealing the nitride openings.Type: GrantFiled: July 14, 2008Date of Patent: March 22, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeff J. Xu, Chia-Ta Hsieh, Chun-Pei Wu, Chun-Hung Lee
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Patent number: 7910482Abstract: A method for processing a substrate comprising at least a buried oxide (BOX) layer and a semiconductor material layer is provided. The method includes etching the semiconductor material layer to form a vertical semiconductor material structure overlying the BOX layer, leaving an exposed portion of the BOX layer. The method further includes exposing a top surface of the exposed portion of the BOX layer to an oxide etch resistant species to form a thin oxide etch resistant layer overlying the exposed portion of the BOX layer.Type: GrantFiled: May 30, 2008Date of Patent: March 22, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Tab A. Stephens, Leo Mathew, Lakshmanna Vishnubholta, Bruce E. White
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Publication number: 20110037104Abstract: Methods include, for example, forming a vertically disposed active region on a substrate; forming a first gate over a portion of the vertically disposed active region; forming a dielectric over the portion; exposing an upper surface of the first gate; forming a second gate over the upper surface; and forming a spacer pocket region between the vertically disposed active region, the first gate and the dielectric, wherein the spacer pocket region is self-aligned to a lower surface of the second gate and has a substantially uniform thickness from an upper to a lower extent thereof.Type: ApplicationFiled: August 13, 2009Publication date: February 17, 2011Applicant: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Novak
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Patent number: 7858454Abstract: A method is provided for forming a self-aligned carbon nanotube (CNT) field effect transistor (FET). According to one feature, a self-aligned source-gate-drain (S-G-D) structure is formed that allows for the shrinking of the gate length to arbitrarily small values, thereby enabling ultra-high performance CNT FETs. In accordance with another feature, an improved design of the gate to possess a âTâ-shape, referred to as the âT-Gate,â thereby enabling a reduction in gate resistance and further providing an increased power gain. The self-aligned T-gate CNT FET is formed using simple fabrication steps to ensure a low cost, high yield process.Type: GrantFiled: July 29, 2008Date of Patent: December 28, 2010Assignee: RF Nano CorporationInventor: Amol M. Kalburge
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Patent number: 7858467Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including sidewall parts and a bottom part, or a stepped structure including a first planar part, a second planar part, and a step part located at a boundary between the first planar part and the second planar part, and supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure by applying a predetermined voltage to the semiconductor substrate, to perform anisotropic oxidation or anisotropic nitridation of the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure.Type: GrantFiled: March 27, 2009Date of Patent: December 28, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Isao Kamioka, Junichi Shiozawa, Ryu Kato, Yoshio Ozawa
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Patent number: 7855407Abstract: Embodiments relate to a Complementary Metal Oxide Semiconductor (CMOS) image sensor, and to a method for manufacturing the same, that improves the low-light level characteristics of the CMOS image sensor. The CMOS image sensor has a photosensor unit and a signal processing unit, and may include a semiconductor substrate having a device isolating implant area provided with a first ion implant area and a complementary second ion implant area within the first ion implant area; a device isolating layer in the signal processing unit; a photodiode in the photosensor unit; and transistors in the signal processing unit. A crystal defect zone neighboring the photodiode may be minimized using the device isolating implant area between adjacent photodiodes so that a source of dark current can be reduced and the occurrence of interface traps can be prevented, making it possible to improve the low-light level characteristics of the image sensor.Type: GrantFiled: December 13, 2007Date of Patent: December 21, 2010Assignee: Dongbu HiTek Co., Ltd.Inventor: Hee Sung Shim
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Patent number: 7855109Abstract: A method for manufacturing a semiconductor device according to the present invention, comprising the steps of: forming a screen oxide layer over the surface of an active region of a semiconductor substrate in which an isolation structure defining the active region is formed; forming a first recess pattern in the active region and a second recess pattern in the isolation structure by etching a gate forming area in the active region and the isolation structure part extended thereto; removing the screen oxide film and simultaneously expanding the width of the second recess pattern; forming a first insulation dielectric layer over the resultant of the substrate having the second recess pattern with the expanded width so that the first insulation dielectric layer is blocked at the upper end thereof in the first recess pattern and it is deposited along the profile in the second recess pattern; forming a second insulation dielectric layer over the first insulation dielectric layer so that the second recess patter isType: GrantFiled: December 30, 2008Date of Patent: December 21, 2010Assignee: Hynix Semiconductor Inc.Inventors: Hyung Hwan Kim, Kwang Kee Chae, Jong Goo Jung, Ok Min Moon, Young Bang Lee, Sung Eun Park
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Patent number: 7790535Abstract: A semiconductor device and a method of manufacturing are provided. A dielectric layer is formed over a substrate, and a first silicon-containing layer, undoped, is formed over the dielectric layer. Atomic-layer doping is used to dope the undoped silicon-containing layer. A second silicon-containing layer is formed over first silicon-containing layer. The process may be expanded to include forming a PMOS and NMOS device on the same wafer. For example, the first silicon-containing layer may be thinned in the PMOS region prior to the atomic-layer doping. In the NMOS region, the doped portion of the first silicon-containing layer is removed such that the remaining portion of the first silicon-containing layer in the NMOS is undoped. Thereafter, another atomic-layer doping process may be used to dope the first silicon-containing layer in the NMOS region to a different conductivity type. A third silicon-containing layer may be formed doped to the respective conductivity type.Type: GrantFiled: September 16, 2008Date of Patent: September 7, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jing-Cheng Lin, Chen-Hua Yu
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Patent number: 7781267Abstract: A semiconductor device and associated method for forming. The semiconductor device comprises an electrically conductive nanotube formed over a first electrically conductive member such that a first gap exists between a bottom side the electrically conductive nanotube and a top side of the first electrically conductive member. A second insulating layer is formed over the electrically conductive nanotube. A second gap exists between a top side of the electrically conductive nanotube and a first portion of the second insulating layer. A first via opening and a second via opening each extend through the second insulating layer and into the second gap.Type: GrantFiled: May 19, 2006Date of Patent: August 24, 2010Assignee: International Business Machines CorporationInventors: Jeffrey Peter Gambino, Son Van Nguyen
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Publication number: 20100207173Abstract: A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch.Type: ApplicationFiled: February 19, 2009Publication date: August 19, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Frederick G. Anderson, David S. Collins, Richard A. Phelps, Robert M. Rassel, Michael J. Zierak
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Publication number: 20100207174Abstract: The invention provides a method for forming a semiconductor structure. A plurality of first type well regions is formed in the first type substrate. A plurality of second type well regions and a plurality of second type bar doped regions are formed in the first type substrate by a doping process using a mask. The second type bar doped regions are diffused to form a second type continuous region by annealing. The second type continuous region is adjoined with the first type well regions. A second type dopant concentration of the second type continuous region is smaller than a second type dopant concentration of the second type bar doped regions. A second type source/drain region is formed in the second type well region.Type: ApplicationFiled: February 16, 2009Publication date: August 19, 2010Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Hung-Shern Tsai, Shang-Hui Tu, Shin-Cheng Lin
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Patent number: 7763523Abstract: A method for forming a device isolation structure of a semiconductor device using at least three annealing steps to anneal a flowable insulation layer is presented. The method includes the steps of forming a hard mask pattern on a semiconductor substrate having active regions exposing a device isolation region of the semiconductor substrate; etching the device isolation region of the semiconductor substrate exposed through the hard mask pattern, and therein forming a trench; forming a flowable insulation layer to fill a trench; first annealing the flowable insulation layer at least three times; second annealing the first annealed flowable insulation layer; removing the second annealed flowable insulation layer until the hard mask pattern is exposed; and removing the exposed hard mask pattern.Type: GrantFiled: March 10, 2008Date of Patent: July 27, 2010Assignee: Hynix Semiconductor Inc.Inventors: Sang Tae Ahn, Ja Chun Ku, Eun Jeong Kim
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Patent number: 7755140Abstract: A SOI device features a conductive pathway between active SOI devices and a bulk SOI substrate. The conductive pathway provides the ability to sink plasma-induced process charges into a bulk substrate in the event of process charging, such as interlayer dielectric deposition in a plasma environment, plasma etch deposition, or other fabrication provides. A method is also disclosed which includes dissipating electrostatic and process charges from a top of a SOI device to the bottom of the device. The top and bottom of the SOI device may characterize a region of active devices and a semiconductor method respectively. The method further includes a single masking step to create seed regions for an epitaxial-silicon pathway.Type: GrantFiled: November 3, 2006Date of Patent: July 13, 2010Assignee: Intel CorporationInventors: Sangwoo Pae, Jose Maiz
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Patent number: 7745274Abstract: The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.Type: GrantFiled: March 8, 2007Date of Patent: June 29, 2010Assignee: Texas Instruments IncorporatedInventors: Xiaoju Wu, Fan-Chi Frank Hou, Pinghai Hao
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Patent number: 7732279Abstract: Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation layer being parallel to the bit line without overlapping the bit line; and forming a gate line including a gate pattern and a conductive line by forming the gate pattern in the active region and forming a conductive line that extends at a right angle to the bit line across the active region and is electrically connected to the gate pattern disposed thereunder. The gate pattern and the conductive line can be integrally formed.Type: GrantFiled: July 25, 2008Date of Patent: June 8, 2010Assignee: Samsung Electronics, Co., LtdInventor: Joon-Soo Park
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Patent number: 7713804Abstract: A JFET structure with self-aligned metal source, drain and gate contacts with very low resistivity and very small feature sizes. Small source, drain and gate openings are etched in a thin dielectric layer which has a thickness set according to the desired source, gate and drain opening sizes, said dielectric layer having a nitride top layer. Metal is deposited on top of said dielectric layer to fill said openings and the metal is polished back to the top of the dielectric layer to achieve thin source, drain and gate contacts. Some embodiments include an anti-leakage poly-silicon layer lining the contact holes and all embodiments where spiking may occur include a barrier metal layer.Type: GrantFiled: November 24, 2008Date of Patent: May 11, 2010Assignee: SuVolta, Inc.Inventors: Madhukar B. Vora, Ashok K. Kapoor
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Patent number: 7670888Abstract: Fashioning a low noise (1/f) junction field effect transistor (JFET) is disclosed, where multiple implants are performed to push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.Type: GrantFiled: April 11, 2007Date of Patent: March 2, 2010Assignee: Texas Instruments IncorporatedInventors: Pinghai Hao, Imran Khan, Joe Trogolo
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Patent number: 7670890Abstract: An junction field effect transistor (JFET) is fashioned with a patterned layer of silicide block (SBLK) material utilized in forming gate, source and drain regions. Utilizing the silicide block in this manner helps to reduce low-frequency (flicker) noise associated with the JFET by suppressing the impact of surface states, among other things.Type: GrantFiled: July 26, 2006Date of Patent: March 2, 2010Assignees: Texas Instruments Deutschland GmbH, Texas Instruments IncorporatedInventors: Badih El-Kareh, Hiroshi Yasuda, Scott Gerard Balster, Philipp Steinmann, Joe R. Trogolo
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Patent number: 7659180Abstract: In one embodiment, a method of fabricating one or more transistors in an integrated circuit includes an annealing step prior to a gate oxidation step. The annealing step may comprise a rapid thermal annealing (RTA) step performed prior to a gate oxidation pre-clean step. Among other advantages, the annealing step reduces a step height difference between P-doped and N-doped regions of a field oxide of a shallow trench isolation structure. The shallow trench isolation structure may be separating a PMOS transistor and an NMOS transistor in the integrated circuit.Type: GrantFiled: August 26, 2004Date of Patent: February 9, 2010Assignee: Cypress Semiconductor CorporationInventors: Antoine Khoueir, Maroun Khoury, Andrey Zagrebelny
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Patent number: 7629223Abstract: A method for manufacturing a semiconductor device includes forming a plurality of trenches for element isolation and a plurality of trenches for alignment mark on a substrate. The substrate has an active region. The method also includes laminating an oxide film on the substrate and over both of the trenches. The method also includes etching the oxide film using a resist mask that masks the element isolation trenches, so that the oxide film laminated in the active region and the oxide film laminated in the alignment mark trenches are removed. The method also includes polishing a surface of the substrate to planarize or smooth the surface of the substrate. Accordingly, those portions of the oxide film which project from the substrate surface are eliminated and the oxide film remains only inside the element isolation trenches. This divides the active region into a plurality of individual active regions for the respective semiconductor elements.Type: GrantFiled: November 20, 2008Date of Patent: December 8, 2009Assignee: Oki Semiconductor Co., Ltd.Inventors: Tadashi Narita, Katsuo Oshima
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Publication number: 20090206336Abstract: A method for fabricating a semiconductor device comprises depositing a first layer of oxide on at least a portion of a channel of a transistor. The method further comprises depositing a layer of nitride on the first layer of oxide and etching at least a portion of the layer of nitride to the first layer of oxide. The method further comprises depositing a second layer of oxide and planarizing the oxide to expose at least a portion of the layer of nitride. The method further comprises stripping at least a portion of the layer of nitride to create one or more notches and removing at least a portion of the first layer of oxide. The method further comprises depositing a layer of polysilicon, wherein at least a portion of the layer of polysilicon is deposited into at least one of the one or more notches.Type: ApplicationFiled: February 19, 2008Publication date: August 20, 2009Inventor: Srinivasa R. Banna
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Patent number: 7514313Abstract: A process of forming an electronic device can include forming an insulating layer over first and second active regions, and a field isolation region. The process can also include forming a seed layer and exposing the first active region. The process can further include selectively forming a first and second semiconductor layer over the first active region and the seed layer, respectively. The first and second semiconductor layers can be spaced-apart from each other. In one aspect, the process can include selectively forming the first and second semiconductor layers simultaneously at a substantially same point in time. In another aspect, an electronic device can include first and second transistor structures separated by a field isolation region and electrically connected by a conductive member. A semiconductor island, designed to be electrically floating, can lie between the conductive member and the base layer.Type: GrantFiled: April 10, 2006Date of Patent: April 7, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Omar Zia, Da Zhang, Venkat R. Kolagunta, Narayanan C. Ramani, Bich-Yen Nguyen
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Publication number: 20090039398Abstract: An n type impurity region is continuously formed on the bottom portion of a channel region below a source region, a gate region and a drain region. The n type impurity region has an impurity concentration higher than the channel region and a back gate region, and is less influenced by the diffusion of p type impurities from the gate region and the back gate region. Moreover, by continuously forming the impurity region from a portion below the source region to a portion below the drain region, the resistance value of a current path in the impurity region is substantially uniformed. Therefore, the IDSS is stabilized, the forward transfer admittance gm and the voltage gain Gv are improved, and the noise voltage Vno is decreased. Furthermore, the IDSS variation within a single wafer is suppressed.Type: ApplicationFiled: August 5, 2008Publication date: February 12, 2009Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.Inventors: Mitsuo Hatamoto, Yoshiaki Matsumiya
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Publication number: 20080315266Abstract: A junction field effect transistor (JFET) has a hyperabrupt junction layer that functions as a channel of a JFET. The hyperabrupt junction layer is formed by two dopant profiles of opposite types such that one dopant concentration profile has a peak concentration depth at a tail end of the other dopant profile. The voltage bias to the channel is provided by a body that is doped with the same type of dopants as the gate. This is in contrast with conventional JFETs that have a body that is doped with the opposite conductivity type as the gate. The body may be electrically decoupled from the substrate by another reverse bias junction formed either between the body and the substrate or between a buried conductor layer beneath the body and the substrate. The capability to form a thin hyperabrupt junction layer allows formation of a JFET in a semiconductor-on-insulator substrate.Type: ApplicationFiled: June 25, 2007Publication date: December 25, 2008Inventors: Ebenezer E. Eshun, Jeffrey B. Johnson, Richard A. Phelps, Robert M. Rassel, Michael J. Zierak
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Patent number: 7459357Abstract: The present invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage, frequency or current characteristics. The cross-lateral transistor is formed on a commercial semiconductor substrate (102). A channel structure (124) is formed along the substrate, having source (120) and drain (122) structures laterally formed on opposites sides thereof. A first gate structure (116) is formed along the substrate, laterally adjoining the channel structure orthogonal to the source and drain structures. A second gate structure (118) is formed along the substrate, laterally adjoining the channel structure, orthogonal to the source and drain structures and opposite the first gate stricture.Type: GrantFiled: August 16, 2007Date of Patent: December 2, 2008Assignee: Texas Instruments IncorporatedInventors: Gregory E Howard, Leland Swanson
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Publication number: 20080272394Abstract: Junction field effect transistors (JFET) formed in substrates containing germanium. JFETs having polycrystalline semiconductor surface contacts with self-aligned silicide formed thereon and self-aligned source, drain and gate regions formed by thermal drive-in of impurities from surface contacts into the substrate, and implanted link regions. Others have a polycrystalline semiconductor gate surface contact and metal back gate, source and drain contacts and a metal surface contact to the gate surface contact with implanted source and drains and a self-aligned gate region. JFETs having a polycrystalline semiconductor gate surface contact and metal back gate, source and drain contacts and a metal surface contact to the gate surface contact with implanted source and drains and a self-aligned gate region and silicide formed on the top of the source, drain and back gate contacts and on top of the gate polycrystalline semiconductor gate contact to which the metal surface contacts make electrical contact.Type: ApplicationFiled: October 10, 2007Publication date: November 6, 2008Inventors: Ashok Kumar Kapoor, Madhukar B. Vora, Weimin Zhang, Sachin R. Sonkusale, Yujie Liu
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Publication number: 20080251818Abstract: Fashioning a low noise (1/f) junction field effect transistor (JFET) is disclosed, where multiple implants are performed to push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.Type: ApplicationFiled: April 11, 2007Publication date: October 16, 2008Inventors: Pinghai Hao, Imran Khan, Joe Trogolo
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Patent number: 7422937Abstract: A semiconductor device manufacturing method including forming at least a first conductive film and a first insulting film above a semiconductor substrate, forming a plurality of first resist patterns above the first insulating film periodically at first intervals, patterning at least the first insulting film by use of the first resist patterns to form a plurality of mask patterns, each of the mask patterns including the first insulating film, selectively forming a second resist pattern in a space between the mask patterns in such a manner that the second resist pattern is formed in the space corresponding to a region where a second wiring structure wider than the first wiring structure is to be formed, and patterning the first conductive film by use of the second resist pattern and the mask patterns.Type: GrantFiled: June 15, 2007Date of Patent: September 9, 2008Assignee: Kabushiki Kaisha ToshibaInventor: Tadashi Miwa
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Patent number: 7420202Abstract: An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.Type: GrantFiled: November 8, 2005Date of Patent: September 2, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Vance H. Adams, Paul A. Grudowski, Venkat R. Kolagunta, Brian A. Winstead
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Patent number: 7402496Abstract: A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a first spacer structure and a second spacer structure respectively disposed on sidewalls of the first gate structure and the second gate structure; a first LDD and a second LDD respectively disposed in the substrate at both sides of the first gate structure and the second gate structure; an epitaxial material layer, disposed in the first active region and located on a side of the first LDD; and a passivation layer, disposed on the first gate structure, the first spacer structure, and the first LDD and covering the second active region, wherein the passivation layer comprises a carbon-containing oxynitride layer.Type: GrantFiled: September 11, 2006Date of Patent: July 22, 2008Assignee: United Microelectronics Corp.Inventors: Che-Hung Liu, Po-Lun Cheng, Chun-An Lin, Li-Yuen Tang, Hung-Lin Shih, Ming-Chi Fan, Hsien-Liang Meng, Jih-Shun Chiang
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Patent number: 7399679Abstract: A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.Type: GrantFiled: November 29, 2005Date of Patent: July 15, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Ming Sheu, Da-Wen Lin, Cheng-Ku Chen, Po-Ying Yeh, Shi-Shung Peng, Chung-Cheng Wu
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Publication number: 20080128673Abstract: A transistor for a phase change memory device includes a semiconductor substrate in which active regions are delimited by an isolation structure. A groove is defined on a surface of a gate forming area of each active region. Portions of the isolation structure, which are adjacent to the gate forming area of the active region, are recessed to expose side faces of the gate forming area of the active region. A gate is formed on the gate forming area of the active region over the gate forming area grooves and exposed side faces thereof as well as the recessed portions of the isolation structure. Junction areas are then formed in the active region on both sides of the gate to complete the transistor of a phase change memory device.Type: ApplicationFiled: September 14, 2007Publication date: June 5, 2008Inventors: Heon Yong CHANG, Suk Kyoung HONG, Hae Chan PARK, Nam Kyun PARK
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Patent number: 7361537Abstract: A method of fabricating a recess channel array transistor is disclosed. An impurity region is formed in a semiconductor substrate. Then, a polysilicon layer is formed on the semiconductor substrate, both of which are then etched to form a trench that defines an active region. By filling the trench with an insulating material, a STI and an interlayer insulating layer are formed. A patterned mask layer is formed to be used for etching the polysilicon layer and the interlayer insulating layer, thereby forming an opening that defines a contact pad. A Spacer is formed along a sidewall of the contact pad. Using the mask layer and the spacer, the semiconductor substrate is etched to thereby form a recess channel trench. Thereafter, a gate insulating layer and a gate conductive layer are formed. A nitride layer is formed on the resultant structure, and chemical mechanical polishing is performed to isolate the nodes.Type: GrantFiled: October 19, 2004Date of Patent: April 22, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Je-Min Park
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Patent number: 7354812Abstract: Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.Type: GrantFiled: September 1, 2004Date of Patent: April 8, 2008Assignee: Micron Technology, Inc.Inventors: Shubneesh Batra, Howard C. Kirsch, Gurtej S. Sandhu, Xianfeng Zhou, Chih-Chen Cho
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Patent number: 7326608Abstract: In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon nitride pattern are sequentially formed on the substrate and on a sidewall of a lower portion of the active pattern. A device isolation layer is formed on the second silicon nitride pattern, and a top surface of the device isolation layer is coplanar with top surfaces of the oxide pattern and the second silicon nitride pattern. A buffer pattern having an etching selectivity with respect to the second silicon nitride pattern is formed between the first oxide pattern and the second silicon nitride pattern.Type: GrantFiled: November 30, 2005Date of Patent: February 5, 2008Assignee: Samsung Electronic Co., Ltd.Inventors: Deok-Hyung Lee, Yu-Gyun Shin, Jong-Wook Lee, Min-Gu Kang
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Patent number: 7306959Abstract: This disclosure concerns methods for fabrication of integrated high speed optoelectronic devices. In one example of such a method, a device region that includes a top surface and a bottom surface is formed on a top surface of a substrate. The device region may take the form of an optical emitter, such as a VCSEL, or a detector, such as a photodiode. Next, an isolation region is formed that is configured such that the device region is surrounded by the isolation region. A superstrate is then disposed on the top surface of the device region. Finally, a micro-optical device, such as a lens, is placed on a top surface of the superstrate.Type: GrantFiled: December 22, 2004Date of Patent: December 11, 2007Assignee: Finisar CorporationInventor: Yue Liu
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Patent number: 7265008Abstract: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a âcorrugated substrateâ), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and âwrappedâ gates can be used in conjunction with the segmented channel regions to further enhance device performance.Type: GrantFiled: July 1, 2005Date of Patent: September 4, 2007Assignee: Synopsys, Inc.Inventors: Tsu-Jae King, Victor Moroz
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Patent number: 7250346Abstract: In the method of manufacturing a dual gate oxide layer of a semiconductor device, which has first and second active regions operating at mutually different voltages on a semiconductor substrate, the first and second active regions having a device isolation layer of STI (Shallow Trench Isolation) structure; the method of manufacturing the dual gate insulation layer includes, forming the device isolation layer so that an uppermost part thereof is positioned lower than an upper surface of the first and second active regions, before forming a gate insulation layer corresponding to each of the first and second active regions. Whereby, it is be effective till a portion of trench sidewall utilized as the active region, to increase a cell current of the active region and to prevent a stringer caused by a stepped coverage between the active region and a field region and a dent caused on a boundary face between the active region and the field region.Type: GrantFiled: June 23, 2004Date of Patent: July 31, 2007Assignee: Samsung Electronics Col., Ltd.Inventors: Jong-Sik Chun, Hyun-Ho Jo, Byung-Hong Chung
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Patent number: 7247534Abstract: A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.Type: GrantFiled: November 19, 2003Date of Patent: July 24, 2007Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, Omer H. Dokumaci, Oleg G. Gluschenkov
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Patent number: 7244642Abstract: The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a spacer material (415) located over gate electrodes (250) and a doped region (255) located between the gate electrodes (250), removing a portion of the spacer material (415) and the protective layer (510) located over the gate electrodes (250). A remaining portion of the spacer material (415) remains over the top surface of the gate electrodes (250) and over the doped region (255), and a portion of the protective layer (510) remains over the doped region (255). The method further comprises removing the remaining portion of the spacer material (415) to form spacer sidewalls on the gate electrodes (250), expose the top surface of the gate electrodes (250), and leave a remnant of the spacer material (415) over the doped region (255).Type: GrantFiled: September 16, 2005Date of Patent: July 17, 2007Assignee: Texas Instruments IncorporatedInventors: Steven A. Vitale, Hyesook Hong, Freidoon Mehrad
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Patent number: 7241651Abstract: A plurality of first wiring structures of a first width are arranged periodically at first intervals. A second wiring structure is formed next to one of the first wiring structures. The lower part of the second wiring structure has a second width substantially equal to the sum of n times the first width of the first wiring structure (n is a positive integer equal to two or more) and (n?1) times the first interval.Type: GrantFiled: November 9, 2004Date of Patent: July 10, 2007Assignee: Kabushiki Kaisha ToshibaInventor: Tadashi Miwa
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Patent number: 7172914Abstract: A method of forming a semiconductor structure includes forming an isolation region in a semiconductor substrate. A first oxide layer is on the substrate, a first sacrificial layer is on the first oxide layer, and a first nitride layer is on the first sacrificial layer. The first oxide layer may be a screen oxide layer, and the method provides consistency in the thickness of the screen oxide layer.Type: GrantFiled: January 2, 2001Date of Patent: February 6, 2007Assignee: Cypress Semiconductor CorporationInventor: Sundar Narayanan
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Patent number: 6962839Abstract: The present invention generally relates to an apparatus and method of carbon nanotube (CNT) gate field effect transistor (FET), which is used to replace the current metal gate of transistor for decreasing the gate width greatly. The carbon nanotube has its own intrinsic characters of metal and semiconductor, so it can be the channel, connector or next-level gate of transistor. Furthermore, the transistor has the structure of exchangeable source and drain, and can be defined the specificity by outside wiring.Type: GrantFiled: July 29, 2004Date of Patent: November 8, 2005Assignee: Industrial Technology Research InstituteInventors: Jeng-Hua Wei, Hsin-Hui Chen, Ming-Jiunn Lai, Hung-Hsiang Wang, Ming-Jer Kao
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Patent number: 6955957Abstract: Disclosed is a method of forming the floating gate in the flash memory device. After the first polysilicon film is deposited on the semiconductor substrate, the trench is formed on the first polysilicon film with the pad nitride film not deposited. The HDP oxide film is then deposited to bury the trench. Next, the HDP oxide film is etched to define a portion where the second polysilicon film will be deposited in advance. The second polysilicon film is then deposited on the entire top surface, thus forming the floating gate. Thus, it is possible to completely remove a moat and an affect on EFH (effective field oxide height), solve a wafer stress by simplified process and a nitride film, and effectively improve the coupling ratio of the flash memory device.Type: GrantFiled: July 10, 2003Date of Patent: October 18, 2005Assignee: Hynix Semiconductor Inc.Inventor: Hyeon Sang Shin
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Patent number: 6861303Abstract: Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.Type: GrantFiled: May 9, 2003Date of Patent: March 1, 2005Assignee: Texas Instruments IncorporatedInventors: Pinghai Hao, Fan-Chi Hou, Imran Khan
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Patent number: 6852582Abstract: The present invention generally relates to an apparatus and method of carbon nanotube (CNT) gate field effect transistor (FET), which is used to replace the current metal gate of transistor for decreasing the gate width greatly. The carbon nanotube has its own intrinsic characters of metal and semiconductor, so it can be the channel, connector or next-level gate of transistor. Furthermore, the transistor has the structure of exchangeable source and drain, and can be defined the specificity by outside wiring.Type: GrantFiled: June 3, 2003Date of Patent: February 8, 2005Assignee: Industrial Technology Research InstituteInventors: Jeng-Hua Wei, Hsin-Hui Chen, Ming-Jiunn Lai, Hung-Hsiang Wang, Ming-Jer Kao
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Patent number: 6812080Abstract: As shown in FIG. 1(a), a gate oxide film 12 is formed on an Si substrate 11. A polysilicon layer 13 is formed thereon. A natural oxide film 14 having an arbitrary thickness is formed on the polysilicon layer 13 after phosphorus is made to diffuse into the polysilicon layer 13 and before a resist layer is coated. Thus, as shown in FIG. 1(b), the natural oxide film 14 present on the polysilicon layer 13 is removed by DHF cleaning (cleaning with dilute HF). Thereafter, a resist layer 15 is coated onto the polysilicon layer 13, and is patterned. A polysilicon gate electrode G is formed by dry-etching using the resist layer 15 as a mask.Type: GrantFiled: April 5, 2002Date of Patent: November 2, 2004Assignee: Seiko Epson CorporationInventor: Hirofumi Kobayashi
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Patent number: 6797551Abstract: An isolation region is embedded in a semiconductor substrate. The height of the upper face of the isolation region is substantially equal to the height of the surface of the semiconductor substrate. A gate electrode is formed on a gate insulating film and over the isolation region. A first side face of the gate electrode is formed over the isolation region. A second side face of the gate electrode is formed over the active region. A field insulator is formed on the isolation region. A first side face of the field insulator contacts with the first side face of the gate electrode. A second side face of the field insulator is continuous with a plane obtained by extending the side face of the isolation region. A sidewall insulator has a sidewall contacting with the second side face of the field insulator and the second side face of the gate electrode.Type: GrantFiled: December 11, 2002Date of Patent: September 28, 2004Assignee: Kabushi Kaisha ToshibaInventor: Kumi Oguchi