Abstract: A process for fabricating a CMOS device in which conductive gate structures are defined self-aligned to shallow trench isolation (STI), regions, without using a photolithographic procedure, has been developed. The process features definition of shallow trench openings in regions of a semiconductor substrate not covered by dummy gate structures, or by silicon oxide spacers located on sides of the dummy gate structures. Filling of the shallow trench openings with silicon oxide, and removal of the dummy gate structures, result in STI regions comprised of filled shallow trench openings, overlying silicon oxide shapes, and silicon oxide sidewall spacers on the sides of the overlying silicon oxide shapes. Formation of silicon nitride spacers on the sides of the STI regions, is followed by deposition of a high k gate insulator layer and of a conductive gate structure, with the conductive gate structure formed self-aligned to the STI regions.

Abstract: Disclosed is a method for forming a contact hole in the process of manufacturing a logic device employing a shallow trench isolation (STI) method. The method prevents an isolation region from being damaged because there is little overlap margin for a contact hole in the active region, when a contact hole is formed in an isolation region beyond the border of an active region, that is, when a borderless contact hole is formed. According to the method, a silicon nitride layer used as an etch-stop layer is formed in the process of providing the STI, thereby avoiding deterioration of the characteristics of a resulting semiconductor device.

Abstract: A nonwoven has low tensile and high elongation in the first direction (typically the CD) and high tensile and low elongation in the second direction (typically the MD). The nonwoven has a plurality of bonding points defining a total bonding area along the second direction greater than along the first direction. Accordingly, the nonwoven has unbonded fiber portions and bonded fiber portions, with a bonded portion/unbonded portion ratio greater along the second direction than along the first direction. The bonding points are preferably either circular or oval in plan.

Abstract: Plural p+-type regions are formed on a silicon substrate, and thereafter, an n-type epitaxial growth layer is formed. Narrow concave portions are formed to extend between the surface of the epitaxial growth layer 14 and the silicon substrate and to have the almost the same lateral sectional shape. As a result, remaining parts, which are defined by the concave portions, of the epitaxial growth layer on p+-type field limiting rings are separated from the silicon substrate. Thus, a depletion layer is spread beyond the field limiting rings and a large forward voltage-resistance can be realized.

Abstract: A method of fabricating an improved flash memory device having core stacks and periphery stacks which are protected with an oxide layer, a protective layer and an insulating layer. A high energy dopant implant is used to pass the dopant through the insulating layer, the protective layer and oxide layer into the substrate to create source and drain regions, without using a self aligned etch. The flash memory device has an intermetallic dielectric layer placed over the core stacks and the periphery stacks. A tungsten plug is placed in the intermetallic dielectric layer to provide an electrical connection to the drain of the flash memory device.

Abstract: Provided are a semiconductor device which shows excellent negative differential conductance or negative transconductance and is manufactured without a complicated manufacturing process and a method of manufacturing the same. The semiconductor device includes a channel layer serving as a conduction region and a floating region electrically separated from the channel layer. Provided between the channel layer and the floating region is a quantum well layer constituted with a pair of barrier layers and a quantum well layer sandwiched between the pair of barrier layers. A source electrode and a drain electrode are electrically connected to the channel layer. A gate electrode is provided in an opposite position from the well layer in the floating region. When changing a drain voltage relative to a predetermined gate voltage, drain current characteristics show negative differential conductance.

Abstract: A method of fabricating an isolated vertical transistor comprising the following steps. A wafer having a first implanted region selected from the group comprising a source region and a drain region is provided. The wafer further includes STI areas on either side of a center transistor area. The wafer is patterned down to the first implanted region to form a vertical pillar within the center transistor area using a patterned hardmask. The vertical pillar having side walls. A pad dielectric layer is formed over the wafer, lining the vertical pillar. A nitride layer is formed over the pad dielectric layer. The structure is patterned and etched through the nitride layer and the pad dielectric layer; and into the wafer within the STI areas to form STI trenches within the wafer. The STI trenches are filled with insulative material to form STIs within STI trenches. The patterned nitride and pad dielectric layers are removed. The patterned hardmask is removed.

Abstract: A process for integrating the fabrication of an N type, junction field effect transistor (NJFET), device, with the fabrication and a high voltage, P channel metal oxide semiconductor (PMOS), device, has been developed. The process includes the formation of a deep N well region for accommodation of the high voltage, PMOS device, while a shallow N well region is used to contain the NJFET device. Featured in the integrated fabrication sequence is the simultaneous formation of P type source/drain regions for the high voltage PMOS device, and the P type gate structure of the NJFET device.

Abstract: As shown in FIG. 1(a), a gate oxide film 12 is formed on an Si substrate 11. A polysilicon layer 13 is formed thereon. A natural oxide film 14 having an arbitrary thickness is formed on the polysilicon layer 13 after phosphorus is made to diffuse into the polysilicon layer 13 and before a resist layer is coated. Thus, as shown in FIG. 1(b), the natural oxide film 14 present on the polysilicon layer 13 is removed by DHF cleaning (cleaning with dilute HF). Thereafter, a resist layer 15 is coated onto the polysilicon layer 13, and is patterned. A polysilicon gate electrode G is formed by dry-etching using the resist layer 15 as a mask.

Abstract: First and second impurity diffusion regions are disposed in partial surface layers of a semiconductor substrate and spaced apart by some distance. A gate electrode is formed above a channel region defined between the first and second impurity diffusion regions. A gate insulating film is disposed between the channel region and gate electrode. Of the gate insulating film, a portion thereof disposed at least in a partial area along the longitudinal direction of a path interconnecting the first and second impurity diffusion regions, having a lamination structure of a first insulating film, a charge trap film and a second insulating film sequentially stacked in this order. The charge trap film is made of insulating material easier to trap electrons than the first and second insulating films.

Abstract: In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.

Abstract: A method of fabricating an integrated circuit, and an integrated circuit so fabricated, is disclosed. A silicon dioxide layer (14) that is doped with both boron and phosphorous, typically referred to as BPSG, is used as a planarizing layer in the integrated circuit structure, above which conductive structures (46, 52, 54) are disposed. A silicon nitride layer (30) is in place below the BPSG layer (14), and serves as a barrier to the diffusion of boron and phosphorous from the BPSG layer (14) during high temperature processes such as reflow and densification of the BPSG layer (14) itself. Contact openings (PC, BLC, CT) are etched through the BPSG layer (14) and the silicon nitride layer (30) using a two-step etch process.

Abstract: A method for fabricating a periodic table group III-IV metal semiconductor metal field-effect enhancement mode complementary transistor pair device is described, a device typically made of gallium arsenide materials. The disclosed fabrication uses initially undoped semiconductor materials, single metallization for ohmic and Schottky barrier contacts, employs a non-alloyed ohmic contact semiconductor layer and includes an inorganic dielectric material layer providing non photosensitive masking at plural points in the fabrication sequence. The invention uses selective ion implantations, and a combined optical and electron beam lithographic process, the latter in small dimension gate areas. These attributes are combined to provide a field-effect transistor complementary pair of reduced fabrication cost, low electrical energy operating requirements increased dimensional accuracy and current state of the art electrical performance. Fabricated device characteristics are also disclosed.

Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact--which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

Abstract: A method and apparatus for preventing charge damage to a protected structure during processing of a semiconductor device. A first source/drain region of a protection transistor is coupled to a protected transistor gate. A second source/drain region of the protection transistor is coupled to ground. The protection transistor is then turned on during the processing of the device to ground the protected transistor gate.

Abstract: A method for manufacturing a flash memory with a shallow trench isolation and a buried bit line. In the invention, the shallow trench isolation is used as an isolation region, so that the size of the devices can be greatly reduced and the integration of the devices can be greatly increased. Additionally, the shallow trench isolation is formed in the substrate before the buried bit line implantation step is performed, so that the short channel effect caused by the lateral diffusion of the doped ions can be eliminated. Moreover, since the neighboring doped regions are electrically coupled to each other through the polysilicon layer, the access rate of the flash memory can be enhanced.

Abstract: Protection structures for suppressing plasma damage. Plasma damage is shown to occur primarily during a metal clear portion of a metal etch as opposed to also occurring during the overetch portion of the etch. The protection structures (202) provide a temporary connection between the metal layer (210) being etched and the substrate or a protection device during the clear portion of the etch. This temporary connection (202) is removed as the metal (210) is cleared.

Abstract: The present invention is to provide a semiconductor integrated circuit having bipolar transistor elements with a reduced isolating distance between adjacent transistors and a reduced collector/substrate capacitance. In the surface of a P-type semiconductor substrate, N.sup.+ type regions are formed serving as buried collector regions of bipolar transistors TR1 and TR2. Between the N.sup.+ type regions, a P-type region for element isolation is provided not in contact with the N.sup.+ type regions. A P-type impurity concentration in the peripheral portions of N.sup.+ type regions is equal to that of the semiconductor substrate. The insulating film serving as an element-isolating layer is provided on the P-type region in contact therewith and thus electrically isolates adjacent bipolar transistors.