Specified Crystallographic Orientation Patents (Class 438/198)
  • Patent number: 10804376
    Abstract: A method of manufacturing a semiconductor device includes preparing a first wafer including a first trench; forming a first semiconductor layer inside the first trench so that a first space remains in the first trench; obtaining a first level corresponding to a bottom of the first space and a second level estimated by a size or a shape of the first space; preparing a second wafer including a second trench having a shape and a size substantially same as a shape and a size of the first trench; forming a second semiconductor layer inside the second trench in the second so that a second space remains in the second trench; forming a third semiconductor layer to fill the second space in the second trench; and removing a surface portion of the second wafer to a depth corresponding to a level between the first level and the second level.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: October 13, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Shigeaki Takagi
  • Patent number: 10797162
    Abstract: The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: You-Ru Lin, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 10388868
    Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: August 20, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chi Tu, Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang, Sheng-Hung Shih, Wen-Chun You, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 10254185
    Abstract: A sensor includes a deformable membrane that deflects in response to a stimuli. The sensor further includes a capacitive element coupled to the deformable membrane. The capacitive element is disposed within an enclosed cavity of the sensor. The capacitive element changes capacitance in response to the deformable membrane deflecting. The capacitive element comprises a getter material for collecting gas molecules within the enclosed cavity.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: April 9, 2019
    Assignee: InvenSense, Inc.
    Inventors: Johannes Schumm, Andreas Reinhard, Thomas Kraehenbuehl, Stefan Thiele, Rene Hummel, Chung-Hsien Lin, Wang Shen Su, Tsung Lin Tang, Chia Min Lin
  • Patent number: 10170365
    Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Chi-Wen Liu, Ying-Keung Leung
  • Patent number: 9691758
    Abstract: A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a fin extending away from a substrate, a plurality of epitaxially grown regions disposed along a top surface of the fin, and at least two contacts that provide electrical contact to the fin. The plurality of epitaxially grown regions are arranged to alternate with regions having no epitaxial material grown on the top surface of the fin. A resistance exists between the two contacts that is at least partially based on the arrangement of the plurality of epitaxially grown regions.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: June 27, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hsin Hu, Hsueh-Shih Fan, Huan-Tsung Huang
  • Patent number: 9576955
    Abstract: Semiconductor devices are provided. The semiconductor devices include active fins including a buffer layer disposed on a substrate and a channel layer disposed on the buffer layer and having a first second lattice constant higher than a lattice constant of the buffer layer, a gate structure covering the channel layer and intersecting the active fins, sidewall spacers disposed on both sidewalls of the gate structure, and capping layers disposed to contact lower surfaces of the sidewall spacers and having a width substantially the same as a width of the lower surfaces of the sidewall spacers.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: February 21, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Hwan Lee, Tae Yong Kwon, Sang Su Kim, Chang Jae Yang, Jung Han Lee, Hwan Wook Choi, Yeon Cheol Heo, Sang Hyuk Hong
  • Patent number: 9449866
    Abstract: The invention discloses a treatment process for a semiconductor, comprising providing a substrate, the substrate comprises silicon material; defining a trench region; removing the trench region using a plasma etching process and exposing a trench surface, the trench surface comprising surface defects; forming an oxidation layer overlaying the trench surface; removing the oxidation layer and at least a portion of the surface defects; expositing a treated trench surface, the treated trench surface being substantially free from surface defects; and forming a layer of silicon germanium material overlaying the treated trench surface. The invention further provides a semiconductor processing technique used to eliminate or reduce dislocation defect on the semiconductor device and improve device performance. In the treatment process, a substrate is subjected to at least one oxidation-deoxidation processes, where an oxidation layer is formed and then removed.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: September 20, 2016
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Quanbo Li, Jun Huang, Xiangguo Meng, Yu Zhang
  • Patent number: 9269608
    Abstract: A semiconductor structure is formed with a first wafer (e.g. a handle wafer) and a second wafer (e.g. a bulk silicon wafer) bonded together. The second wafer includes an active layer, which in some embodiments is formed before the two wafers are bonded together. A substrate is removed from the second wafer on an opposite side of the active layer from the first wafer using a SiGeC or SiGeBC layer as an etch stop. In some embodiments, the SiGeC or SiGeBC layer is formed by epitaxial growth, ion implantation or a combination of epitaxial growth and ion implantation.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: February 23, 2016
    Assignee: QUALCOMM SWITCH CORP.
    Inventor: Stephen A. Fanelli
  • Patent number: 9159617
    Abstract: Embodiments of the invention provide a semiconductor structure and a method of forming a semiconductor structure. Embodiments of the semiconductor structure have a plurality of fins on a substrate. The semiconductor has, and the method achieves, a silicide layer formed on and substantially surrounding at least one epitaxial region formed on a top portion of the plurality of fins. Embodiments of the present invention provide a method and structure for forming a conformal silicide layer on the epitaxial regions that are formed on the top portion of unmerged fins of a finFET.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: October 13, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xunyuan Zhang, Xiuyu Cai
  • Patent number: 9059234
    Abstract: Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening. Then, the second etch is performed such that an undoped region of the substrate at the sidewalls of the opening is etched at a faster etch rate than the doped region, thereby ensuring that the trench has a relatively high aspect ratio. Also disclosed is a bipolar semiconductor device formation method. This method incorporates the trench formation technique so that a trench isolation region formed around a collector pedestal has a high aspect ratio and, thereby so that collector-to-base capacitance Ccb and collector resistance Rc are both minimized.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: John J. Benoit, James R. Elliott, Qizhi Liu
  • Patent number: 9053947
    Abstract: A method includes forming a gate stack over a semiconductor fin, wherein the semiconductor fin forms a ring, and etching a portion of the semiconductor fin not covered by the gate stack to form a recess. The method further includes performing an epitaxy to grow an epitaxy semiconductor region from the recess, forming a first contact plug overlying and electrically coupled to the epitaxy semiconductor region, and forming a second contact plug, wherein the second contact plug is overlying and electrically coupled to the gate stack.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: June 9, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hsin Hu, Min-Chang Liang
  • Publication number: 20150140747
    Abstract: A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a bulk epitaxial pattern disposed in a recess region formed in the semiconductor substrate at a side of the gate pattern, an insert epitaxial pattern disposed on the bulk epitaxial pattern, and a capping epitaxial pattern disposed on the insert epitaxial pattern. The bulk epitaxial pattern has an upper inclined surface that is a {111} crystal plane, and the insert epitaxial pattern includes a specific element that promotes the growth rate of the insert epitaxial pattern on the upper inclined surface.
    Type: Application
    Filed: December 10, 2014
    Publication date: May 21, 2015
    Inventors: Dong Hyuk Kim, Dongsuk Shin, Hoi Sung Chung, Naein Lee
  • Patent number: 9012276
    Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFET) are manufactured using a high-K, metal-gate ‘channel-last’ process. Between spacers formed over a well area having separate drain and source areas, a recess in the underlying is formed using a crystallographic etch to provide [111] boundaries adjacent the source and drain regions. An ion implant step localized by the cavity results in a localized increase in well-doping directly beneath the recess. Within the recess, an active region is formed using an un-doped or lightly doped epitaxial layer, deposited at a very low temperature. A high-K dielectric stack is formed over the lightly doped epitaxial layer, over which a metal gate is formed within the cavity boundaries.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: April 21, 2015
    Assignee: Gold Standard Simulations Ltd.
    Inventors: Ashok K. Kapoor, Asen Asenov
  • Patent number: 9006070
    Abstract: Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min Hao Hong, You-Hua Chou, Chih-Tsung Lee, Shiu-Ko JangJian, Miao-Cheng Liao, Hsiang-Hsiang Ko, Chen-Ming Huang
  • Publication number: 20150087120
    Abstract: A semiconductor structure and method of manufacturing the same are provided. The semiconductor device includes epitaxial raised source/drain (RSD) regions formed on the surface of a semiconductor substrate through selective epitaxial growth. In one embodiment, the faceted side portions of the RSD regions are utilized to form cavity regions which may be filled with a dielectric material to form dielectric spacer regions. Spacers may be formed over the dielectric spacer regions. In another embodiment, the faceted side portions may be selectively grown to form air gap spacer regions in the cavity regions. A conformal spacer layer with interior and exterior surfaces may be formed in the cavity region, creating an air gap spacer defined by the interior surfaces of the conformal spacer layer.
    Type: Application
    Filed: December 1, 2014
    Publication date: March 26, 2015
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Juntao Li, Alexander Reznicek
  • Patent number: 8987079
    Abstract: A method for developing a custom device, the method including: programming a programmable device, where the programmable device includes a layer of monocrystalline first transistors and alignment marks, the first layer of monocrystalline first transistors is overlaid by interconnection layers, the interconnection layers are overlaid by a second layer of monocrystalline second transistors, where the interconnection layers include copper or aluminum, where the programming includes use of the second transistors, where the programming includes use of N type transistors and P type transistors, and where the programmable device includes at least one programmable connection; and then a step of producing a volume device according to a specific programmed design of the programmable device, where the volume device includes the at least one programmable connection replaced with a lithography defined connection, and where the volume device does not have the second layer.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: March 24, 2015
    Assignee: Monolithic 3D Inc.
    Inventor: Zvi Or-Bach
  • Patent number: 8981493
    Abstract: An improved finFET and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon. Fins are formed that have {110} silicon on the fin tops and {100} silicon on the long fin sides (sidewalls). The lateral epitaxial growth rate is faster than the vertical epitaxial growth rate. The resulting merged fins have a reduced merged region in the vertical dimension, which reduces parasitic capacitance. Other fins are formed with {110} silicon on the fin tops and also {110} silicon on the long fin sides. These fins have a slower epitaxial growth rate than the {100} side fins, and remain unmerged in a semiconductor integrated circuit, such as an SRAM circuit.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Thomas N. Adam, Ali Khakifirooz, Alexander Reznicek
  • Publication number: 20140367768
    Abstract: A method for fabricating a semiconductor device includes forming an isolation feature in a substrate, forming a gate stack over the substrate, forming a source/drain (S/D) recess cavity in the substrate, where the S/D recess cavity is positioned between the gate stack and the isolation feature. The method further includes forming an epitaxial (epi) material in the S/D recess cavity, where the epi material has an upper surface which including a first crystal plane. Additionally, the method includes performing a redistribution process to the epi material in the S/D recess cavity using a chlorine-containing gas, where the first crystal plane is transformed to a second crystal plane after the redistribution.
    Type: Application
    Filed: September 2, 2014
    Publication date: December 18, 2014
    Inventors: Yen-Ru LEE, Ming-Hua YU, Tze-Liang LEE, Chii-Horng LI, Pang-Yen TSAI, Lilly SU, Yi-Hung LIN, Yu-Hung CHENG
  • Patent number: 8912052
    Abstract: A semiconductor device, including: a first layer including monocrystalline material and first transistors, the first transistors overlaid by a first isolation layer; a second layer including second transistors and overlaying the first isolation layer, the second transistors including a monocrystalline material; at least one contact to the second transistors, where the at least one contact is aligned to the first transistors with less than about 40 nm alignment error, a first set of external connections underlying the first layer to connect the device to external devices; and a second set of external connections overlying the second layer to connect the device to external devices.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: December 16, 2014
    Assignee: Monolithic 3D Inc.
    Inventor: Zvi Or-Bach
  • Patent number: 8900942
    Abstract: A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: December 2, 2014
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Dong Hyuk Kim, Dongsuk Shin, Myungsun Kim, Hoi Sung Chung
  • Patent number: 8900978
    Abstract: A method for making a semiconductor device includes forming at least one gate stack on a layer comprising a first semiconductor material and etching source and drain recesses adjacent the at least one gate stack. The method further includes shaping the source and drain recesses to have a vertical side extending upwardly from a bottom to an inclined extension adjacent the at least one gate stack.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: December 2, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Nicolas Loubet, Douglas LaTulipe, Alexander Reznicek
  • Patent number: 8889503
    Abstract: Provided is a method for manufacturing a semiconductor device which includes, on a wafer which has a notch, a plurality of transistors parallel with and perpendicular to a notch direction extending between the center of the wafer and the notch, the method including: preparing the wafer having the front surface which has Off angle of at least 2 degrees and at most 2.8 degrees from plane in a direction in which Twist angle relative to the notch direction is at least 12.5 degrees and at most 32.5 degrees; and doping impurities into the front surface of the wafer in a direction perpendicular to the front surface.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: November 18, 2014
    Assignee: Panasonic Corporation
    Inventor: Kenji Yoneda
  • Patent number: 8883651
    Abstract: A method of manufacturing a transistor of a semiconductor device, the method including forming a gate pattern on a semiconductor substrate, forming a spacer on a sidewall of the gate pattern, wet etching the semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess is adjacent to the spacer, and wet etching the first recess to form a second recess in the semiconductor substrate.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seokhoon Kim, Sangsu Kim, Chung Geun Koh, Byeongchan Lee, Sunghil Lee, Jinyeong Joe
  • Publication number: 20140326952
    Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
    Type: Application
    Filed: May 9, 2014
    Publication date: November 6, 2014
    Inventors: Kelin J. KUHN, Seiyon KIM, Rafael RIOS, Stephen M. Cea, Martin D. GILES, Annalisa CAPPELLANI, Titash RAKSHIT, Peter CHANG, Willy RACHMADY
  • Patent number: 8853023
    Abstract: A method for stressing a pattern having a pattern surface, in a layer of semiconductive material that can be silicon on the surface of a stack of layers generated on the surface of a substrate, said stack comprising at least one stress layer of alloy SixGey with x and y being molar fractions, and a buried layer of silicon oxide, comprises: etching at the periphery of a surface of dimensions greater than said pattern surface, of the buried layer of silicon oxide and layer of alloy SixGey over a part of the depth of said layer of alloy; the buried layer of silicon oxide being situated between said layer of semiconductive material and said stress layer of alloy SixGey. In a transistor structure, etching at the periphery of said surface obtains a pattern thus defined having dimensions greater than the area of interest situated under the gate of the transistor.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: October 7, 2014
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Simeon Morvan, Francois Andrieu, Jean-Charles Barbe
  • Patent number: 8816430
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a gate electrode, source/drain regions, and a gate insulating film. The substrate is made of monocrystalline silicon, an upper surface of the substrate is a (100) plane, and a trench is made in the upper surface. The gate electrode is provided in at least an interior of the trench. The source/drain regions are formed in regions of the substrate having the trench interposed. The gate insulating film is provided between the substrate and the gate electrode. The trench includes a bottom surface made of a (100) plane, a pair of oblique surfaces made of (111) planes contacting the bottom surface, and a pair of side surfaces made of (110) planes contacting the oblique surfaces. The source/drain regions are in contact with the side and oblique surfaces and are apart from a central portion of the bottom surface.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Yanagisawa
  • Patent number: 8809947
    Abstract: In an exemplary embodiment, a method for fabricating integrated circuits includes providing a semiconductor substrate. The method etches the semiconductor substrate to form a non-planar transistor structure having sidewalls. On a standard (100) <110> substrate the fin sidewalls have (110) surface plane if the fins are aligned or perpendicular with the <110> wafer notch. The method includes depositing a sacrificial liner along the sidewalls of the non-planar transistor structure. Further, a confining material is deposited overlying the semiconductor substrate and adjacent the sacrificial liner. The method includes removing at least a portion of the sacrificial liner and forming a void between the sidewalls of the non-planar transistor structure and the confining material. A cladding layer is epitaxially grown in the void. Since the sidewall growth is limited by the confining material, a cladding layer of uniform thickness is enabled on fins with (110) sidewall and (100) top surface.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: August 19, 2014
    Assignee: GlobalFoundries, Inc.
    Inventors: Kerem Murat Akarvardar, Ajey Poovannummoottil Jacob
  • Patent number: 8809852
    Abstract: One of objects is to provide a semiconductor film having stable characteristics. Further, one of objects is to provide a semiconductor element having stable characteristics. Further, one of objects is to provide a semiconductor device having stable characteristics. Specifically, a structure which includes a seed crystal layer (seed layer) including crystals each having a first crystal structure, one of surfaces of which is in contact with an insulating surface, and an oxide semiconductor film including crystals growing anisotropically, which is on the other surface of the seed crystal layer (seed layer) may be provided. With such a heterostructure, electric characteristics of the semiconductor film can be stabilized.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: August 19, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Takahashi, Tetsunori Maruyama
  • Publication number: 20140217499
    Abstract: A structure includes a semiconductor substrate including a first semiconductor material. A portion of the semiconductor substrate extends between insulation regions in the semiconductor substrate. The portion of the semiconductor substrate has a (111) surface and a bottom surface. The (111) surface is slanted and has a top edge and a bottom edge. The bottom surface is parallel to a top surface of the insulation regions, and is connected to the bottom edge. A semiconductor region overlaps the portion of the semiconductor substrate, wherein the semiconductor region includes a second semiconductor material different from the first semiconductor material. The top edge and the bottom edge of the (111) surface are at a first depth and a second depth, respectively, relative to a top surface of the semiconductor region. A ratio of the first depth to the second depth is smaller than about 0.6.
    Type: Application
    Filed: February 1, 2013
    Publication date: August 7, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Taiwan Semiconductor Manufacturing Company, Ltd.
  • Patent number: 8790972
    Abstract: Methods of forming integrated circuit devices include forming a PMOS transistor having a SiGe channel region therein and then exposing at least a portion of the PMOS transistor to a hydrogen plasma. A tensile stress layer may be formed on the PMOS transistor. The exposing step may include exposing source and drain regions of the PMOS transistor to the hydrogen plasma.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: July 29, 2014
    Assignees: Samsung Electronics Co., Ltd., International Business Machines Corporation, GLOBALFOUNDRIES Singapore Pte. Ltd., Freescale Semiconductor, Inc.
    Inventors: Yong-Kuk Jeong, Laegu Kang, Kim Nam Sung, Dae-won Yang
  • Patent number: 8765540
    Abstract: The present invention provides a semiconductor structure, which comprises: a substrate, a semiconductor base, a semiconductor auxiliary base layer, a cavity, a gate stack, a sidewall spacer, and a source/drain region, wherein the gate stack is located on the semiconductor base; the sidewall spacer is located on the sidewalls of the gate stack; the source/drain region is embedded in the semiconductor base and is located on both sides of the gate stack; the cavity is embedded in the substrate; the semiconductor base is suspended above the cavity, the thickness of the middle portion of the semiconductor base is greater than the thickness of the two end portions of the semiconductor base in the direction of the length of the gate, and the two end portions of the semiconductor base are connected to the substrate in the direction of the width of the gate; and the semiconductor auxiliary base layer is located on the sidewall of the semiconductor base and has an opposite doping type to that of the source/drain region
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: July 1, 2014
    Assignee: The Institute of Microelectronics Chinese Academy of Science
    Inventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo
  • Publication number: 20140179070
    Abstract: A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A conductive feature is disposed over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region. A dielectric material is disposed between the conductive feature and the semiconductor region. The dielectric material, the conductive feature, and the semiconductor region form an anti-fuse.
    Type: Application
    Filed: February 25, 2014
    Publication date: June 26, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hsiao-Lan Yang
  • Publication number: 20140179071
    Abstract: Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel.
    Type: Application
    Filed: February 25, 2014
    Publication date: June 26, 2014
    Inventors: Min Hao Hong, You-Hua Chou, Chih-Tsung Lee, Shiu-Ko JangJian, Miao-Cheng Liao, Hsiang-Hsiang Ko, Chen-Ming Huang
  • Publication number: 20140170998
    Abstract: A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Inventors: Han Wui THEN, Sansaptak DASGUPTA, Marko RADOSAVLJEVIC, Benjamin CHU-KUNG, Sanaz K. GARDNER, Seung Hoon SUNG, Robert S. CHAU
  • Publication number: 20140151705
    Abstract: A method is provided for fabricating a nanowire-based semiconductor structure. The method includes forming a first nanowire with a first polygon-shaped cross-section having a first number of sides. The method also includes forming a semiconductor layer on surface of the first nanowire to form a second nanowire with a second polygon-shaped cross-section having a second number of sides, the second number being greater than the first number. Further, the method includes annealing the second nanowire to remove a substantial number of vertexes of the second polygon-shaped cross-section to form the nanowire with a non-polygon-shaped cross-section corresponding to the second polygon-shaped cross-section.
    Type: Application
    Filed: March 15, 2013
    Publication date: June 5, 2014
    Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP.
    Inventors: DEYUAN XIAO, JAMES HONG
  • Publication number: 20140154848
    Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer.
    Type: Application
    Filed: February 6, 2014
    Publication date: June 5, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Su-Horng Lin, Chi-Ming Yang, Chyi Shyuan Chern, Chin-Hsiang Lin
  • Publication number: 20140145245
    Abstract: A semiconductor field-effect device is disclosed that utilizes an octagonal or inverse-octagonal deep trench super-junction in combination with an octagonal or inverse-octagonal gate trench. The field-effect device achieves improved packing density, improved current density, and improved on resistance, while at the same time maintaining compatibility with the multiple-of-45°-angles of native photomask processing and having well characterized (010), (100) and (110) (and their equivalent) silicon sidewall surfaces for selective epitaxial refill and gate oxidation, resulting in improved scalability. By varying the relative length of each sidewall surface, devices with differing threshold voltages can be achieved without additional processing steps. Mixing trenches with varying sidewall lengths also allows for stress balancing during selective epitaxial refill.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 29, 2014
    Applicant: D3 Semiconductor LLC
    Inventors: Thomas E. Harrington, III, Robert Kuo-Chang Yang
  • Patent number: 8735237
    Abstract: The thickness of drain and source areas may be reduced by a cavity etch used for refilling the cavities with an appropriate semiconductor material, wherein, prior to the epitaxial growth, an implantation process may be performed so as to allow the formation of deep drain and source areas without contributing to unwanted channel doping for a given critical gate height. In other cases, the effective ion blocking length of the gate electrode structure may be enhanced by performing a tilted implantation step for incorporating deep drain and source regions.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: May 27, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Uwe Griebenow, Kai Frohberg, Frank Feustel, Thomas Werner
  • Patent number: 8729607
    Abstract: Structures and methods are presented relating to formation of finFET semiconducting devices. A finFET device is presented comprising fin(s) formed on a substrate, wherein the fin(s) has a needle-shaped profile. The needle-shaped profile, in conjunction with at least a buffer layer or a doped layer, epitaxially formed on the fin(s), facilitates strain to be induced into the fin(s) by the buffer layer or the doped layer. The fin(s) can comprise silicon aligned on a first plane, while at least one of the buffer layer or the doped layer are grown on a second plane, the alignment of the first and second planes are disparate and are selected such that formation of the buffer layer or the doped layer generates a stress in the fin(s). The generated stress results in a strain being induced into the fin(s) channel region, which can improve electron and/or hole mobility in the channel.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Itokawa, Akira Hokazono
  • Publication number: 20140117366
    Abstract: According to an embodiment, a semiconductor device includes an underlying layer and a plurality of transistors. The underlying layer includes a first region and a second region provided adjacently to the first region. The transistors are arranged in a plane parallel to an upper surface of the underlying layer. Each transistor includes a channel allowing a current to flow in a first direction intersecting the plane. The plurality of transistors includes a first transistor provided on the first region and a second transistor provided on the second region, a first channel of the first transistor having a first crystal orientation, and a second channel of the second transistor having a second crystal orientation different from the first crystal orientation.
    Type: Application
    Filed: September 13, 2013
    Publication date: May 1, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Masumi SAITOH
  • Publication number: 20140106521
    Abstract: Provided is a method for manufacturing a semiconductor device which includes, on a wafer which has a notch, a plurality of transistors parallel with and perpendicular to a notch direction extending between the center of the wafer and the notch, the method including: preparing the wafer having the front surface which has Off angle of at least 2 degrees and at most 2.8 degrees from plane in a direction in which Twist angle relative to the notch direction is at least 12.5 degrees and at most 32.5 degrees; and doping impurities into the front surface of the wafer in a direction perpendicular to the front surface.
    Type: Application
    Filed: December 12, 2013
    Publication date: April 17, 2014
    Applicant: Panasonic Corporation
    Inventor: Kenji YONEDA
  • Publication number: 20140106520
    Abstract: A semiconductor device manufacturing method with high productivity is disclosed with improved trade-off relationship between auto-doping and breakdown in alignment mark form. First to sixth epitaxial layers are grown sequentially on Si {100} main surface of an arsenic doped substrate using multilayer epitaxial technology. Epitaxial growth conditions of the first to sixth epitaxial layers are growth at atmospheric pressure and a temperature of 1,150° C. to 1,180° C., with epitaxial growth rate of 2.2 to 2.6 ?m/minute. An alignment mark of depressed form whose bottom surface is the Si {100} plane is formed in the arsenic doped substrate. Every time one of the first to sixth epitaxial layers is grown on the main surface of the arsenic doped substrate, an alignment mark of depressed form is formed in the outermost epitaxial layer by a portion above the alignment mark of the layer below being transformed.
    Type: Application
    Filed: October 11, 2013
    Publication date: April 17, 2014
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Kazuya YAMAGUCHI
  • Publication number: 20140106522
    Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.
    Type: Application
    Filed: December 23, 2013
    Publication date: April 17, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Huan Tsai, Chun-Fai Cheng, Hui Ouyang, Yuan-Hung Chiu, Yen-Ming Chen
  • Patent number: 8697522
    Abstract: A fin Field Effect Transistor (finFET), an array of finFETs, and methods of production thereof. The finFETs are provided on an insulating region, which may optionally contain dopants. Further, the finFETs are optionally capped with a pad. The finFETs provided in an array are of uniform height.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: April 15, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris
  • Patent number: 8686438
    Abstract: When viewed in a plan view, a termination region (TM) surrounds an element region (CL). A first side of a silicon carbide substrate (SB) is thermally etched to form a side wall (ST) and a bottom surface (BT) in the silicon carbide substrate (SB) at the termination region (TM). The side wall (ST) has a plane orientation of one of {0-33-8} and {0-11-4}. The bottom surface (BT) has a plane orientation of {000-1}. On the side wall (ST) and the bottom surface (BT), an insulating film (8T) is formed. A first electrode (12) is formed on the first side of the silicon carbide substrate (SB) at the element region (CL). A second electrode (14) is formed on a second side of the silicon carbide substrate (SB).
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: April 1, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Takeyoshi Masuda, Keiji Wada
  • Patent number: 8673704
    Abstract: A FinFET and a method for manufacturing the same are disclosed. The FinFET comprises an etching stop layer on a semiconductor substrate; a semiconductor fin on the etching stop layer; a gate conductor extending in a direction perpendicular to a length direction of the semiconductor fin and covering at least two side surfaces of the semiconductor fin; a gate dielectric layer between the gate conductor and the semiconductor fin; a source region and a drain region which are provided at two ends of the semiconductor fin respectively; and an interlayer insulating layer adjoining the etching stop layer below the gate dielectric layer, and separating the gate conductor from the etching stop layer and the semiconductor fin. A height of the fin of the FinFET is approximately equal to a thickness of a semiconductor layer for forming the semiconductor fin.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: March 18, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Wei He, Qingqing Liang, Haizhou Yin, Zhijiong Luo
  • Patent number: 8664056
    Abstract: When forming cavities in active regions of semiconductor devices in order to incorporate a strain\-inducing semiconductor material, superior uniformity may be achieved by using an implantation process so as to selectively modify the etch behavior of exposed portions of the active region. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility, while at the same time the dependence on pattern loading effect may be reduced. Consequently, a significantly reduced variability of transistor characteristics may be achieved.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: March 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Frank Wirbeleit, Andy Wei
  • Publication number: 20140054657
    Abstract: In one embodiment, a semiconductor device includes a substrate, a gate insulator on the substrate, and a gate electrode on the gate insulator. The device further includes a source diffusion layer of a first conductivity type and a drain diffusion layer of a second conductivity type disposed on a surface of the substrate so as to sandwich the gate electrode. The device further includes a junction forming region disposed between the source diffusion layer and the drain diffusion layer so as to contact the source diffusion layer. The junction forming region includes a source extension layer of the first conductivity type, a pocket layer of the second conductivity type above the source extension layer, and a diffusion suppressing layer disposed between the source extension layer and the pocket layer and containing carbon so as to suppress diffusion of impurities between the source extension layer and the pocket layer.
    Type: Application
    Filed: February 13, 2013
    Publication date: February 27, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira HOKAZONO, Yoshiyuki KONDO, Toshitaka MIYATA
  • Patent number: 8658488
    Abstract: A graphene layer is provided onto at least an upper surface of a first dielectric material which includes at least one first conductive region contained therein. At least one semiconductor device is formed using the graphene layer as an element of the at least one semiconductor device. After forming the at least one semiconductor device, a second dielectric material is formed covering the graphene layer, the at least one semiconductor device, and portions of the first dielectric material. The second dielectric that is formed includes at least one second conductive region contained therein, and the at least one second conductive region is in contact with a conductive element of the at least one semiconductor device.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Christos D. Dimitrakopoulos, Guy Cohen, Stephen M. Gates, Alfred Grill, Timothy J. McArdle, Chun-yung Sung