Abstract: A finFET and its method for fabrication include a gate electrode formed over a channel region of a semiconductor fin. The semiconductor fin has a crystallographic orientation and an axially specific piezoresistance coefficient. The gate electrode is formed with an intrinsic stress determined to influence, and preferably optimize, charge carrier mobility within the channel region. To that end, the intrinsic stress preferably provides induced axial stresses within the gate electrode and semiconductor fin channel region that complement the axially specific piezoresistance coefficient.

Abstract: Metal-oxide semiconductor field effect transistor (MOSFET) devices having metal gate stacks and techniques for improving performance thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate having a buried oxide layer at least a portion of which is configured to serve as a primary background oxygen getterer of the device; and a gate stack separated from the substrate by an interfacial oxide layer. The gate stack comprises a high-K layer over the interfacial oxide layer; and a metal gate layer over the high-K layer.

Abstract: The present invention includes a technique for making a dual voltage integrated circuit device. A gate dielectric layer is formed on a semiconductor substrate and a gate material layer is formed on the dielectric layer. A first region of the gate material layer is doped to a first nonzero level and a second region of the gate material level is doped to a second nonzero level greater than the first level. A first field effect transistor is defined that has a first gate formed from the first region. Also, a second field effect transistor is defined that has a second gate formed from the second region. The first transistor is operable at a gate threshold voltage greater than the second transistor in accordance with a difference between the first level and the second level.

Abstract: A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.

Abstract: At least one recessed region having two parallel edges is formed in an insulator layer over a semiconductor layer such that the lengthwise direction of the recessed region coincides with optimal carrier mobility surfaces of the semiconductor material in the semiconductor layer for finFETs to be formed. Self-assembling block copolymers are applied within the at least one recessed region and annealed to form a set of parallel polymer block lines having a sublithographic width and containing a first polymeric block component. The pattern of sublithographic width lines is transferred into the semiconductor layer employing the set of parallel polymer block lines as an etch mask. Sublithographic width semiconductor fins thus formed may have sidewalls for optimal carrier mobility for p-type finFETs and n-type finFETs.

Abstract: A semiconductor process and apparatus includes forming <100> channel orientation PMOS transistors (34) with enhanced hole mobility in the channel region of a transistor by epitaxially growing a bi-axially stressed silicon germanium channel region layer (22), alone or in combination with an underlying silicon carbide layer (86), prior to forming a PMOS gate structure (36) overlying the channel region layer, and then depositing a neutral (53) or compressive (55) contact etch stop layer over the PMOS gate structure. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.

Abstract: A method of manufacturing a semiconductor device, including the steps of preparing a silicon substrate which has a main surface whose plane direction is a surface (100); forming an n channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) which has a gate electrode, a source region, a drain region and a channel whose channel length direction is parallel to a crystal orientation <100> of the silicon substrate; and forming NiSi over the gate electrode and NiSi2 over the source region and the drain region at the same steps.

Abstract: Apparatus and systems may include integrated circuits for use with Radio Frequency Identification (RFID) tags having an antenna structure with at least three coupling ends. The integrated circuits may include three or more nodes corresponding respectively to the at least three coupling ends, and a modulator switch to receive a single modulator switching signal input. Methods may include those used to form and operate such circuits. Additional apparatus, systems, and methods are disclosed.

Abstract: A method of forming a semiconductor structure having a hybrid crystal orientation and forming MOSFETs having improved performance on the semiconductor structure is provided. The method includes providing a substrate comprising a buried oxide (BOX) on a first semiconductor layer, and a second semiconductor layer on the BOX, wherein the first and second semiconductor layers have a first and a second crystal orientation, respectively, and wherein the substrate comprises a first region and a second region. An isolation structure is formed in the second region extending to the first semiconductor layer. A trench is then formed in the isolation structure, exposing the first semiconductor layer. A semiconductor material is epitaxially grown in the trench. The method further includes forming a MOSFET of a first type on the second semiconductor layer and a MOSFET of an opposite type than the first type on the epitaxially grown semiconductor material.

Abstract: A method for fabricating a hybrid orientation substrate includes steps of providing a direct silicon bonding (DSB) wafer having a first substrate with (100) crystalline orientation and a second substrate with (110) crystalline orientation directly bonded on the first substrate, forming and patterning a first blocking layer on the second substrate to define a first region not covered by the first blocking layer and a second region covered by the first blocking layer, performing an amorphization process to transform the first region of the second substrate into an amorphized region, and performing an annealing process to recrystallize the amorphized region into the orientation of the first substrate and to make the second region stressed by the first blocking layer.

Abstract: The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.

Abstract: A CMOS structure includes a v-shape surface in an nMOSFET region. The v-shape surface has an orientation in a (100) plane and extends into a Si layer in the nMOSFET region. The nMOSFET gate dielectric layer is a high-k material, such as Hf02. The nMOSFET has a metal gate layer, such as Ta. Poly-Si is deposited on top of the metal gate layer.

Abstract: A semiconductor structure, such as a CMOS semiconductor structure, includes a field effect device that includes a plurality of source and drain regions that are asymmetric. Such a source region and drain region asymmetry is induced by fabricating the semiconductor structure using a semiconductor substrate that includes a horizontal plateau region contiguous with and adjoining a sloped incline region. Within the context of a CMOS semiconductor structure, such a semiconductor substrate allows for fabrication of a pFET and an nFET upon different crystallographic orientation semiconductor regions, while one of the pFET and the nFET (i.e., typically the pFET) has asymmetric source and drain regions.

Abstract: The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer.

Abstract: An SRAM bit cell structure that can be produced in small sizes while maintaining performance is presented. In one configuration, an SRAM bit cell includes driver field effect transistors that are p-type field effect transistors, load field effect transistors that are n-type field effect transistors and transfer gates that are p-type field effect transistors. Each field effect transistor may be arranged on a substrate that will enhance performance. In one arrangement, the p-type field effect transistors may be arranged on a silicon (110) substrate to enhance hole mobility while the n-type field effect transistors may be arranged on a silicon on insulator (100) substrate to enhance electron mobility. In another arrangement, the load n-type field effect transistor may be arranged on the same silicon (110) substrate as the other field effect transistors in the cell.

Abstract: A semiconductor device includes a semiconductor substrate having, on a surface thereof, a (110) surface of Si1-xGex (0.25?x?0.90), and n-channel and p-channel MISFETs formed on the (110) surface, each MISFET having a source region, a channel region and a drain region. Each MISFET has a linear active region which is longer in a [?110] direction than in a [001] direction and which has a facet of a (311) or (111) surface, the source region, the channel region and the drain region are formed in this order or in reverse order in the [?110] direction of the linear active region, the channel region of the n-channel MISFET is formed of Si and having uniaxial tensile strain in the [?110] direction, and the channel region of the p-channel MISFET being formed of Si1-yGey (x<y?1) and having uniaxial compressive strain in the [?110] direction.

Abstract: A method of fabricating a dual-gate semiconductor device, including forming a first PMOS transistor on a semiconductor substrate, the first PMOS transistor having a first gate electrode and a first gate insulation layer; and forming a first NMOS transistor on the semiconductor substrate, the first NMOS transistor having a second gate electrode and a second gate insulation layer. The gate insulation layer of the first PMOS transistor is a silicon nitride oxide layer.

Abstract: This invention provides a strained-channel field effect transistor (FET) in which the semiconductor of the channel of the FET is formed in a compliant substrate layer disposed over a twist-bonded semiconductor interface. This FET geometry increases the efficacy of local stress elements such as stress liners and embedded lattice-mismatched source/drain regions by mechanically decoupling the semiconductor of the channel region from the underlying rigid substrate. These strained-channel FETs may be incorporated into complementary metal oxide semiconductor (CMOS) circuits in various combinations. In one embodiment of this invention, both pFETs and nFETs are in a twist-bonded (001) silicon layer on a (001) silicon base layer. In another embodiment, pFETs are in a twist-bonded (011) silicon layer on a (001) silicon base layer and nFETs are in a conventional, non-twist-bonded (001) silicon base layer.

Abstract: Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Methods such as amorphization and templated recrystallization (ATR) have disadvantages for fabrication of deep submicron CMOS. This invention is a method of forming an integrated circuit (IC) which has (100) and (110)-oriented regions. The method forms a directly bonded silicon (DSB) layer of (110)-oriented silicon on a (100)-oriented substrate. The DSB layer is removed in the NMOS regions and a (100)-oriented silicon layer is formed by selective epitaxial growth (SEG), using the substrate as the seed layer. NMOS transistors are formed on the SEG layer, while PMOS transistors are formed on the DSB layer. An integrated circuit formed with the inventive method is also disclosed.

Abstract: Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells appropriate for the technology node. This invention provides a method of forming an integrated circuit (IC) substrate containing regions with two different silicon crystal lattice orientations. Starting with a (110) direct silicon bonded (DSB) layer on a (100) substrate, regions in the DSB layer are amorphized and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Lateral templating by the DSB layer is reduced by amorphization of the upper portion of the (110) regions through a partially absorbing amorphization hard mask. Boundary morphology is less than 40 nanometers wide. An integrated circuit formed with the inventive method is also disclosed.

Abstract: The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. In particular, this invention provides a melt-recrystallization ATR method, for use alone or in combination with non-melt-recrystallization ATR methods, in which selected Si regions bounded by dielectric-filled trenches are induced to undergo an orientation change by the steps of preamorphization, laser-induced melting, and corner-defect-free templated recrystallization from the melt.

Abstract: An epitaxial layer of silicon (Si) or silicon-germanium (SiGe) extends over the edge of silicon trench isolation (STI), thereby increasing the effective width of an active silicon region (RX) bordered by the STI. The RX region may have a <100> crystal orientation. An effective width of an FET device formed in the RX region may be increased, therefore performance may be improved with same density. Isolation may not be degraded since RX-to-RX distance is same at bottom. Junction capacitance may be reduced since part of the RX is on STI.

Abstract: A semiconductor process and apparatus provide a shallow trench isolation region (96) with a trench liner (95, 104) for use in a hybrid substrate device (21) by lining a first trench with a first trench liner (95), and then lining a second trench formed within the first trench by depositing a second trench liner (104) that is anisotropically etched to expose an underlying substrate (70) on which is epitaxially grown a silicon layer (110) to fill the second trench. By forming first gate electrodes (251) over a first SOI substrate (90) using deposited (100) silicon and forming second gate electrodes (261) over an epitaxially grown (110) silicon substrate (110), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (261) having improved hole mobility.

Abstract: A method of fabricating a semiconductor device according to one embodiment of the invention includes: forming a gate electrode on a semiconductor substrate through a gate insulating film; forming offset spacers on side surfaces of the gate electrode, respectively; etching the semiconductor substrate with a channel region below the offset spacers and the gate electrode being left by using the offset spacers as a mask; forming a first epitaxial layer made of a crystal having a lattice constant different from that of a crystal constituting the semiconductor substrate on the semiconductor substrate thus etched; etching at least a portion of the first epitaxial layer adjacent to the channel region to a predetermined depth from a surface of the first epitaxial layer toward the semiconductor substrate side; and forming a second epitaxial layer containing therein a conductivity type impurity on the first epitaxial layer thus etched.

Abstract: A method and structure for reducing leakage currents in integrated circuits based on a direct silicon bonding (DSB) fabrication process. After recessing a top semiconductor layer and an underlying semiconductor substrate, a dielectric layer may be deposited and etched back to form embedded spacers. Conventional source/drain regions may then be formed.

Abstract: A double-gated fin-type field effect transistor (FinFET) structure has electrically isolated gates. In a method for manufacturing the FinFET structure, a fin, having a gate dielectric on each sidewall corresponding to the central channel region, is formed over a buried oxide (BOX) layer on a substrate. Independent first and second gate conductors on either sidewall of the fin are formed and include symmetric multiple layers of conductive material. An insulator is formed above the fin by either oxidizing conductive material deposited on the fin or by removing conductive material deposited on the fin and filling in the resulting space with an insulating material. An insulating layer is deposited over the gate conductors and the insulator. A first gate contact opening is etched in the insulating layer above the first gate. A second gate contact opening is etched in the BOX layer below the second gate.

Abstract: In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of the channel region. The channel region is oriented such that a current flow between the source/drain regions has a <100> direction through the channel region. Dielectric regions create a compressive stress on the channel region perpendicular to the current flow.

Abstract: The present invention relates to semiconductor-on-insulator (SOI) substrate structures that contain surface semiconductor regions of different crystal orientations located directly on an insulator layer. The present invention also relates to methods for fabricating such SOI substrate structures, by growing an insulator layer directly on a multi-orientation bulk semiconductor substrate that comprises surface semiconductor regions of different crystal orientations located directly on a semiconductor base layer, and removing the semiconductor base layer, thereby forming a multi-orientation SOI substrate structure that comprises surface semiconductor regions of different crystal orientations located directly on the insulator layer.

Abstract: When the CW laser is employed for annealing the semiconductor film, a device having a high characteristic can be expected. On the other hand, when the beam shaped to be elliptical is scanned on the semiconductor film, a proportion of excimer-like crystal grain region becomes large and this is a problem in point of high integration. The present invention is to make the excimer-like crystal grain region formed over the semiconductor film as small as possible. In the present invention, a fundamental wave having a wavelength of approximately 1 ?m is irradiated supplementarily to the semiconductor film, which is the irradiated surface, simultaneously with a harmonic emitted from a CW laser. In addition, the fundamental wave is irradiated with a large amount of energy to a region irradiated by the harmonic with a small amount of energy, and the fundamental wave is irradiated with a small amount of energy to a region irradiated by the harmonic with a large amount of energy.

Abstract: Disclosed is a producing method of a semiconductor device, including: loading a silicon substrate into a processing chamber, the silicon substrate having a silicon nitride film or a silicon oxide film on at least a portion of a surface thereof and a silicon surface being exposed from the surface; and alternately repeating a first introducing at least a silane-compound gas into the processing chamber and a second introducing at least etching gas a plurality of times to selectively grow an epitaxial film on the silicon surface, wherein the alternate repeating is started with the second introducing prior to the first introducing.

Abstract: Embodiments of the invention include apparatuses and methods relating to three dimensional transistors having high-k dielectrics and metal gates with fins protected by a hard mask layer on their top surface. In one embodiment, the hard mask layer includes an oxide.

Abstract: The present invention facilitates semiconductor device fabrication and performance by providing a semiconductor device that can improve channel mobility for both N type and P type transistor devices. The semiconductor device of the present invention is fabricated on a semiconductor substrate 802 that has a first and second crystallographic orientation axes (e.g., <110>, <100>) 804 and 806. Source to drain channel regions for P type devices are formed 904 and aligned along the first crystallographic orientation axis. Source to drain channel regions for N type devices are formed 906 rotated from the channel regions of the P type devices by an offset angle so that the source to drain channel regions for the N type devices are aligned with the second crystallographic orientation axis.

Abstract: The present invention facilitates semiconductor device fabrication and performance by providing a semiconductor device that can improve channel mobility for both N type and P type transistor devices. The semiconductor device of the present invention is fabricated on a semiconductor substrate 802 that has a first and second crystallographic orientation axes (e.g., <110>, <100>) 804 and 806. Source to drain channel regions for P type devices are formed 904 and aligned along the first crystallographic orientation axis. Source to drain channel regions for N type devices are formed 906 rotated from the channel regions of the P type devices by an offset angle so that the source to drain channel regions for the N type devices are aligned with the second crystallographic orientation axis.

Abstract: Semiconductor-on-diamond (SOD) substrates and methods for making such substrates are provided. In one aspect, a method of making an SOD substrate may include depositing a base layer onto a lattice-orienting silicon (Si) substrate such that the base layer lattice is substantially oriented by the Si substrate, depositing a semiconductor layer onto the base layer such that the semiconductor layer lattice is substantially oriented with respect to the base layer lattice, and disposing a layer of diamond onto the semiconductor layer. The base layer may include numerous materials, including, without limitation, aluminum phosphide (AlP), boron arsenide (BAs), gallium nitride (GaN), indium nitride (InN), and combinations thereof. Additionally, the method may further include removing the lattice-orienting Si substrate and the base layer from the semiconductor layer. In one aspect, the Si substrate may be of a single crystal orientation.

Abstract: Disclosed herein is a structure with two different type tri-gate MOSFETs formed on the same substrate. Each MOSFET comprises a fin with optimal mobility for the particular type of MOSFET. Due to the processes used to form fins with different crystalline orientations on the same substrate, one of the MOSFETs has a fin with a lower mobility top surface. To inhibit inversion of the top surface, this MOSFET has a gate dielectric layer with a thicker region on the top surface than it does on the opposing sidewall surfaces. Additionally, several techniques for forming the thicker region of the gate dielectric layer are also disclosed.

Abstract: Disclosed is an integrated circuit structure that has a substrate having at least two types of crystalline orientations. The first-type transistors are on first portions of the substrate that have a first type of crystalline orientation and second-type transistors are on second portions of the substrate that have a second type of crystalline orientation. The straining layer is above the first-type transistors and the second-type transistors. Further, the straining layer can be strained above the first-type transistors and relaxed above the second-type transistors.

Abstract: A method for fabricating a semiconductor structure having heterogeneous crystalline orientations by forming a region including a semiconductor material having a specified crystalline orientation using an epitaxial buffer overlying a semiconductor substrate. The buffer provides a transfer body such that the semiconductor material has a crystalline orientation that differs from the crystalline orientation of a semiconductor region underlying the buffer. The method also includes fabricating a semiconductor structure having a p-type device region and an n-type device region, where a supporting semiconductor substrate is either n-type or p-type and where the semiconductor material is separated from the substrate by a buffer and has a crystalline orientation that differs from the crystalline orientation of the substrate.

Abstract: Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.

Abstract: A mask for crystallization of amorphous silicon to polysilicon is provided. The mask includes a plurality of slit patterns for defining regions to be illuminated. The plurality of slit patterns are formed along a longitudinal first direction and the mask moves along a longitudinal second direction. The first longitudinal direction is substantially perpendicular to the second longitudinal direction. Each of the split patterns is deviated apart by substantially a same distance from another. Thus, the polysilicon using the mask.

Abstract: A hybrid substrate having a high-mobility surface for use with planar and/or multiple-gate metal oxide semiconductor field effect transistors (MOSFETs) is provided. The hybrid substrate has a first surface portion that is optimal for n-type devices, and a second surface portion that is optimal for p-type devices. Due to proper surface and wafer flat orientations in each semiconductor layers of the hybrid substrate, all gates of the devices are oriented in the same direction and all channels are located on the high mobility surface. The present invention also provides for a method of fabricating the hybrid substrate as well as a method of integrating at least one planar or multiple-gate MOSFET thereon.

Abstract: The present invention provides a semiconductor device and a method of manufacturing a semiconductor device in which a driving force can be increased by increasing a strain amount given by a stressed film in a MOS transistor including an elevated region. On a silicon substrate, a device isolation region 102, a gate insulating film 103, a gate electrode 104, an extension 105, and a sidewall insulating film 106 are formed. After that, an elevated region is formed, and a source/drain region 108 and a silicide layer 109 are formed. Subsequently, the sidewall insulating film 106 is etched to provide a gap from the elevated region 107, and a stressed film 110 is buried in the gap.

Abstract: A semiconductor device according to an embodiment includes: a semiconductor substrate; a fin formed on the semiconductor substrate; a gate electrode formed so as to sandwich both side faces of the fin between its opposite portions via a gate insulating film; an extension layer formed on a region of a side face of the fin, the region being on the both sides of the gate electrode, the extension layer having a plane faced to a surface of the semiconductor substrate at an acute angle; and a silicide layer formed on a surface of the plane faced to the surface of the semiconductor substrate at an acute angle.

Abstract: An organic semiconductor device includes a substrate, a gate electrode formed directly on the substrate , gate insulating film formed directly on the gate electrode, a source electrode and a drain electrode formed directly on the gate insulating film, an organic semiconductor layer formed directly on the source electrode and the drain electrode, and a voltage control layer disposed directly between the gate insulating film and the organic semiconductor layer and directly contacting the source electrode and the drain electrode, wherein the voltage control layer gives an ambipolar characteristic to the organic semiconductor layer.

Abstract: A semiconductor structure is provided that includes a hybrid orientated substrate having at least two coplanar surfaces of different surface crystal orientations, wherein one of the coplanar surfaces has bulk-like semiconductor properties and the other coplanar surface has semiconductor-on-insulator (SOI) properties. In accordance with the present invention, the substrate includes a new well design that provides a large capacitance from a retrograde well region of the second conductivity type to the substrate thereby providing noise decoupling with a low number of well contacts. The present invention also provides a method of fabricating such a semiconductor structure.

Abstract: A method for fabricating a transistor, the method includes forming a gate over a substrate to form a first resultant structure, forming a gate spacer at first and second sidewalls of the gate, etching portions of the substrate proximate to the gate spacer to form a recess in a source/drain region of the substrate, forming a first epitaxial layer including germanium to fill the recess, and performing a high temperature oxidation process to form a second epitaxial layer including germanium over an interfacial layer between the substrate and the first epitaxial layer, the second epitaxial layer having a germanium concentration that is higher than a germanium concentration of the first epitaxial SiGe layer, thereby forming a second resultant structure.

Abstract: Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low work function, is formed over a semiconductor substrate. Oxygen and/or nitrogen are then added to the metal carbide in a second region to establish a second work function in the second region, where the metal carbide itself establishes a first work function in a first region. One or more first metal gate transistor types are then formed in the first region and one or more second metal gate transistor types are formed in the second region.

Abstract: There is provided a method of manufacturing a semiconductor device. In one aspect, the method includes providing a strained silicon layer having a crystal orientation located over a semiconductor substrate having a different crystal orientation. A mask is placed over a portion of the strained silicon layer to leave an exposed portion of the strained silicon layer. The exposed portion of the strained silicon layer is amorphized and re-crystallized to a crystal structure having an orientation the same as the semiconductor substrate.

Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.

Abstract: A method of manufacturing an integrated circuit on semiconductor substrates, e.g., silicon wafer. The method includes providing a semiconductor substrate characterized by a first lattice with a first structure and a first spacing. In a specific embodiment, the semiconductor substrate has an overlying film of material with a second lattice with a second structure and a second spacing, the second spacing placing the film of material in a strain mode characterized by a first tensile and/or compressive mode along a single film surface crystal axis across a first portion of the film of material relative to the semiconductor substrate with the first structure and the first spacing. The method patterns a predetermined region of the first portion of the film of material to cause the first tensile and/or compressive mode in the first portion of the film of material to change to a second tensile and/or compressive mode in a resulting patterned portion of the first portion of the film of material.

Abstract: An electronic device can include a base layer, a semiconductor layer, and a first semiconductor fin spaced apart from and overlying a semiconductor layer. In a particular embodiment, a second semiconductor fin can include a portion of the semiconductor layer. In another aspect, a process of forming an electronic device can include providing a workpiece that includes a base layer, a first semiconductor layer that overlies and is spaced apart from a base layer, a second semiconductor layer that overlies, and an insulating layer lying between the first semiconductor layer and the second semiconductor layer. The process can also include removing a portion of the second semiconductor layer to form a first semiconductor fin, and forming a conductive member overlying the first semiconductor fin.