Abstract: In a method for forming a silicon-on-insulator FET providing a contact to be given a fixed potential to a substrate, the substrate-biasing between the SOI transistor and the silicon substrate is performed via the plug. As a result, the contact hole for the substrate-biasing does not need to pass through the insulating layer, the silicon layer, and the interlayer insulating layer. Therefore, the interlayer insulating layer can be make shallow the depth.

Abstract: A phase changeable memory cell that includes a substrate, a bottom electrode, a phase changeable material layer pattern, and a top electrode. The bottom electrode is on the substrate. The phase changeable material layer pattern is on the bottom electrode. The top electrode is on the phase changeable material layer pattern, and has a tip that extends toward the bottom electrode.

Abstract: A method of producing a strain-relaxed Si—Ge virtual substrate for use in a semiconductor substrate which is planar and of less defects for improving the performance of a field effect semiconductor device, which method comprises covering an Si—Ge layer formed on an SOI substrate with an insulating layer to prevent evaporation of Ge, heating the mixed layer of silicon and germanium at a temperature higher than a solidus curve temperature determined by the germanium content of the Si—Ge layer into a partially melting state, and diffusing germanium to the Si layer on the insulating layer, thereby solidifying the molten Si—Ge layer to obtain a strain-relaxed Si—Ge virtual substrate.

Abstract: A method of forming a substantially uniform oxide film over surfaces with different level of doping and/or different dopant type is disclosed. In one aspect, a method for forming a uniform oxide spacer on the sidewalls of heavily doped n- and p-type gates is disclosed. The method includes providing a semiconductor substrate having at least two regions with dissimilar dopant characteristics, optionally heating the substrate; and forming a uniform oxide layer over the at least two regions by exposing the substrate to a gaseous mixture including atomic oxygen.

Abstract: An MIS device (20) includes a semiconducting substrate (22), a silicon nitride buffer layer (24), a ferroelectric metal oxide superlattice material (26), and a noble metal top electrode (28). The layered superlattice material (26) is preferably a strontium bismuth tantalate, strontium bismuth niobate, or strontium bismuth niobium tantalate. The device is constructed according to a preferred method that includes forming the silicon nitride on the semiconducting substrate prior to deposition of the layered superlattice material. The layered superlattice material is preferably deposited using liquid polyoxyalkylated metal organic precursors that spontaneously generate a layered superlattice upon heating of the precursor solution. UV exposure during drying of the precursor liquid imparts a C-axis orientation to the final crystal, and results in improved thin-film electrical properties.

Abstract: Techniques for forming gate dielectric layers (702) overlying amorphous substrate materials are presented. In addition, techniques for low temperature processing operations that allow for the use of amorphous silicon in doping operations are presented. The amorphous silicon regions (604, 606) are formed prior to formation of structures included in the gate structure (804) of the semiconductor device, where the gate structures (804) are preferably formed using low temperature operations that allow the amorphous silicon regions (604, 606) to remain in an amorphous state. Source/drain regions (1004, 1006) are formed in the amorphous silicon regions (604, 606), and then the substrate is annealed to recrystallize the amorphous regions.

Abstract: The present invention relates generally to a method for forming a pattern and a semiconductor device, and in particular, to a method for forming a pattern for the formation of quantum dots or wires with (1)˜(50) nm dimension using the atomic array of a crystalline material and to the manufacture of functional devices that have such a structure.

Abstract: A method of forming a polysilicon layer includes the steps of: loading a semiconductor substrate in a CVD reactor wherein a gate insulating layer is formed on the substrate; decompressing the reactor; depositing a first polysilicon layer on the substrate by flowing an SiH4 gas into the reactor; forming a plurality of Si—N bonds on the first polysilicon layer by maintaining atmospheric pressure of the reactor by filling the reactor with nitrogen gas; decompressing the reactor; and depositing a second polysilicon layer on the first polysilicon layer by flowing SiH4 gas into the reactor.

Abstract: Process for pre-drying textile filaments after wet treatment and device for practicing this method The present invention has for its object a process for pre-drying textile filaments after wet treatment and a device for practicing this process.

Abstract: The present invention provides at least one nozzle that sprays a rotating workpiece with an etchant at an edge thereof.

Abstract: A strained Si CMOS structure is formed by steps which include forming a relaxed SiGe layer on a surface of a substrate; forming isolation regions and well implant regions in said relaxed SiGe layer; and forming a strained Si layer on said relaxed SiGe layer. These processing steps may be used in conjunction with conventional gate processing steps in forming a strained MOSFET structure.

Abstract: A method of making a semiconductor device and the device. The device, according to a first embodiment, is fabricated by providing a silicon (111) surface, forming on the surface a dielectric layer of crystalline silicon nitride and forming an electrode layer on the dielectric layer of silicon nitride. The silicon (111) surface is cleaned and made atomically flat. The dielectric layer if formed of crystalline silicon nitride by placing the surface in an ammonia ambient at a pressure of from about 1×10−7 to about 1×10−5 Torr at a temperature of from about 850° C. to about 1000° C. The electrode layer is heavily doped silicon. According to a second embodiment, there is provided a silicon (111) surface on which is formed a first dielectric layer of crystalline silicon nitride having a thickness of about 2 monolayers.

Abstract: Silicide films having a high heat-resistance are formed on a gate electrode, simultaneously with silicide films having good junction leakage characteristics on diffusion layers. A transistor includes a polycrystalline silicon gate electrode, a gate insulating film, a diffusion layer, and sidewalls on a silicon substrate isolated by an element isolation oxide film. A first silicide film and a second silicide film are formed on the gate electrode and on the diffusion layer, respectively. The first silicide film is thicker than the second silicide film.

Abstract: A method for forming an oxide of substantially uniform thickness on at least two crystallographic planes of silicon, in accordance with the present invention, includes providing a substrate where silicon surfaces have at least two different crystallographic orientations of the silicon crystal. Atomic oxygen (O) is formed for oxidizing the surfaces. An oxide is formed on the surfaces by reacting the atomic oxygen with the surfaces to simultaneously form a substantially uniform thickness of the oxide on the surfaces.

Abstract: A gate electrode structure of a semiconductor device and a manufacturing method thereof are provided. The gate electrode structure includes a first silicon layer pattern formed of a polycrystalline silicon layer and a second silicon layer pattern having surface roughness lower than that of the first silicon layer pattern formed on the first silicon layer pattern.

Abstract: A probe of a scanning probe microscope (SPM) having a field-effect transistor (FET) structure at the tip of the probe, and a method of fabricating the probe are provided. The SPM prove having a source, channel and drain is formed by etching a single crystalline silicon substrate into a V-shaped groove and doping the etching sloping sides at one end of the V-shaped groove with impurities.

Abstract: An MOS-type semiconductor device comprises two semiconductors separated by an insulator. The two semiconductors comprise monocrystal semiconductors, each having a crystallographic orientation with respect to the insulator (or other crystallographic/semiconductor property) different to the crystallographic orientation (or other respective property) of the other semiconductor. This arrangement of crystallographic orientations (and other crystallographic/semiconductor properties) can yield reduced unintended electron tunneling or current leakage through the insulator vis à vis a semiconductor device in which such an arrangement is not used. Methods for forming the MOS-type semiconductor devices of the invention are also provided.

Abstract: Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. Embodiments of a method of forming an integrated circuit include forming a trench in a silicon wafer. A trench wall of the trench has a (110) crystal plane orientation. A semiconductor device is also formed lateral to the trench wall such that the semiconductor device is capable of conducting an electrical current in a <110> direction. One method of the present invention provides for forming an integrated circuit.

Abstract: A method of making a semiconductor device and the device. The device, according to a first embodiment, is fabricated by providing a silicon (111) surface, forming on the surface a dielectric layer of crystalline silicon nitride and forming an electrode layer on the dielectric layer of silicon nitride. The silicon (111) surface is cleaned and made atomically flat. The dielectric layer if formed of crystalline silicon nitride by placing the surface in an ammonia ambient at a pressure of from about 1×10−7 to about 1×10−5 Torr at a temperature of from about 850° C. to about 1000° C. The electrode layer is heavily doped silicon. According to a second embodiment, there is provided a silicon (111) surface on which is formed a first dielectric layer of crystalline silicon nitride having a thickness of about 2 monolayers.

Abstract: Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. Embodiments of a method of forming an integrated circuit include forming a trench in a silicon wafer. A trench wall of the trench has a (110) crystal plane orientation. A semiconductor device is also formed lateral to the trench wall such that the semiconductor device is capable of conducting an electrical current in a <110> direction. One method of the present invention provides for forming an integrated circuit.

Abstract: An electrode material layer of a WSi.sub.2 /polysilicon lamination layer and a conductive material layer for antireflection made of TiN or TiON and containing the direction <200> are sequentially deposited on a gate insulating film. The conductive material layer is patterned through dry etching using a resist layer as a mask to leave a portion of the conductive material layer. The resist layer may be as thin as capable of patterning the conductive material layer. After the resist layer is removed, the electrode material layer is patterned through dry etching using the conductive material layer as a mask to leave a portion of the electrode material layer. A lamination of the left electrode material layer and conductive material layer is used as a gate electrode layer. A lamination of the resist layer and conductive material layer may be used as a mask.

Abstract: A method of increasing the performance of an FET device by aligning the channel of the FET with the [110] crystal direction of a {100} silicon wafer. The {100} silicon wafer and the image of a lithographic mask are rotated 45.degree. relative to each other so that, instead of the channel being aligned parallel with the [100] crystal direction in the conventional fabrication, the channel is aligned approximately parallel with the [110] crystal direction. The mobility of the carriers is higher in the [110] crystal direction thereby increasing the performance of the FET with only a minor modification in the lithographic process. The novel FET results with its channel aligned approximately parallel with the [110] crystal direction.

Abstract: A semiconductor device, which has an oxide laver with the thickness thereof being varied from portion to portion of the inner surface of a trench and can be easily produced, and a process of producing the same. An n.sup.+ type single crystal SiC substrate is formed of SiC of hexagonal system having a carbon face with a (0001) face orientation as a surface, and an n type epitaxial layer and a p type epitaxial layer are successively laminated onto the substrate. An n.sup.+ source region is provided within the p type epitaxial layer, and the trench extends through the source region and the epitaxial layer into the semiconductor substrate. The side face of the trench is almost perpendicular to the surface of the epitaxial layer with the bottom face of the trench having a plane parallel to the surface of the epitaxial layer. The thickness of a gate oxide layer, formed by thermal oxidation, on the bottom face of the trench is larger than the thickness of the gate oxide layer on the side face of the trench.

Abstract: Disclosed is a method for making a superconducting field-effect device with a grain boundary channel, the method comprising the steps of depositing a first superconducting thin film on a substrate; patterning the first superconducting thin film to form a patterned superconducting thin film having an opening; depositing a template layer thereon; selectively etching back the template layer to form a patterned template layer; growing a second superconducting thin film to form a grain boundary therebetween; depositing an insulating layer on the second superconducting thin film to protect the second superconducting thin film from degrading in property in the air; selectively etching back the insulating layer to form a patterned insulating layer; forming a gate insulating layer on the patterned insulating layer; and coating metal electrodes thereon, source/drain being formed respectively on the etched portions, and a gate electrode being formed on the deposited portion of the gate insulating layer directly above th