Including Passive Device (e.g., Resistor, Capacitor, Etc.) Patents (Class 438/210)
  • Patent number: 10431738
    Abstract: An integrated fan-out package including an integrated circuit, a plurality of memory devices, an insulating encapsulation, and a redistribution circuit structure is provided. The memory devices are electrically connected to the integrated circuit. The integrated circuit and the memory devices are stacked, and the memory devices are embedded in the insulating encapsulation. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the integrated circuit and the memory devices. Furthermore, methods for fabricating the integrated fan-out package are also provided.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: October 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee
  • Patent number: 10141395
    Abstract: A metal-insulator-metal (MIM) capacitor, includes a cross-sectional view: a first metal plate; a second metal plate; a third metal plate; and a layer of high-k material contacting the first metal plate, the second metal plate, and the third metal plate.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: November 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Chih-Chao Yang
  • Patent number: 10032771
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a first capacitor with a first gate overlying a first gate dielectric that in turn overlies a first channel. a second capacitor includes a second gate overlying a second gate dielectric that in turn overlies a second channel. The second gate dielectric has a different composition than the first gate dielectric. A capacitor interconnect is in electrical communication with the first capacitor and with the second capacitor.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: July 24, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yuan Sun, Shyue Seng Tan, Kiok Boone Elgin Quek
  • Patent number: 9865510
    Abstract: A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: January 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Po-Nien Chen, Bao-Ru Young, Harry-Hak-Lay Chuang, Jin-Aun Ng, Ming Zhu
  • Patent number: 9799609
    Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: October 24, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Masami Koketsu, Toshiaki Sawada
  • Patent number: 9773808
    Abstract: This disclosure is directed to techniques for fabricating CMOS devices for SRAM cells with resistors formed along transistor well sidewall edges by self-aligned, angled implantation, which may enable more compact SRAM architecture with SEU mitigation, such as for space-based or other radiation-hardened applications. An example method includes implanting a dopant into a doped semiconductor well covered by a barrier, wherein the doped semiconductor well is disposed on a buried insulator and wherein the dopant is of opposite doping type to the doped semiconductor well, thereby forming a resistor on an edge of the doped semiconductor well, wherein the resistor has the opposite doping type. The method further includes forming a second insulator adjacent to the resistor, removing the barrier, and forming agate layer on the doped semiconductor well, thereby forming a gate adjacent to the doped semiconductor well and the resistor.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: September 26, 2017
    Assignee: Honeywell International Inc.
    Inventor: Paul S. Fechner
  • Patent number: 9768176
    Abstract: A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation film; a gate electrode filled in the active region; a bit line contact structure coupled to an active region between the gate electrodes; and a line-type bit line electrode formed over the bitline contact structure. The bit line contact structure includes a bit line contact formed over the active region; and an ohmic contact layer formed over the bit line contact.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: September 19, 2017
    Assignee: SK HYNIX INC.
    Inventor: Min Soo Yoo
  • Patent number: 9443726
    Abstract: A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface. A shrinkable layer is formed to cover the dielectric layer, where the shrinkable layer has a second top surface. A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: September 13, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Ju Li, Po-Cheng Huang, Yu-Ting Li, Jen-Chieh Lin, Chih-Hsun Lin, Tzu-Hsiang Hung, Wu-Sian Sie, I-Lun Hung, Wen-Chin Lin, Chun-Tsen Lu
  • Patent number: 9324655
    Abstract: An electronic fuse structure including an Mx level including a first Mx metal, a second Mx metal, and an Mx cap dielectric above of the first and second Mx metal, an Mx+1 level above the Mx level, the Mx+1 level including an Mx+1 metal and a via electrically connecting the Mx metal to the Mx+1 metal in a vertical orientation, and a nano-pillar located within the via and above the second Mx metal.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: April 26, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig, Andrew H. Simon
  • Patent number: 9252250
    Abstract: An embodiment integrated circuit device and a method of making the same. The embodiment integrated circuit includes a substrate supporting a source with a first doping type and a drain with a second doping type on opposing sides of a channel region in the substrate, and a pocket disposed in the channel region, the pocket having the second doping type and spaced apart from the drain between about 2 nm and about 15 nm. In an embodiment, the pocket has a depth of between about 1 nanometer to about 30 nanometers.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: February 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ying Zhang
  • Patent number: 9190277
    Abstract: An integrated circuit containing a PMOS transistor may be formed by implanting boron in the p-channel source drain (PSD) implant step at a dose consistent with effective channel length control, annealing the PSD implant, and subsequently concurrently implanting boron into a polysilicon resistor with a zero temperature coefficient of resistance using an implant mask which also exposes the PMOS transistor, followed by a millisecond anneal.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: November 17, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Mahalingam Nandakumar
  • Patent number: 9111756
    Abstract: Methods and apparatus are provided for an integrated circuit with a transistor and a resistor. The method includes depositing a first dielectric layer over the transistor and the resistor, followed by an amorphous silicon layer. The amorphous silicon layer is implanted over the resistor to produce an etch mask, and the amorphous silicon layer and first dielectric layer are removed over the transistor. A contact location on the transistor is then silicided.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: August 18, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Joachim Patzer, Hans-Peter Moll
  • Patent number: 9105601
    Abstract: Disclosed herein is a power module package including: a substrate including a metal layer, a first insulation layer formed on the metal layer, a first circuit pattern formed on the first insulation layer and including a first pad and a second pad spaced apart from the first pad, a second insulation layer formed on the first insulation layer to cover the first circuit pattern, and a second circuit pattern formed on the second insulation layer and including a third pad formed on a location corresponding to the first pad and a fourth pad spaced apart from the third pad; a semiconductor chip mounted on the second circuit pattern; one end being electrically connected to the semiconductor chip, and another end protruding from the outside, wherein the first pad and the third pad, and the second pad and the fourth pad have different polarities.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: August 11, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Tae Hyun Kim, Do Jae Yoo, Bum Seok Suh
  • Patent number: 9076670
    Abstract: In an integrated circuit that includes an NMOS logic transistor, an NMOS SRAM transistor, and a resistor, the gate of the SRAM transistor is doped at the same time that the resistor is doped, thereby allowing the gate of the logic transistor to be separately doped without requiring any additional masking steps.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: July 7, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Himadri Sekhar Pal, Ebenezer Eshun, Shashank S. Ekbote
  • Patent number: 9070569
    Abstract: A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: June 30, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Cheol Lee, Chi-Sung Oh, Jin-Kuk Kim
  • Publication number: 20150132902
    Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.
    Type: Application
    Filed: November 17, 2014
    Publication date: May 14, 2015
    Inventors: Harry-Hak-Lay Chuang, Kong-Beng Thei, Sheng-Chen Chung, Chiung-Han Yeh, Lee-Wee Teo, Yu-Ying Hsu, Bao-Ru Young
  • Patent number: 9029982
    Abstract: A semiconductor device includes a semiconductor substrate, and a multilayer wiring layer provided over the semiconductor substrate. The multilayer wiring layer includes an inductor wiring formed in one wiring layer, a plurality of first dummy metals formed in the same layer as the inductor and provided inside the inductor, a plurality of second dummy metals formed in a same layer as the inductor and provided outside the inductor, a plurality of third dummy metals formed in a layer lower than the one wiring layer including the inductor, and provided inside the inductor in a plan view, a plurality of fourth dummy metals formed in a same layer as the plurality of third dummy metals and provided outside the inductor in the plan view, and a plurality of fifth dummy metals formed in the same layer as the plurality of third dummy metals and provided to overlap with the inductor.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: May 12, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Shinichi Uchida
  • Patent number: 9029180
    Abstract: A method of producing a temperature sensing device is provided. The method includes forming at least one silicon layer and at least one electrode or contact to define a thermistor structure. At least the silicon layer is formed by printing, and at least one of the silicon layer and the electrode or contact is supported by a substrate during printing thereof. Preferably, the electrodes or contacts are formed by printing, using an ink comprising silicon particles having a size in the range 10 nanometers to 100 micrometers, and a liquid vehicle composed of a binder and a suitable solvent. In some embodiments the substrate is an object the temperature of which is to be measured. Instead, the substrate may be a template, may be sacrificial, or may be a flexible or rigid material. Various device geometries are disclosed.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: May 12, 2015
    Assignee: PST Sensors (Proprietary) Limited
    Inventors: David Thomas Britton, Margit Harting
  • Patent number: 9018060
    Abstract: A variable capacitance sensor includes a first conductive electrode comprising electrically interconnected first conductive sheets; a second conductive electrode comprising electrically interconnected second conductive sheets, wherein the first conductive sheets are at least partially interleaved with the second conductive sheets, and wherein the second conductive electrode is electrically insulated from the first conductive electrode; and microporous dielectric material at least partially disposed between and contacting the first conductive sheets and the second conductive sheets. A method of making a variable capacitance sensor by replacing ceramic in a ceramic capacitor with a microporous material is also disclosed.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: April 28, 2015
    Assignee: 3M Innovative Properties Company
    Inventors: Stefan H. Gryska, Michael C. Palazzotto
  • Patent number: 9006703
    Abstract: Aspects of the present invention relate to method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof. Various embodiments include a method for reducing lateral extrusion formed in semiconductor structures. The method can include removing a portion of a first lateral extrusion in an aluminum layer of the semiconductor structure, and determining a post-removal thickness of a dielectric layer positioned adjacent the aluminum layer. The post-removal thickness may be determined subsequent to the removing of the portion of the first lateral extrusion. The method can also include determining a difference between the post-removal thickness of the dielectric layer and a pre-removal thickness of the dielectric layer.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Shawn A. Adderly, Brian M. Czabaj, Daniel A. Delibac, Jeffrey P. Gambino, Matthew D. Moon, David C. Thomas
  • Patent number: 8994086
    Abstract: The invention provides a semiconductor device which is non-volatile, easily manufactured, and can be additionally written. A semiconductor device of the invention includes a plurality of transistors, a conductive layer which functions as a source wiring or a drain wiring of the transistors, and a memory element which overlaps one of the plurality of transistors, and a conductive layer which functions as an antenna. The memory element includes a first conductive layer, an organic compound layer and a phase change layer, and a second conductive layer stacked in this order. The conductive layer which functions as an antenna and a conductive layer which functions as a source wiring or a drain wiring of the plurality of transistors are provided on the same layer.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroko Abe, Yukie Nemoto, Ryoji Nomura, Mikio Yukawa
  • Patent number: 8962422
    Abstract: A method of fabricating a semiconductor device includes etching a substrate to form a field trench defining an active region and a lower gate pattern on the active region, the lower gate pattern including a tunneling insulating pattern and a lower gate electrode pattern, filling a field insulating material in the field trench to form a field region, forming an upper gate pattern on the lower gate pattern, sequentially forming a stopping layer and a buffer layer on the field region and the upper gate pattern, forming a first resistive pattern on the buffer layer of the field region, and forming a second resistive pattern on the buffer layer on the upper gate pattern, forming an interlayer insulating layer covering the first and second resistive patterns, and performing a planarization process to remove a top surface of the interlayer insulating layer and to remove the second resistive pattern.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jun Seong, Jae-Hwang Sim
  • Patent number: 8963224
    Abstract: Provided is a semiconductor device including, on the same semiconductor substrate, a transistor element, a capacitor, and a resistor. The capacitor is formed on an active region, and the resistor is formed on an element isolation region, both formed of the same polysilicon film. By CMP or etch-back, the surface is ground down while planarizing the surface until a resistor has a desired thickness. Owing to a difference in height between the active region and the element isolation region, a thin resistor and a thick upper electrode of the capacitor are formed to prevent passing through of a contact.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: February 24, 2015
    Assignee: Seiko Instruments Inc.
    Inventors: Ayako Inoue, Kazuhiro Tsumura
  • Patent number: 8940598
    Abstract: A method for adding a low TCR resistor to a baseline CMOS manufacturing flow. A method of forming a low TCR resistor in a CMOS manufacturing flow. A method of forming an n-type and a p-type transistor with a low TCR resistor in a CMOS manufacturing flow.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: January 27, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Greg Charles Baldwin, Kamel Benaissa, Sarah Liu, Song Zhao
  • Patent number: 8940612
    Abstract: An integrated circuit containing a metal gate transistor and a thin polysilicon resistor may be formed by forming a first layer of polysilicon and removed it in an area for the thin polysilicon resistor. A second layer of polysilicon is formed over the first layer of polysilicon and in the area for the thin polysilicon resistor. The thin polysilicon resistor is formed in the second layer of polysilicon and the sacrificial gate is formed in the first layer of polysilicon and the second layer of polysilicon. A PMD layer is formed over the second layer of polysilicon and a top portion of the PMD layer is removed so as to expose the sacrificial gate but not expose the second layer of polysilicon in the thin polysilicon resistor. The sacrificial gate is removed and a metal replacement gate is formed.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: January 27, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Kamel Benaissa
  • Patent number: 8936982
    Abstract: A method for fabricating a semiconductor device includes etching a semiconductor substrate to form bulb-type trenches that define a plurality of active regions in the semiconductor substrate; forming a supporter in each of the bulb-type trenches; dividing each active region, of the plurality of active regions, into a pair of body lines by forming a trench through each active region; and forming a bit line in each body line of the pair of body lines.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: January 20, 2015
    Assignee: SK hynix Inc.
    Inventors: Heung-Jae Cho, Eui-Seong Hwang, Eun-Shil Park
  • Patent number: 8933499
    Abstract: In some embodiments, a circuit element includes a first FET and a first storage capacitor. The first FET includes a gate stack, a first source or drain region, a second source or drain region and a body structure. The gate stack is configured over the body structure. The first source or drain region and the second source or drain region are configured on opposite sides of the gate stack. The first storage capacitor includes an anode and a cathode. The first source or drain region is coupled to the anode of the first storage capacitor non-selectively, and does not have stressor material with a lattice constant different from that of a channel region in the body structure. The second source or drain structure is coupled to the anode of the first storage capacitor selectively, and has the stressor material.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: January 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventor: Chih-Yang Chang
  • Patent number: 8927406
    Abstract: A method for fabricating a dual damascene metal gate includes forming a dummy gate onto a substrate, disposing a protective layer on the substrate and the dummy gate, and growing an expanding layer on sides of the dummy gate. The method further includes removing the protective layer, forming a spacer around the dummy gate, and depositing and planarizing a dielectric layer. The method further includes selectively removing the expanding layer, and removing the dummy gate.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Wang, Wen-Chu Hsiao, Ying-Min Chou, Hsiang-Hsiang Ko
  • Patent number: 8927328
    Abstract: A 3D semiconductor device and a method of manufacturing the same are provided. The method includes forming a first semiconductor layer including a common source node on a semiconductor substrate, forming a transistor region on the first semiconductor layer, wherein the transistor region includes a horizontal channel region substantially parallel to a surface of the semiconductor substrate, and source and drain regions branched from the horizontal channel region to a direction substantially perpendicular to the surface of the semiconductor substrate, processing the first semiconductor layer to locate the common source node corresponding to the source region, forming a gate in a space between the source region and the drain region, forming heating electrodes on the source region and the drain region, and forming resistance variable material layers on the exposed heating electrodes.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: January 6, 2015
    Assignee: SK Hynix Inc.
    Inventor: Suk Ki Kim
  • Patent number: 8916426
    Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: William F. Clark, Jr., Robert J. Gauthier, Jr., Terence B. Hook, Junjun Li, Theodorus E. Standaert, Thomas A. Wallner
  • Patent number: 8916436
    Abstract: A method for producing an integrated device including an MIM capacitor. The method includes the steps of providing a functional substrate including functional circuits of the integrated device, forming a first conductive layer including a first plate of the capacitor on the functional substrate; the first plate has a first melting temperature. The method further includes depositing a layer of insulating material including a dielectric layer of the capacitor on a portion of the first conductive layer corresponding to the first plate; the layer of insulating material is deposited at a process temperature being lower than the first melting temperature. The method further includes forming a second conductive layer including a second plate of the capacitor on a portion of the layer of insulating material corresponding to the dielectric layer. In the solution according to an embodiment of the invention, the first melting temperature is higher than 500° C.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: December 23, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alessandro Dundulachi, Antonio Molfese
  • Publication number: 20140370671
    Abstract: An electrical fuse has an anode contact on a surface of a semiconductor substrate. The electrical fuse has a cathode contact on the surface of the semiconductor substrate spaced from the anode contact. The electrical fuse has a link within the substrate electrically interconnecting the anode contact and the cathode contact. The link comprises a semiconductor layer and a silicide layer. The silicide layer extends beyond the anode contact. An opposite end of the silicide layer extends beyond the cathode contact. A silicon germanium region is embedded in the semiconductor layer under the silicide layer, between the anode contact and the cathode contact.
    Type: Application
    Filed: August 7, 2014
    Publication date: December 18, 2014
    Inventors: Yan Zun Li, Zhengwen Li, Chengwen Pei, Jian Yu
  • Patent number: 8883606
    Abstract: In accordance with the teachings described herein, a multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same are provided. The multi-level thin film capacitor (MLC) may include at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material. A buffer layer may be included between the ceramic substrate and the thin film MLC. The buffer layer may have a smooth surface with a surface roughness (Ra) less than or equal to 0.08 micrometers (um).
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: November 11, 2014
    Assignee: BlackBerry Limited
    Inventors: Ivoyl P. Koutsaroff, Mark Vandermeulen, Andrew Vladimir Claude Cervin, Atin J. Patel
  • Publication number: 20140319592
    Abstract: Implementations disclosed herein may relate to a memory cell, such as a DRAM memory cell, for example.
    Type: Application
    Filed: April 26, 2013
    Publication date: October 30, 2014
    Inventor: AP Memory Corporation, USA
  • Patent number: 8871603
    Abstract: The invention relates to a semiconductor device and a method of manufacturing an electronic device. A first conductive layer (first metal interconnect layer) is deposited. There is an insulating layer (first intermetal dielectric) layer deposited. A resistive layer is deposited on top of the insulating layer and structured in order to serve as a thin film resistor. A second insulating layer (second intermetal dielectric) is then deposited on top of the resistive layer. A first opening is etched into the insulating layers (first and second intermetal dielectric) down to the first conductive layer. A second opening is etched into the insulating layers (first and second intermetal dielectrics) down to the first conductive layer. A cross-sectional plane of the second opening is arranged such that it at least partially overlaps the resistive layer of the thin film resistor in a first direction.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: October 28, 2014
    Assignees: Texas Instruments Deutschland GmbH, Texas Instruments Incorporated
    Inventors: Christoph Andreas Othmar Dirnecker, Leif Christian Olsen
  • Patent number: 8859383
    Abstract: A semiconductor device having a dielectric layer with improved electrical characteristics and associated methods, the semiconductor device including a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate and an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: October 14, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youn-soo Kim, Jae-hyoung Choi, Kyu-ho Cho, Wan-don Kim, Jae-soon Lim, Sang-yeol Kang
  • Patent number: 8853046
    Abstract: A single TiON film is used to form a ReRAM device by varying the oxygen and nitrogen content throughout the device to form the electrodes and switching layer. A ReRAM device that can be formed in a single deposition chamber is also disclosed. The ReRAM device can be formed by forming a first titanium nitride layer, forming a titanium oxynitride-titanium oxide-titanium oxynitride layer, and then forming a second titanium nitride.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: October 7, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Nan Lu, Chien-Lan Hsueh
  • Patent number: 8815695
    Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. A second electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the second electrode layer contains a conductive base layer and conductive metal oxide layer. In some embodiments, both the first electrode layer and the second electrode layer contain a conductive base layer and conductive metal oxide layer.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: August 26, 2014
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Xiangxin Rui, Mitsuhiro Horikawa, Hiroyuki Ode, Karthik Ramani
  • Patent number: 8809996
    Abstract: An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Der-Chyang Yeh, Li-Hsien Huang
  • Patent number: 8809108
    Abstract: Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly contacting the first and second electrodes. Forming the memory element can include forming a programmable portion of the memory element isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element. Other embodiments are described.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: August 19, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 8796782
    Abstract: A polysilicon film that serves as a resistance element is formed. The polysilicon film is patterned to a predetermined shape. CVD oxide films covering the patterned polysilicon film are etched thereby removing the portion of the CVD oxide film where the contact region is formed, leaving the portion covering the portion of the polysilicon film that serves as the resistor main body. BF2 is implanted by using the portions of the remaining CVD oxide films covering the polysilicon film as an implantation mask thereby forming a high concentration region in the contact region.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: August 5, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Takayuki Igarashi
  • Patent number: 8796087
    Abstract: A semiconductor device including a substrate; a bottom electrode on the substrate; a first dielectric layer on the bottom electrode, the first dielectric layer including a first metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb; a second dielectric layer on the first dielectric layer, the second dielectric layer including a second metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb, wherein the first metal oxide and the second metal oxide are different materials; a third dielectric layer on the second dielectric layer, the third dielectric layer including a metal carbon oxynitride; and an upper electrode on the third dielectric layer.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: August 5, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Weon-Hong Kim, Min-Woo Song, Jung-Min Park
  • Patent number: 8791566
    Abstract: The present invention provides an aluminum nitride substrate and an aluminum nitride circuit board having excellent insulation characteristics and heat dissipation properties and having high strength, a semiconductor apparatus, and a method for manufacturing an aluminum nitride substrate.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: July 29, 2014
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Materials Co., Ltd.
    Inventors: Haruhiko Yamaguchi, Yoshiyuki Fukuda
  • Patent number: 8786025
    Abstract: A system and method for forming a resistor system is provided. An embodiment comprises a resistor formed in a U-shape. The resistor may comprise multiple layers of conductive materials, with a dielectric layer filling the remainder of the U-shape. The resistor may be integrated with a dual metal gate manufacturing process or may be integrated with multiple types of resistors.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: July 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Yao Lai, Chun-Yi Lee, Shyh-Wei Wang, Yen-Ming Chen
  • Patent number: 8772905
    Abstract: A semiconductor device structure and method to form the same. The semiconductor device structure includes a non-volatile charge trap memory device and a resistor or capacitor. A dielectric layer of a charge trap dielectric stack of the memory device is patterned to expose a portion of a first conductive layer peripheral to the memory device. A second conductive layer formed over the dielectric layer and on the exposed portion of the first conductive layer is patterned to form resistor or capacitor contacts and capacitor plates.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Umberto M. Meotto, Paolo Tessariol
  • Patent number: 8766410
    Abstract: Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Josephine Chang, Leland Chang, Brian L. Ji, Steven John Koester, Amlan Majumdar
  • Patent number: 8748256
    Abstract: A method for forming an integrated circuit (IC) including a silicide block poly resistor (SIBLK poly resistor) includes forming a dielectric isolation region in a top semiconductor surface of a substrate. A polysilicon layer is formed including patterned resistor polysilicon on the dielectric isolation region and gate polysilicon on the top semiconductor surface. Implanting is performed using a first shared metal-oxide-semiconductor (MOS)/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon and gate polysilicon of a MOS transistor with at least a first dopant. Implanting is then performed using a second shared MOS/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon, gate polysilicon and source and drain regions of the MOS transistor with at least a second dopant. A metal silicide is formed on a first and second portion of a top surface of the patterned resistor polysilicon to form the SIBLK poly resistor.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: June 10, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Song Zhao, Gregory Charles Baldwin, Shashank S. Ekbote, Youn Sung Choi
  • Patent number: 8748988
    Abstract: A semiconductor device has a semiconductor substrate, a field insulating film disposed on a surface of the semiconductor substrate, a base insulating film disposed on a surface of the field insulating film, and a resistor disposed on the base insulating film. The resistor is formed of a polycrystalline silicon film and has a resistance region and electrode lead-out regions disposed at both ends of the resistance region. A portion of the base insulating film below the resistance region projects with respect to portions of the base insulating film below the electrode lead-out regions so that a height difference occurs therebetween. The resistance region has a thickness thinner than that of each of the electrode lead-out regions.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: June 10, 2014
    Assignee: Seiko Instruments Inc.
    Inventor: Yuichiro Kitajima
  • Patent number: 8723157
    Abstract: A non-volatile semiconductor storage device includes memory cells, each of which is arranged at an intersection between a first wiring and a second wiring intersecting each other. Each of the memory cells includes: a first electrode layer; a plurality of variable resistance layers laminated on the first electrode layer and functioning as variable resistance elements; a second electrode layer formed between the variable resistance layers; and a third electrode layer formed on the top one of the variable resistance layers. Each of the variable resistance layers is composed of a material containing carbon.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: May 13, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiko Yamamoto, Yasuyuki Baba, Takuya Konno
  • Patent number: 8716081
    Abstract: A method and structure for a memory device, such as a 1T-SRAM, having a capacitor top plate directly over a doped bottom plate region. An example device comprises the following. An isolation film formed as to surround an active area on a substrate. A gate dielectric and gate electrode formed over a portion of the active area. A source element and a drain element in the substrate adjacent to the gate electrode. The drain element is comprised of a drain region and a bottom plate region. The drain region is between the bottom plate region and the gate structure. A capacitor dielectric and a capacitor top plate are over at least portions of the bottom plate region.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: May 6, 2014
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Lee Wee Teo, Yong Meng Lee, Zhao Lun, Chung Woh Lai, Shyue Seng Tan, Jeffrey Chee, Shailendra Mishra, Johnny Widodo