And Additional Electrical Device Patents (Class 438/200)
  • Patent number: 10854280
    Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. While activated, the read assist transistor may generate an adaptive underdrive on the wordline, the level of which depends on the process, temperature and voltage of operation of the memory, when the wordline is selected and driven by the wordline driver.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: December 1, 2020
    Assignee: Arm Limited
    Inventors: Abhairaj Singh, Vivek Asthana, Monu Rathore, Ankur Goel, Nikhil Kaushik, Rachit Ahuja, Rahul Mathur, Bikas Maiti, Yew Keong Chong
  • Patent number: 10840094
    Abstract: There is provided a technique that includes: (a) forming a silicon germanium film in an amorphous state so as to embed an inside of a recess formed on a surface of a substrate, by supplying a first silicon-containing gas and a germanium-containing gas to the substrate at a first temperature; (b) raising a temperature of the substrate from the first temperature to a second temperature, which is higher than the first temperature; and (c) forming a silicon film on the silicon germanium film by supplying a second silicon-containing gas to the substrate at the second temperature, wherein in (c), the silicon germanium film as a base of the silicon film is crystallized while the silicon film is formed.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: November 17, 2020
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Kiyohiko Maeda, Masato Terasaki, Yasuhiro Megawa, Takahiro Miyakura, Akito Hirano, Takashi Nakagawa
  • Patent number: 10825847
    Abstract: A solid-state imaging element includes a plurality of shallow light receivers that are arrayed two-dimensionally in the vicinity of the surface of a semiconductor substrate and a plurality of deep light receivers that are arrayed two-dimensionally below the shallow light receivers. The shallow light receivers include visible light image light receivers that photoelectrically convert visible light and infrared light and output signals, and infrared light receivers that photoelectrically convert the infrared light. The infrared light receivers include a first infrared light receiver that is used to correct the signals output from the visible light image light receivers to provide signals of visible light components in the visible light image light receivers and a second infrared light receiver that is connected to the deep light receivers to form a multilayer light receiver.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: November 3, 2020
    Assignee: Tower Partners Semiconductor Co., Ltd.
    Inventors: Katsuya Furukawa, Masahiro Oda
  • Patent number: 10804116
    Abstract: An electronics package includes an insulating substrate, an electrical component having a back surface coupled to a first surface of the insulating substrate, and an insulating structure surrounding at least a portion of a perimeter of the electrical component. A first wiring layer extends from the first surface of the insulating substrate and over a sloped side surface of the insulating structure to electrically couple with at least one contact pad on an active surface of the electrical component. A second wiring layer is formed on a second surface of the insulating substrate and extends through at least one via therein to electrically couple with the first wiring layer.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: October 13, 2020
    Assignee: General Electric Company
    Inventors: Christopher James Kapusta, Raymond Albert Fillion, Risto Ilkka Sakari Tuominen, Kaustubh Ravindra Nagarkar
  • Patent number: 10797048
    Abstract: In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first side wall spacers is different from a second depth of the first space above the first gate electrode layer.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiang-Ku Shen, Chih Wei Lu, Janet Chen, Jeng-Ya David Yeh
  • Patent number: 10784411
    Abstract: An optoelectronic component includes an optoelectronic semiconductor chip that emits electromagnetic radiation, arranged in a housing, wherein the housing has an outer wall face and an exit face transparent to the electromagnetic radiation, the exit face is set back relative to the outer wall face in a direction of an interior of the housing, the optoelectronic semiconductor chip is arranged such that radiation emitted by the optoelectronic semiconductor chip in an emission direction can emerge from the optoelectronic component through the exit face, and the outer wall face has separating marks and the exit face is free of separating marks.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: September 22, 2020
    Assignee: OSRAM OLED GmbH
    Inventors: Andreas Wojcik, Martin Haushalter
  • Patent number: 10756099
    Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a substrate, a plurality of first gate structures, a first dielectric layer, a second dielectric layer, a third dielectric layer and a contact plug. The first gate structures are formed on an array region of the substrate. The first dielectric layer is formed on top surfaces and sidewalls of the first gate structures. The second dielectric layer is formed on the first dielectric layer and in direct contact with the first dielectric layer. The second dielectric layer and the first dielectric layer are made of the same material. The third dielectric layer is formed between the first gate structures and defines a plurality of contact holes exposing the substrate. The contact plug fills the contact holes.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: August 25, 2020
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Shu-Ming Lee, Tzu-Ming Ou Yang, Meng-Chang Chan
  • Patent number: 10756113
    Abstract: Embodiments of a semiconductor memory device include a substrate having a first region with peripheral devices, a second region with one or more memory arrays, and a third region between the first and the second regions. The semiconductor memory device also includes a protective structure for peripheral devices. The protective structure for peripheral devices of the semiconductor memory device includes a first dielectric layer and a barrier layer disposed on the first dielectric layer. The protective structure for peripheral devices of the semiconductor memory device further includes a dielectric spacer formed on a sidewall of the barrier layer and a sidewall of the first dielectric layer, wherein the protective structure is disposed over the first region and at least a portion of the third region.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: August 25, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zongliang Huo, Wenbin Zhou, Zhiguo Zhao, Zhaoyun Tang, Hai Lin Xiong
  • Patent number: 10734062
    Abstract: A semiconductor device includes a cell array having an upper segment and a lower segment which are classified according to refresh units. The semiconductor device includes a first repair controller configured to output a first repair signal for controlling a repair operation of the upper segment based on a fuse address, a row address, a second control signal, and selection address being at a first level, and generate a first control signal for controlling a repair operation of the lower segment based on the fuse address, the row address, and selection address.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: August 4, 2020
    Assignee: SK hynix Inc.
    Inventors: Ja Beom Koo, Sung Soo Chi
  • Patent number: 10700065
    Abstract: In an embodiment, an integrated circuit includes transistors in different active regions, electrically isolated using single diffusion break isolation. The single diffusion break isolation includes a first dummy transistor that has a different threshold voltage than the transistors in either active region for which the single diffusion break is creating isolation. The first dummy transistor may have lower leakage current than transistors in either active region, creating effective isolation between the active regions and consuming relatively small amounts of power due to the lower leakage currents.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: June 30, 2020
    Assignee: Apple Inc.
    Inventors: Emre Alptekin, Thomas Hoffmann
  • Patent number: 10651228
    Abstract: A photodetector includes a quantum dot group including a first quantum dot of a reference size and a second quantum dot of a size other than the reference size, a first resonant tunneling structure disposed on a first side of the quantum dot group and including a barrier layer, a well layer, and a barrier layer, and a second resonant tunneling structure disposed on a second side of the quantum dot group and including a barrier layer, a well layer, and a barrier layer, wherein a first resonance level of the first resonant tunneling structure and a ground level of the first quantum dot have a relationship that causes tunneling, and a second resonance level of the second resonant tunneling structure and an excited level of the first quantum dot have a relationship that causes tunneling.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: May 12, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Hiroyasu Yamashita
  • Patent number: 10615352
    Abstract: An excellent complementary semiconductor device is provided using a simple process. An n-type drive semiconductor device including a substrate; and a source electrode, a drain electrode, a gate electrode, a gate insulating layer, and a semiconductor layer on the substrate; and including a second insulating layer on the opposite side of the semiconductor layer from the gate insulating layer; in which the second insulating layer contains an organic compound containing a bond between a carbon atom and a nitrogen atom; and in which the semiconductor layer contains a carbon nanotube composite having a conjugated polymer attached to at least a part of the surface thereof.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: April 7, 2020
    Assignee: TORAY INDUSTRIES, INC.
    Inventors: Hiroji Shimizu, Seiichiro Murase, Daisuke Sakaii
  • Patent number: 10615183
    Abstract: An electronic device includes a first substrate, a second substrate, a plurality of first metal line segments and a shielding layer. The second substrate is opposite to the first substrate. The first metal line segments are disposed on the first substrate and extend along a first direction, wherein at least one of the first metal line segments includes a first alignment part and a first trace part, a width of the first alignment part is larger than a width of the first trace part, and the first alignment parts are arranged along a second direction. The shielding layer is disposed on the second substrate, and the shielding layer includes a plurality of first alignment structures, wherein one of the first alignment parts is aligned with one of the first alignment structures in a normal vector of the first substrate.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: April 7, 2020
    Assignee: HANNSTAR DISPLAY CORPORATION
    Inventors: Chung-Lin Chang, Hsuan-Chen Liu
  • Patent number: 10593599
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The method includes: recessing an isolation region between adjacent gate structures and below metallization overburden of source/drain metallization; planarizing the metallization overburden to a level of the adjacent gate structures; and forming source/drain contacts to the source/drain metallization, on sides of and extending above the adjacent gate structures.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: March 17, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chanro Park, Stan Tsai
  • Patent number: 10573722
    Abstract: In an embodiment, a wide bandgap semiconductor power device, includes a wide bandgap semiconductor substrate layer; an epitaxial semiconductor layer disposed above the wide bandgap semiconductor substrate layer; a gate dielectric layer disposed directly over a portion of the epitaxial semiconductor layer; and a gate electrode disposed directly over the gate dielectric layer. The gate electrode includes an in-situ doped semiconductor layer disposed directly over the gate dielectric layer and a metal-containing layer disposed directly over the in-situ doped semiconductor layer.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: February 25, 2020
    Assignee: GENERAL ELECTRIC COMPANY
    Inventor: Thomas Bert Gorczyca
  • Patent number: 10546859
    Abstract: Under one aspect, a non-volatile nanotube diode device includes first and second terminals; a semiconductor element including a cathode and an anode, and capable of forming a conductive pathway between the cathode and anode in response to electrical stimulus applied to the first conductive terminal; and a nanotube switching element including a nanotube fabric article in electrical communication with the semiconductive element, the nanotube fabric article disposed between and capable of forming a conductive pathway between the semiconductor element and the second terminal, wherein electrical stimuli on the first and second terminals causes a plurality of logic states.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: January 28, 2020
    Assignee: Nantero, Inc.
    Inventors: Claude L. Bertin, Thomas Rueckes, X. M. Henry Huang, Ramesh Sivarajan, Eliodor G. Ghenciu, Steven L. Konsek, Mitchell Meinhold
  • Patent number: 10488364
    Abstract: Methods and apparatuses for detecting ammonia are disclosed. A sensor can include a transistor having a gate, a drain, and a source. A layer of ammonia detecting material can be functionally attached to the transistor. The ammonia detecting material can be zinc oxide (ZnO) nanorods, which effectively functionalize the transistor by changing the amount of current that flows through the gate when a voltage is applied. Alternatively, or in addition to ZnO nanorods, films or nanostructure type metal oxides including TiO2, ITO, ZnO, WO3 and AZO can be used. The transistor is preferably a high electron mobility transistor (HEMT).
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: November 26, 2019
    Assignee: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INCORPORATED
    Inventors: Soohwan Jang, Fan Ren, Stephen J. Pearton
  • Patent number: 10446401
    Abstract: Reliability of a semiconductor device is improved. In a method of manufacturing a semiconductor device, nitrogen is introduced into a surface of a substrate and a sacrificial film is formed on the surface in a field effect transistor formation region different from a memory transistor formation region. Subsequently, the sacrificial film is removed to remove the nitrogen introduced in the surface of the substrate in the field effect transistor formation region.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: October 15, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hideki Makiyama
  • Patent number: 10403821
    Abstract: A method of making an electrode for an organic electronic device comprises the steps of depositing an ink on a light emitting layer, and drying said ink to form said electrode. The ink comprises conductive metal or carbon particles, a binder and a hydrocarbon solvent selected from 1,1?-bicyclohexyl, cis-decalin trans-decaiin or n-undecane.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: September 3, 2019
    Assignee: Cambridge Display Technology Limited
    Inventors: Simon Goddard, Nicholas Dartnell
  • Patent number: 10366972
    Abstract: The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed microelectronics package includes a module substrate, a first die with a first coupling component, a second die with a second coupling component, and a first mold compound. The first die is attached to the module substrate. The first mold compound resides over the module substrate, surrounds the first die, and extends above an upper surface of the first die to define a first opening. Herein, the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first die in X-direction and Y-direction. The second die is stacked with the first die and in the first opening, such that the second coupling component is mirrored to the first coupling component.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: July 30, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim
  • Patent number: 10361300
    Abstract: A vertical FET with asymmetrically positioned source region and drain region is provided. The source region of the vertical FET is separated from a gate electrode by a gate dielectric and the drain region of the vertical FET is separated from the gate electrode by a drain spacer formed therebetween.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10347525
    Abstract: A method for producing a bonded SOI wafer, by ion implantation delamination to fabricate a bonded SOI wafer having a BOX layer and a SOI layer on a base wafer. After performing flattening heat treatment in an argon gas-containing atmosphere, sacrificial oxidation treatment adjusts the film thickness of the SOI layer, wherein the film thickness of the BOX layer is 500 nm or more. A sacrificial oxide film is formed so the relationship between the film thickness of the SOI layer on the sacrificial oxidation treatment is performed. The film thickness of the sacrificial oxide film formed by the sacrificial oxidation treatment satisfies 0.9d>t>0.45d. A method for producing a bonded SOI wafer can prevent the generation of particles from the outermost peripheral part, which is the form of an overhang by flattening heat treatment, of a SOI layer in the production of a bonded SOI wafer.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: July 9, 2019
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Isao Yokokawa
  • Patent number: 10325896
    Abstract: The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed microelectronics package includes a module substrate, a first die with a first coupling component, a second die with a second coupling component, and a first mold compound. The first die is attached to the module substrate. The first mold compound resides over the module substrate, surrounds the first die, and extends above an upper surface of the first die to define a first opening. Herein, the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first die in X-direction and Y-direction. The second die is stacked with the first die and in the first opening, such that the second coupling component is mirrored to the first coupling component.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: June 18, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim
  • Patent number: 10297678
    Abstract: The present disclosure provides a method for manufacturing a thin film transistor comprising, forming a pattern of an active layer on a substrate through a patterning process; performing ion doping to a channel region of the active layer; forming a gate insulating layer; forming a pattern of a gate through the patterning process; performing ion doping to a source contact region and a drain contact region of the active layer; forming an interlayer insulating layer; and performing laser annealing to the active layer, so as to make the active layer crystallize and the ions doped in the channel region, the source contact region and the drain contact region of the active layer activate simultaneously. In this method, the crystallization of the active layer and the activation of the ions doped in the active layer are implemented in the same process, which reduces the process cost and improves the efficiency.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: May 21, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaolong Li, Zunqing Song, Xiaowei Xu, Dong Li
  • Patent number: 10295409
    Abstract: According to one embodiment, a value of a film thickness of a processing object disposed above a substrate is obtained. Then, a wavelength that provides a highest degree of intensity of signal light reflected when the signal light is incident onto the processing object having the value of the film thickness, based on wavelength selection reference information is selected. Then, a first instruction performing an alignment process to the substrate by use of signal light having a wavelength thus selected is generated. The wavelength selection reference information is information that includes a correlation between values of the film thickness of the processing object and degrees of intensity of the signal light, with respect to a plurality of wavelengths.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: May 21, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Miki Toshima, Satoshi Usui, Manabu Takakuwa, Nobuhiro Komine, Takaki Hashimoto
  • Patent number: 10283494
    Abstract: The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed microelectronics package includes a module substrate, a first die with a first coupling component, a second die with a second coupling component, and a first mold compound. The first die is attached to the module substrate. The first mold compound resides over the module substrate, surrounds the first die, and extends above an upper surface of the first die to define a first opening. Herein, the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first die in X-direction and Y-direction. The second die is stacked with the first die and in the first opening, such that the second coupling component is mirrored to the first coupling component.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: May 7, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim
  • Patent number: 10236281
    Abstract: The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed microelectronics package includes a module substrate, a first die with a first coupling component, a second die with a second coupling component, and a first mold compound. The first die is attached to the module substrate. The first mold compound resides over the module substrate, surrounds the first die, and extends above an upper surface of the first die to define a first opening. Herein, the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first die in X-direction and Y-direction. The second die is stacked with the first die and in the first opening, such that the second coupling component is mirrored to the first coupling component.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: March 19, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim
  • Patent number: 10153347
    Abstract: A semiconductor device includes a first nitride semiconductor layer containing Ga, a second nitride semiconductor layer provided on the first nitride semiconductor layer containing Ga, a first electrode and a second electrode provided on or above the first nitride semiconductor layer and electrically connected to the first nitride semiconductor layer, a gate electrode provided between the first electrode and the second electrode, a conductive layer provided on or above the second electrode, of which a first distance to the second electrode is smaller than a second distance between the second electrode and the gate electrode, and which is electrically connected to the first electrode or the gate electrode, a first aluminum oxide layer provided between the gate electrode and the second electrode and provided between the second nitride semiconductor layer and the conductive layer, a silicon oxide layer, and a second aluminum oxide layer.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: December 11, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Hisashi Saito, Hiroshi Ono
  • Patent number: 10141084
    Abstract: An anisotropic conductive film, the anisotropic conductive film including an insulating layer and a conductive layer laminated on the insulating layer, the conductive layer containing conductive particles, wherein after glass substrates are positioned to face each other on the upper and lower surface of the anisotropic conductive film and are pressed against the anisotropic conductive film at 3 MPa (based on the sample area) and 160° C. (based on the detection temperature of the anisotropic conductive film) for 5 sec, a ratio of the area of the insulating layer to that of the conductive layer is from about 1.3:1 to about 3.0:1.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 27, 2018
    Assignee: Cheil Industries, Inc.
    Inventors: Kyoung Soo Park, Woo Suk Lee, Woo Jun Lim, Kyung Jin Lee, Bong Yong Kim, Jin Seong Park, Dong Seon Uh, Youn Jo Ko, Jang Hyun Cho, Sang Sik Bae, Jin Kyu Kim
  • Patent number: 10096601
    Abstract: Under one aspect, a non-volatile nanotube diode device includes first and second terminals; a semiconductor element including a cathode and an anode, and capable of forming a conductive pathway between the cathode and anode in response to electrical stimulus applied to the first conductive terminal; and a nanotube switching element including a nanotube fabric article in electrical communication with the semiconductive element, the nanotube fabric article disposed between and capable of forming a conductive pathway between the semiconductor element and the second terminal, wherein electrical stimuli on the first and second terminals causes a plurality of logic states.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: October 9, 2018
    Assignee: Nantero, Inc.
    Inventors: Claude L. Bertin, Thomas Rueckes, X. M. Henry Huang, Ramesh Sivarajan, Eliodor G. Ghenciu, Steven L. Konsek, Mitchell Meinhold
  • Patent number: 10026775
    Abstract: The performances of a semiconductor device are improved. A semiconductor device has a photodiode and a transfer transistor formed in a pixel region. Further, the semiconductor device has a second transistor formed in a peripheral circuit region. The transfer transistor includes a first gate electrode, and a film part formed of a thick hard mask film formed over the first gate electrode. The second transistor includes a second gate electrode, source/drain regions, silicide layers formed at the upper surface of the second gate electrode, and the upper surfaces of the source/drain regions.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: July 17, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Takeshi Kamino
  • Patent number: 9991324
    Abstract: The present invention belongs to the field of display technology, and particularly relates to an array substrate, a display panel and a display device. The array substrate comprises a light-emitting unit, a driving unit for driving the light-emitting unit, and a driving signal unit for providing a driving signal to the driving unit, the driving unit being provided in a central area of the array substrate, the driving signal unit being provided on at least one side of a marginal area surrounding the central area, wherein the light-emitting unit covers the driving unit and extends into the at least one side of the marginal area on which the driving signal unit is provided. The array substrate can have not only enlarged display area but also decreased bezel width, and also have improved aperture ratio of a pixel.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: June 5, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guang Li, Xinshe Yin, Tuo Sun
  • Patent number: 9972720
    Abstract: A semiconductor device includes a substrate. A planar insulating layer is disposed on an upper surface of the substrate. A channel region is disposed above the planar insulating layer. A gate electrode is disposed on the channel region. The semiconductor device includes a source region and a drain region. Each of the source region and the drain region is disposed on the substrate and is connected to the channel region. The planar insulating layer has a length equal to or greater than a length of the channel region, and the planar insulating layer includes first and second insulating layers having different permittivities.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: May 15, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Dong Il Bae
  • Patent number: 9966355
    Abstract: A wire, preferably a bonding wire for bonding in microelectronics, contains a copper core with a surface and coating layer containing aluminum superimposed over the surface of the copper core. The ratio of the thickness of the coating layer to the diameter of the copper core is from 0.05 to 0.2 ?m. The wire has a diameter in the range of from 100 ?m to 600 ?m and specified standard deviations of the diameter of the copper core and of the thickness of the coating layer. The invention further relates to a process for making a wire, to a wire obtained by the process, to an electric device containing at least two elements and the wire, to a propelled device containing the electric device, and to a process of connecting two elements through the wire by wedge bonding.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: May 8, 2018
    Assignee: Heraeus Deutschland GmbH & Co. KG
    Inventors: Eugen Milke, Peter Prenosil, Sven Thomas
  • Patent number: 9960230
    Abstract: A SIC transistor device includes a silicon-carbide semiconductor substrate having a plurality of first doped regions laterally spaced apart from one another and beneath a main surface of the substrate, a second doped region extending from the main surface to a third doped region that is above the first doped regions, and a plurality of fourth doped regions in the substrate extending from the main surface to the first doped regions. The second doped region has a first conductivity type. The first, third and fourth doped regions have a second conductivity type opposite the first conductivity type. A gate trench extends through the second and third doped regions. The gate trench has sidewalls, a bottom and rounded corners between the bottom and the sidewalls.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: May 1, 2018
    Assignee: Infineon Technologies AG
    Inventors: Romain Esteve, Dethard Peters, Wolfgang Bergner, Ralf Siemieniec, Thomas Aichinger, Daniel Kueck
  • Patent number: 9940425
    Abstract: A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logical cells to make it difficult for reverse engineering programs to be used to discover the circuit's function. Additionally, post processing may be performed on GDS layers to provide a realistic fill of the empty space so as to resemble structural elements found in a functional circuit.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: April 10, 2018
    Assignee: Inside Secure S.A.
    Inventors: Bryan Jason Wang, Lap Wai Chow, James Peter Baukus, Ronald Paul Cocchi
  • Patent number: 9923053
    Abstract: A SIC transistor device includes a silicon-carbide semiconductor substrate having a plurality of first doped regions laterally spaced apart from one another and beneath a main surface of the substrate, a second doped region extending from the main surface to a third doped region that is above the first doped regions, and a plurality of fourth doped regions in the substrate extending from the main surface to the first doped regions. The second doped region has a first conductivity type. The first, third and fourth doped regions have a second conductivity type opposite the first conductivity type. A gate trench extends through the second and third doped regions. The gate trench has sidewalls, a bottom and rounded corners between the bottom and the sidewalls.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: March 20, 2018
    Assignee: Infineon Technologies AG
    Inventors: Romain Esteve, Dethard Peters, Wolfgang Bergner, Ralf Siemieniec, Thomas Aichinger, Daniel Kueck
  • Patent number: 9875948
    Abstract: A package wafer processing method includes a processing step of processing a package wafer along planned dividing lines by a laser beam irradiation unit and forming processing grooves in the package wafer. The processing step includes detecting a processing groove and an exposed key pattern closest to the planned dividing line corresponding to the processing groove at a predetermined timing and measuring, as a deviation amount, the difference between the distance from the processing groove to the exposed key pattern and the distance that is registered in a registration step and is from the planned dividing line corresponding to the processing groove to the closest key pattern. An indexing feed mechanism is corrected according to the deviation amount.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: January 23, 2018
    Assignee: DISCO CORPORATION
    Inventors: Xin Lu, Makoto Tanaka
  • Patent number: 9799612
    Abstract: A semiconductor device includes a substrate, a laminated wiring layer unit, a nitride film disposed on the laminated wiring layer unit, a semiconductor element portion, a sealing portion surrounding the element portion. In the sealing portion, multiple wiring layers are connected with a sealing layer to configure a sealing structure which surrounds the element portion. The laminated wiring layer unit includes an uppermost layer which is made of material having higher adhesion to an uppermost wiring layer, and a protection insulating film made of material having higher adhesion to the sealing layer than the nitride film is disposed on the nitride film. In the sealing portion, a via-hole is defined in the protection insulating film, the nitride film, and the uppermost insulating film to partially expose the uppermost wiring layer. The sealing layer is embedded into the via-hole and is also disposed on a protection insulating film around the via-hole.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: October 24, 2017
    Assignee: DENSO CORPORATION
    Inventor: Kouji Eguchi
  • Patent number: 9773076
    Abstract: In a method, conductive lines used in a circuit are formed. Signal traces of a plurality of signal traces are grouped to a first group of first signal traces or a second group of second signal traces. A first mask is used to form a first conductive line for a first signal trace of the first group. A second mask is used to form a second conductive line for a second signal trace of the second group. The first traces each have a first width. The second traces each have a second width different from the first width. The grouping is based on at least one of following conditions: a current flowing through a signal trace of the signal traces of the plurality of signal traces, a length of the signal trace, a resistivity of the signal trace, or a resistivity-capacitive constant of the signal trace.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: September 26, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chung-Hui Chen
  • Patent number: 9773921
    Abstract: The present disclosure generally relates to an improved large area substrate thin film transistor device, and method of fabrication thereof. More specifically, amorphous and LTPS transistors are formed by first forming an amorphous silicon layer, annealing the amorphous silicon layer to form polycrystalline silicon, depositing a masking layer over a first portion of the polycrystalline silicon layer, implanting a second portion of the polycrystalline silicon layer with an amorphizing species, and removing the masking layer.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: September 26, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Peter Nunan, Xuena Zhang
  • Patent number: 9768248
    Abstract: According to one embodiment, a semiconductor device is provided. The semiconductor device has a first region formed of semiconductor and a second region formed of semiconductor which borders the first region. An electrode is formed to be in ohmic-connection with the first region. A third region is formed to sandwich the first region. A first potential difference is produced between the first and the second regions in a thermal equilibrium state, according to a second potential difference between the third region and the first region.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: September 19, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mitsuhiko Kitagawa
  • Patent number: 9640422
    Abstract: A trench comprising a portion of a substrate is formed. A nucleation layer is deposited on the portion of the substrate within the trench. A III-N material layer is deposited on the nucleation layer. The III-N material layer is laterally grown over the trench. A device layer is deposited on the laterally grown III-N material layer. A low defect density region is obtained on the laterally grown material and is used for electronic device fabrication of III-N materials on Si substrates.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: May 2, 2017
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Sanaz K. Gardner, Seung Hoon Sung, Marko Radosavljevic, Benjamin Chu-Kung, Sherry R. Taft, Ravi Pillarisetty, Robert S. Chau
  • Patent number: 9602746
    Abstract: An image pickup device includes on a silicon layer: a photodiode provided on each pixel basis to perform photoelectric conversion to generate a charge depending on the light receiving amount; a floating diffusion section configured to store the charge generated by the photodiode; and a transistor configured to output a pixel signal at a voltage in accordance with a level of the charge stored in the floating diffusion section, wherein the image pickup device further includes a hermetically-sealed cavity section inside the silicon layer and on at least one of the underside of the floating diffusion section and the underside of a channel body region of the transistor.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: March 21, 2017
    Assignee: Sony Corporation
    Inventor: Yuki Miyanami
  • Patent number: 9569852
    Abstract: An alignment method includes: a storage step that images a first workpiece on a chuck table and stores positions of alignment marks corresponding to scheduled division lines and positional relationships of the division lines with the alignment marks; a holding step that holds a second workpiece with the chuck table; a detection step that images positions of the alignment marks on the second workpiece, the positions corresponding to the stored alignment mark positions, and detects the alignment marks of the second workpiece; and an identification step that identifies positions of scheduled division lines of the second workpiece on the basis of the detected positions of the alignment marks of the second workpiece and the stored positional relationships. If one of the alignment marks of the second workpiece cannot be detected at one of the stored alignment mark positions, the detection step detects other adjacent alignment marks.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: February 14, 2017
    Assignee: Disco Corporation
    Inventor: Makoto Tanaka
  • Patent number: 9515100
    Abstract: Embodiments of the present invention provide an array substrate, a manufacturing method thereof and a display device. The method for manufacturing the array substrate comprises: forming a pattern of an active layer of a switching thin-film transistor (TFT) and a pattern of a corresponding pixel electrode on a base substrate, in which the active layer of the switching TFT and the pixel electrode are on the same layer.
    Type: Grant
    Filed: December 7, 2013
    Date of Patent: December 6, 2016
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Jang Soon Im
  • Patent number: 9466585
    Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: October 11, 2016
    Assignee: NXP B.V.
    Inventors: Tonny Kamphuis, Leonardus Antonius Elisabeth van Gemert, Roelf Anco Jacob Groenhuis, Caroline Catharina Maria Beelen-Hendrikx, Franciscus Henrikus Martinus Swartjes, Jetse de Witte
  • Patent number: 9425312
    Abstract: Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and III-N source regions are provided for low power operations. A broken-band heterojunction is formed by the source and channel regions of the transistors. Fabrication methods include selective anisotropic wet-etching of a silicon substrate followed by epitaxial deposition of III-N material and/or germanium implantation of the substrate followed by the epitaxial deposition of the III-N material.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: August 23, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anirban Basu, Bahman Hekmatshoartabari, Davood Shahrjerdi
  • Patent number: 9401338
    Abstract: An embodiment of an electronic device includes an IC die with a top surface and a bond pad exposed at the top surface. A stud bump (or stack of stud bumps) is connected to the bond pad, and the stud bump and die are encapsulated with encapsulant. A trench is formed from a top surface of the encapsulant to the stud bump, resulting in the formation of a trench-oriented surface of the stud bump, which is exposed at the bottom of the trench. An end of an interconnect is connected to the trench-oriented surface of the stud bump. The interconnect extends above the encapsulant top surface, and may be coupled to another IC die of the same electronic device, another IC die that is distinct from the device, or another conductive feature of the device or a larger electronic system in which the device is incorporated.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: July 26, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Alan J. Magnus, Francisco Chaidez
  • Patent number: 9379150
    Abstract: The present invention improves the performance of an image sensor. In a planar view, fluorine is introduced into a part overlapping with a channel region in a gate electrode GE1 of an amplification transistor and is not introduced into the interior of a semiconductor substrate 1S. Concretely as shown in FIG. 20, a resist film FR1 is patterned in the manner of opening the part planarly overlapping with the channel region in the gate electrode GE1. Then fluorine is injected into the interior of the gate electrode GE1 exposed from an opening OP1 by an ion implantation method using the resist film FR1 in which the opening OP1 is formed as a mask.
    Type: Grant
    Filed: October 25, 2014
    Date of Patent: June 28, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Yukio Nishida, Tomohiro Yamashita, Yuki Yamamoto