Abstract: A substrate processing method capable of filling a gap structure without forming voids or seams in a gap while minimizing damage to the gap structure includes: forming a first thin film on a structure by performing a first cycle a plurality of times, the first cycle including supplying a first reaction gas onto the structure including a gap and purging a residue, forming a second thin film by changing a chemical composition of the first thin film, and forming a third thin film having the same component as that of the second thin film on the second thin film while filling the gap.

Abstract: A light emitting device includes a substrate, and a laminated structure provided to the substrate, and including a columnar part, wherein the columnar part includes a first GaN layer having a first conductivity type, a second GaN layer having a second conductivity type different from the first conductivity type, and a light emitting layer disposed between the first GaN layer and the second GaN layer, the first GaN layer is disposed between the substrate and the light emitting layer, the light emitting layer has a first well layer as an InGaN layer, the first GaN layer has a c-face region, the first GaN layer has a crystal structure of a cubical crystal, and has a first layer constituting the c-face region, and a second layer as a GaN layer having a crystal structure of a hexagonal crystal is disposed between the first layer and the first well layer.

Abstract: A manufacturing system includes a printer chamber having a printer bed that supports manufacturing materials and an internal heating system supported by the printer chamber. The internal heating systems is configured to direct patterned heat energy onto the printer bed and supported manufacturing materials. An external heating system is supported by or positioned near the printer chamber and configured to direct patterned heat energy onto the printer bed and any supported manufacturing materials.

Abstract: A method includes positioning a discrete component assembly on a support fixture of a component transfer system, the discrete component assembly including a dynamic release tape including a flexible support layer, and a dynamic release structure disposed on the flexible support layer, and a discrete component adhered to the dynamic release tape. The method includes irradiating the dynamic release structure to release the discrete component from the dynamic release tape.

Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-? dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium lanthanum nitride (TiLaN), titanium yttrium nitride (TiYN), titanium strontium nitride (TiSrN), titanium magnesium nitriride (TiMgN, titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium carbide aluminum (HfCAl), hafnium aluminum nitride (HfAlN), or hafnium carbonitride (HfCN).

Abstract: First and second concentration measurements are provided in lines for first and second supply liquid lines. A dissolved concentration of gas in the second supply liquid is lower than that in the first supply liquid. In the first and second lines, first ends of branch lines are connected upstream of the concentration measurements. The second ends of the branch lines are connected to a mixing part. By mixing the first and second supply liquids, a processing liquid is generated. Respective flow rates in the branch lines are based on the first and second concentration measurements to set the dissolved concentration of the gas in the processing liquid. Thus, particles or the like can be removed from the processing liquid to be supplied to a substrate, and the dissolved concentration of the gas in the processing liquid can be set with high accuracy.

Abstract: A Fail Bit (FB) repair method includes: a bank to be repaired of a chip to be repaired is determined; first repair processing is performed on a first FB using a redundant circuit; a bit position of a second FB in each target repair bank is determined, and second repair processing is performed on the second FB; an unrepaired FB in each target repair bank is determined, and candidate repair combinations of the unrepaired FBs and a candidate combination count are determined; and if the candidate combination count is greater than a combination count threshold, a target repair position is determined, and repair processing is performed on the target repair position using a Redundant Word-Line (RWL), the target repair position being a position of an FB that maximally reduces the candidate combination count after repair processing.

Abstract: A semiconductor structure is disclosed, including a first conductive line and a first power rail and a first transistor structure arranged between the first conductive line and the first power rail. The first conductive line and the first power rail are separated from each other in a first direction. The first transistor structure includes a first active region coupled to the first conductive line by a first via; a second active region coupled to the first power rail by a second via; and a first gate structure interposed between the first active region and the second active region, and configured to receive a first control signal. The first transistor structure transmits a signal between the first conductive line and the first power rail in response to the first control signal.

Abstract: An atomic layer deposition (ALD) process for depositing a fluorine-containing thin film on a substrate can include a plurality of super-cycles. Each super-cycle may include a metal fluoride sub-cycle and a reducing sub-cycle. The metal fluoride sub-cycle may include contacting the substrate with a metal fluoride. The reducing sub-cycle may include alternately and sequentially contacting the substrate with a reducing agent and a nitrogen reactant.

Abstract: A method for determining a Fail Bit (FB) repair scheme includes: a bank to be repaired of a chip to be repaired is determined, the bank to be repaired including multiple target repair areas; initial repair processing is performed on an FB in each of the target repair areas using a redundant circuit; responsive to that a number of remaining Redundant Word Lines (RWLs) is greater than 0 and a number of remaining Redundant Bit Lines (RBLs) is greater than 0, a candidate repair sub-scheme for each target repair area is determined, and a candidate repair cost corresponding to each candidate repair sub-scheme is determined; and a target repair scheme for the bank to be repaired is determined according to respective candidate repair sub-schemes and candidate repair costs, where the target repair scheme corresponds to a minimum integrated repair cost.

Abstract: An integrated circuit includes a semiconductor substrate, devices, first tap regions, and second tap regions. The devices are over the semiconductor substrate. The first tap regions are over the semiconductor substrate along a first direction. The second tap regions are over the semiconductor substrate along the first direction. A first pitch between adjacent two of the first tap regions in the first direction is greater than a second pitch between adjacent two of the second tap regions in the first direction.

Abstract: Provided are a method for polishing a silicon substrate according to which PID can be reduced and a polishing composition set usable in the polishing method. The silicon substrate polishing method provided by this invention comprises a stock polishing step and a final polishing step. The stock polishing step comprises several stock polishing sub-steps carried out on one same platen. The several stock polishing sub-steps comprise a final stock polishing sub-step carried out while supplying a final stock polishing slurry PF to the silicon substrate. The total amount of the final stock polishing slurry PF supplied to the silicon substrate during the final stock polishing sub-step has a total weight of Cu and a total weight of Ni, at least one of which being 1 ?g or less.

Abstract: A semiconductor structure includes a metal gate structure disposed over a semiconductor substrate, an interlayer dielectric (ILD) layer disposed over the metal gate structure, and a gate contact disposed in the ILD layer and over the metal gate structure, where a bottom surface of the gate contact is defined by a barrier layer disposed over the metal gate structure, where sidewall surfaces of the gate contact are defined by and directly in contact with the ILD layer, and where the barrier layer is free of nitrogen.

Abstract: A semiconductor device includes a semiconductor substrate, a capacitor structure, a first contact plug, and a spacer. The capacitor structure is over the semiconductor substrate. The capacitor structure includes a bottom electrode, a capacitor dielectric, and a top electrode. The bottom electrode is over the semiconductor substrate. The capacitor dielectric is over a first portion of the bottom electrode. The top electrode is over the capacitor dielectric. The first contact plug is over and electrically connected to a second portion of the bottom electrode. The spacer is adjacent at least a sidewall of the second portion of the bottom electrode.

Abstract: A security chip includes: a first medium layer; a second medium layer disposed on the first medium layer, where the first medium layer is an optically denser medium relative to the second medium layer, and a roughness of an upper surface of the first medium layer is greater than or equal to a preset threshold, so that light entering the second medium layer from the first medium layer is able to be totally reflected and/or scattered; and a semiconductor chip disposed on the second medium layer. Based on the above technical solution, light incident from a lower surface of the first medium layer is able to be totally reflected or scattered by the upper surface of the first medium layer, so that most of light cannot reach a logic or storage area on the front of the security chip, thereby achieving the purpose of resisting a laser attack.

Abstract: An atomic layer deposition (ALD) process for depositing a fluorine-containing thin film on a substrate can include a plurality of super-cycles. Each super-cycle may include a metal fluoride sub-cycle and a reducing sub-cycle. The metal fluoride sub-cycle may include contacting the substrate with a metal fluoride. The reducing sub-cycle may include alternately and sequentially contacting the substrate with a reducing agent and a nitrogen reactant.

Abstract: A method for fabricating a photonic device is provided. The method includes forming an optical coupler and a waveguide structure connected to the optical coupler over a semiconductor substrate; forming a metal-dielectric stack over the optical coupler and the waveguide structure; etching a hole in the metal-dielectric stack and vertically overlapping the optical coupler; and forming a protection layer on a sidewall and a bottom of the hole.

Abstract: This disclosure provides an image distance sensor and a manufacture method thereof, as well as a ranging device. The image distance sensor includes a semiconductor substrate, and an image sensing unit and a distance sensing unit formed on the semiconductor substrate. The image sensing unit and the distance sensing unit are formed in a same manufacture process.

Abstract: Under one aspect, a non-volatile nanotube diode device includes first and second terminals; a semiconductor element including a cathode and an anode, and capable of forming a conductive pathway between the cathode and anode in response to electrical stimulus applied to the first conductive terminal; and a nanotube switching element including a nanotube fabric article in electrical communication with the semiconductive element, the nanotube fabric article disposed between and capable of forming a conductive pathway between the semiconductor element and the second terminal, wherein electrical stimuli on the first and second terminals causes a plurality of logic states.

Abstract: An ink jet process is used to deposit a material layer to a desired thickness. Layout data is converted to per-cell grayscale values, each representing ink volume to be locally delivered. The grayscale values are used to generate a halftone pattern to deliver variable ink volume (and thickness) to the substrate. The halftoning provides for a relatively continuous layer (e.g., without unintended gaps or holes) while providing for variable volume and, thus, contributes to variable ink/material buildup to achieve desired thickness. The ink is jetted as liquid or aerosol that suspends material used to form the material layer, for example, an organic material used to form an encapsulation layer for a flat panel device. The deposited layer is then cured or otherwise finished to complete the process.

Abstract: In a silicon carbide stacked substrate, the efficiency of converting the basal plane dislocation (BPD) which is a fault to deteriorate the current-carrying reliability into a threading edge dislocation (TED) which is a harmless fault is improved, thereby improving the reliability of the silicon carbide stacked substrate. As means therefor, in a silicon carbide stacked substrate including a SiC substrate and a buffer layer and a drift layer which are epitaxial layers sequentially formed on the SiC substrate, a semiconductor layer having an impurity concentration lower than those of the SiC substrate and the buffer layer and higher than that of the drift layer is formed between the SiC substrate and the buffer layer so as to be in contact with an upper surface of the SiC substrate.

Abstract: Provided is an oxide semiconductor gas sensor with improved performance that senses selectively methylbenzene gases with high sensitivity. The gas sensor includes a gas sensing layer composed of palladium (Pd)-loaded cobalt oxide (Co3O4) nanostructures. The response of the gas sensor according to the present invention to xylene gas at a concentration as low as 5 ppm is at least 150 times higher than that to ethanol gas. The response of the gas sensor to toluene gas at a concentration as low as 5 ppm is at least 100 times higher than that to ethanol gas. In addition, the oxide semiconductor gas sensor has the ability to selectively detect methylbenzene gases, including xylene and toluene (with at least 30-fold higher response to xylene and at least 15 times higher response to toluene than that to ethanol gas).

Abstract: A method of treating a substrate includes directing ions to the substrate along at least one non-zero angle with respect to a perpendicular to a substrate surface in a presence of a reactive ambient containing a reactive species where the substrate includes a surface feature. At least one surface of the surface feature is etched using the ions in combination with the reactive ambient at a first etch rate that is greater than a second etch rate when the ions are directed to the substrate without the reactive ambient and greater than a third etch rate when the reactive ambient is provided to the substrate without the ions.

Abstract: A laser processing method includes a step of holding a film side of a workpiece which has been divided into chips and whose reverse side carries an adhesive film stuck thereto, a step of detecting widths of grooves in the workpiece at predetermined chip intervals and central coordinates of the widths of the grooves, a step of calculating laser beam irradiation lines based on the detected widths of the grooves and the detected central coordinates, a step of determining misalignment levels of the calculated laser beam irradiation lines according to misalignments of the grooves in widthwise directions thereof, and a step of processing the adhesive film with a laser beam by applying the laser beam to the adhesive film at bottoms of the grooves along the laser beam irradiation lines, thereby separating the adhesive film.

Abstract: Embodiments described herein relate generally to methods for forming low-k dielectrics and the structures formed thereby. In some embodiments, a dielectric is formed over a semiconductor substrate. The dielectric has a k-value equal to or less than 3.9. Forming the dielectric includes using a plasma enhanced chemical vapor deposition (PECVD). The PECVD includes flowing a diethoxymethylsilane (mDEOS, C5H14O2Si) precursor gas, flowing an oxygen (O2) precursor gas; and flowing a carrier gas. A ratio of a flow rate of the mDEOS precursor gas to a flow rate of the carrier gas is less than or equal to 0.2.

Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. While activated, the read assist transistor may generate an adaptive underdrive on the wordline, the level of which depends on the process, temperature and voltage of operation of the memory, when the wordline is selected and driven by the wordline driver.

Abstract: There is provided a technique that includes: (a) forming a silicon germanium film in an amorphous state so as to embed an inside of a recess formed on a surface of a substrate, by supplying a first silicon-containing gas and a germanium-containing gas to the substrate at a first temperature; (b) raising a temperature of the substrate from the first temperature to a second temperature, which is higher than the first temperature; and (c) forming a silicon film on the silicon germanium film by supplying a second silicon-containing gas to the substrate at the second temperature, wherein in (c), the silicon germanium film as a base of the silicon film is crystallized while the silicon film is formed.

Abstract: A solid-state imaging element includes a plurality of shallow light receivers that are arrayed two-dimensionally in the vicinity of the surface of a semiconductor substrate and a plurality of deep light receivers that are arrayed two-dimensionally below the shallow light receivers. The shallow light receivers include visible light image light receivers that photoelectrically convert visible light and infrared light and output signals, and infrared light receivers that photoelectrically convert the infrared light. The infrared light receivers include a first infrared light receiver that is used to correct the signals output from the visible light image light receivers to provide signals of visible light components in the visible light image light receivers and a second infrared light receiver that is connected to the deep light receivers to form a multilayer light receiver.

Abstract: An electronics package includes an insulating substrate, an electrical component having a back surface coupled to a first surface of the insulating substrate, and an insulating structure surrounding at least a portion of a perimeter of the electrical component. A first wiring layer extends from the first surface of the insulating substrate and over a sloped side surface of the insulating structure to electrically couple with at least one contact pad on an active surface of the electrical component. A second wiring layer is formed on a second surface of the insulating substrate and extends through at least one via therein to electrically couple with the first wiring layer.

Abstract: In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first side wall spacers is different from a second depth of the first space above the first gate electrode layer.

Abstract: An optoelectronic component includes an optoelectronic semiconductor chip that emits electromagnetic radiation, arranged in a housing, wherein the housing has an outer wall face and an exit face transparent to the electromagnetic radiation, the exit face is set back relative to the outer wall face in a direction of an interior of the housing, the optoelectronic semiconductor chip is arranged such that radiation emitted by the optoelectronic semiconductor chip in an emission direction can emerge from the optoelectronic component through the exit face, and the outer wall face has separating marks and the exit face is free of separating marks.

Abstract: Embodiments of a semiconductor memory device include a substrate having a first region with peripheral devices, a second region with one or more memory arrays, and a third region between the first and the second regions. The semiconductor memory device also includes a protective structure for peripheral devices. The protective structure for peripheral devices of the semiconductor memory device includes a first dielectric layer and a barrier layer disposed on the first dielectric layer. The protective structure for peripheral devices of the semiconductor memory device further includes a dielectric spacer formed on a sidewall of the barrier layer and a sidewall of the first dielectric layer, wherein the protective structure is disposed over the first region and at least a portion of the third region.

Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a substrate, a plurality of first gate structures, a first dielectric layer, a second dielectric layer, a third dielectric layer and a contact plug. The first gate structures are formed on an array region of the substrate. The first dielectric layer is formed on top surfaces and sidewalls of the first gate structures. The second dielectric layer is formed on the first dielectric layer and in direct contact with the first dielectric layer. The second dielectric layer and the first dielectric layer are made of the same material. The third dielectric layer is formed between the first gate structures and defines a plurality of contact holes exposing the substrate. The contact plug fills the contact holes.

Abstract: A semiconductor device includes a cell array having an upper segment and a lower segment which are classified according to refresh units. The semiconductor device includes a first repair controller configured to output a first repair signal for controlling a repair operation of the upper segment based on a fuse address, a row address, a second control signal, and selection address being at a first level, and generate a first control signal for controlling a repair operation of the lower segment based on the fuse address, the row address, and selection address.

Abstract: In an embodiment, an integrated circuit includes transistors in different active regions, electrically isolated using single diffusion break isolation. The single diffusion break isolation includes a first dummy transistor that has a different threshold voltage than the transistors in either active region for which the single diffusion break is creating isolation. The first dummy transistor may have lower leakage current than transistors in either active region, creating effective isolation between the active regions and consuming relatively small amounts of power due to the lower leakage currents.

Abstract: A photodetector includes a quantum dot group including a first quantum dot of a reference size and a second quantum dot of a size other than the reference size, a first resonant tunneling structure disposed on a first side of the quantum dot group and including a barrier layer, a well layer, and a barrier layer, and a second resonant tunneling structure disposed on a second side of the quantum dot group and including a barrier layer, a well layer, and a barrier layer, wherein a first resonance level of the first resonant tunneling structure and a ground level of the first quantum dot have a relationship that causes tunneling, and a second resonance level of the second resonant tunneling structure and an excited level of the first quantum dot have a relationship that causes tunneling.

Abstract: An electronic device includes a first substrate, a second substrate, a plurality of first metal line segments and a shielding layer. The second substrate is opposite to the first substrate. The first metal line segments are disposed on the first substrate and extend along a first direction, wherein at least one of the first metal line segments includes a first alignment part and a first trace part, a width of the first alignment part is larger than a width of the first trace part, and the first alignment parts are arranged along a second direction. The shielding layer is disposed on the second substrate, and the shielding layer includes a plurality of first alignment structures, wherein one of the first alignment parts is aligned with one of the first alignment structures in a normal vector of the first substrate.

Abstract: An excellent complementary semiconductor device is provided using a simple process. An n-type drive semiconductor device including a substrate; and a source electrode, a drain electrode, a gate electrode, a gate insulating layer, and a semiconductor layer on the substrate; and including a second insulating layer on the opposite side of the semiconductor layer from the gate insulating layer; in which the second insulating layer contains an organic compound containing a bond between a carbon atom and a nitrogen atom; and in which the semiconductor layer contains a carbon nanotube composite having a conjugated polymer attached to at least a part of the surface thereof.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The method includes: recessing an isolation region between adjacent gate structures and below metallization overburden of source/drain metallization; planarizing the metallization overburden to a level of the adjacent gate structures; and forming source/drain contacts to the source/drain metallization, on sides of and extending above the adjacent gate structures.

Abstract: In an embodiment, a wide bandgap semiconductor power device, includes a wide bandgap semiconductor substrate layer; an epitaxial semiconductor layer disposed above the wide bandgap semiconductor substrate layer; a gate dielectric layer disposed directly over a portion of the epitaxial semiconductor layer; and a gate electrode disposed directly over the gate dielectric layer. The gate electrode includes an in-situ doped semiconductor layer disposed directly over the gate dielectric layer and a metal-containing layer disposed directly over the in-situ doped semiconductor layer.

Abstract: Under one aspect, a non-volatile nanotube diode device includes first and second terminals; a semiconductor element including a cathode and an anode, and capable of forming a conductive pathway between the cathode and anode in response to electrical stimulus applied to the first conductive terminal; and a nanotube switching element including a nanotube fabric article in electrical communication with the semiconductive element, the nanotube fabric article disposed between and capable of forming a conductive pathway between the semiconductor element and the second terminal, wherein electrical stimuli on the first and second terminals causes a plurality of logic states.

Abstract: Methods and apparatuses for detecting ammonia are disclosed. A sensor can include a transistor having a gate, a drain, and a source. A layer of ammonia detecting material can be functionally attached to the transistor. The ammonia detecting material can be zinc oxide (ZnO) nanorods, which effectively functionalize the transistor by changing the amount of current that flows through the gate when a voltage is applied. Alternatively, or in addition to ZnO nanorods, films or nanostructure type metal oxides including TiO2, ITO, ZnO, WO3 and AZO can be used. The transistor is preferably a high electron mobility transistor (HEMT).

Abstract: Reliability of a semiconductor device is improved. In a method of manufacturing a semiconductor device, nitrogen is introduced into a surface of a substrate and a sacrificial film is formed on the surface in a field effect transistor formation region different from a memory transistor formation region. Subsequently, the sacrificial film is removed to remove the nitrogen introduced in the surface of the substrate in the field effect transistor formation region.

Abstract: A method of making an electrode for an organic electronic device comprises the steps of depositing an ink on a light emitting layer, and drying said ink to form said electrode. The ink comprises conductive metal or carbon particles, a binder and a hydrocarbon solvent selected from 1,1?-bicyclohexyl, cis-decalin trans-decaiin or n-undecane.

Abstract: The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed microelectronics package includes a module substrate, a first die with a first coupling component, a second die with a second coupling component, and a first mold compound. The first die is attached to the module substrate. The first mold compound resides over the module substrate, surrounds the first die, and extends above an upper surface of the first die to define a first opening. Herein, the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first die in X-direction and Y-direction. The second die is stacked with the first die and in the first opening, such that the second coupling component is mirrored to the first coupling component.

Abstract: A vertical FET with asymmetrically positioned source region and drain region is provided. The source region of the vertical FET is separated from a gate electrode by a gate dielectric and the drain region of the vertical FET is separated from the gate electrode by a drain spacer formed therebetween.

Abstract: A method for producing a bonded SOI wafer, by ion implantation delamination to fabricate a bonded SOI wafer having a BOX layer and a SOI layer on a base wafer. After performing flattening heat treatment in an argon gas-containing atmosphere, sacrificial oxidation treatment adjusts the film thickness of the SOI layer, wherein the film thickness of the BOX layer is 500 nm or more. A sacrificial oxide film is formed so the relationship between the film thickness of the SOI layer on the sacrificial oxidation treatment is performed. The film thickness of the sacrificial oxide film formed by the sacrificial oxidation treatment satisfies 0.9d>t>0.45d. A method for producing a bonded SOI wafer can prevent the generation of particles from the outermost peripheral part, which is the form of an overhang by flattening heat treatment, of a SOI layer in the production of a bonded SOI wafer.

Abstract: The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed microelectronics package includes a module substrate, a first die with a first coupling component, a second die with a second coupling component, and a first mold compound. The first die is attached to the module substrate. The first mold compound resides over the module substrate, surrounds the first die, and extends above an upper surface of the first die to define a first opening. Herein, the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first die in X-direction and Y-direction. The second die is stacked with the first die and in the first opening, such that the second coupling component is mirrored to the first coupling component.

Abstract: According to one embodiment, a value of a film thickness of a processing object disposed above a substrate is obtained. Then, a wavelength that provides a highest degree of intensity of signal light reflected when the signal light is incident onto the processing object having the value of the film thickness, based on wavelength selection reference information is selected. Then, a first instruction performing an alignment process to the substrate by use of signal light having a wavelength thus selected is generated. The wavelength selection reference information is information that includes a correlation between values of the film thickness of the processing object and degrees of intensity of the signal light, with respect to a plurality of wavelengths.

Abstract: The present disclosure provides a method for manufacturing a thin film transistor comprising, forming a pattern of an active layer on a substrate through a patterning process; performing ion doping to a channel region of the active layer; forming a gate insulating layer; forming a pattern of a gate through the patterning process; performing ion doping to a source contact region and a drain contact region of the active layer; forming an interlayer insulating layer; and performing laser annealing to the active layer, so as to make the active layer crystallize and the ions doped in the channel region, the source contact region and the drain contact region of the active layer activate simultaneously. In this method, the crystallization of the active layer and the activation of the ions doped in the active layer are implemented in the same process, which reduces the process cost and improves the efficiency.