Abstract: Field-effect transistors are formed on a substrate having silicided elements including diffusion (source and drain) regions and polysilicon gates. The silicided surfaces of these elements have low ohmic resistance and are used to provide interconnection between contacts that are spaced from each other, thereby freeing routing areas for other interconnections. The diffusion regions of adjacent transistors have edges that face each other, and are formed with indentations which constitute portions of a substrate tap area. The low ohmic resistance of the silicided surfaces of the diffusion regions enables the substrate tap area to be cut out of the diffusion regions without degrading the electrical performance of the transistors, thereby providing a substantial reduction in the space required for the transistors on the substrate.

Abstract: CMOS power device (10) is provided. A tank region (62) is formed in a semiconductor substrate (60). A polysilicon gate layer (34) is disposed above the tank region (62) and defines a plurality of source and drain diffusion openings (38 and 36) having rounded inner corners (40). A plurality of backgate contact regions (42) are segmented and are formed in vacancies in a plurality of source regions (30).