Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding integrated semiconductor structure.

Abstract: A semiconductor memory device, adapted for storing plural bits per cell to be able to accomplish high storage density by a simplified structure, includes a plurality of first gate electrodes extending parallel to one another along one direction and a plurality of second gate electrodes extending in a direction of intersecting the first gate electrodes, in which a diffusion region is provided on each of a plurality of divisions demarcated in a matrix-like pattern by first and second electrodes on a substrate surface. One of the divisions, the four sides of which are defined by two neighboring first gate electrodes and two neighboring second gate electrodes, has four independently accessible bits, and is connected by a contact (CT) with a diffusion region in the division. There are provided a plurality of interconnections connected via contacts to the diffusion regions of other divisions in the plural matrix-like divisions lying on the line of extension of the aforementioned diagonal line.

Abstract: Silicon-oxide-nitride-oxide-silicon (SONOS) devices and methods of manufacturing the same are provided. According to one aspect, a SONOS device includes a semiconductor substrate having a first surface, a second surface of lower elevation than the first surface, and a third surface perpendicular and between the first and second surfaces; a tunnel dielectric layer on the semiconductor substrate; a charge trapping layer in a form of a spacer on the tunnel dielectric layer on the third surface; a charge isolation layer on the tunnel dielectric layer, which covers the charge trapping layer; a gate that extends over a portion of the first surface, over a portion of the second surface, and is adjacent to a portion of the third surface of the semiconductor substrate on the charge isolation layer; a first impurity region formed below the first surface and near the gate; and a second impurity region formed below the second surface, opposite the first impurity region.

Abstract: A graded composition, high dielectric constant gate insulator is deposited between a substrate and floating gate in a flash memory cell transistor. If the composition of the gate insulator is closer to the high-k material near the substrate, the electron barrier for hot electron injection will be lower. If the gate insulator is closer to the high-k material near the floating gate, the tunnel barrier can be lower at the floating gate.

Abstract: Dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Forming a layer of hafnium oxide by atomic layer deposition and forming a layer of a lanthanide oxide by electron beam evaporation, where the layer of hafnium oxide is adjacent and in contact with the layer of lanthanide, provides a dielectric layer with a relatively high dielectric constant as compared with silicon oxide. The dielectric can be formed as a nanolaminate of hafnium oxide and a lanthanide oxide.

Abstract: A method for fabricating improved integrated circuit devices. The method enables selective hardening of gate oxide layers and includes providing a semiconductor substrate having a gate oxide layer formed thereover. A resist is then formed over the gate oxide layer and patterned to expose one or more areas of the gate oxide layer which are to be hardened. The exposed portions of the gate oxide layer are then hardened using a true remote plasma nitridation (RPN) scheme or a high-density plasma (HDP) RPN scheme. Because the RPN scheme used in the method of the present invention runs at low temperature, the patterned resist remains stable through the RPN process, and those areas of gate oxide layer which are exposed by the patterned resist are selectively hardened by the RPN treatment, while those areas covered by the patterned resist remain unaffected.

Abstract: A method of fabricating gates is provided. A first sacrificial layer having a first and a second gate openings therein is formed on a substrate. Next, a gate dielectric layer is formed on the substrate exposed by the first sacrificial layer. Thereafter, a second sacrificial layer is filled in the first and second gate openings. The second sacrificial layer in the first gate opening is removed, and then a first conductive layer is filled in the first gate opening as a gate of a MOS transistor of a first conductivity type. Then, the second sacrificial layer in the second gate opening is removed. A second conductive layer is filled in the second gate opening as a gate of a MOS transistor of a second conductivity type, and the first sacrificial layer is removed.

Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor includes a gate insulating structure comprised of a first conducting oxide layer comprised of indium oxide compounds positioned immediately on top of the compound semiconductor structure, and a second insulating layer comprised of either gallium oxygen and rare earth elements or gallium sulphur and rare earth elements positioned immediately on top of said first layer.

Abstract: A method for forming a nitrided tunnel oxide layer is described. A silicon oxide layer as a tunnel oxide layer is formed on a semiconductor substrate, and a plasma nitridation process is performed to implant nitrogen atoms into the silicon oxide layer. A thermal drive-in process is then performed to diffuse the implanted nitrogen atoms across the silicon oxide layer.

Abstract: A semiconductor device comprises a semiconductor substrate, an N-channel MISFET and a P-channel MISFET provided on the semiconductor substrate, each of the N- and P-channel MISFETs being isolated by an isolation region and having a gate insulating film, a first gate electrode film provided on the gate insulating film of the N-channel MISFET and composed of a first metal silicide, a second gate electrode film provided on the gate insulating film of the P-channel MISFET and composed of a second metal silicide made of a second metal material different from a first metal material composing the first metal silicide, and a work function of the first gate electrode film being lower than that of the second gate electrode film.

Abstract: A semiconductor device provides a gate structure that includes a conductive portion and a high-k dielectric material formed beneath and along sides of the conductive material. An additional gate dielectric material such as a gate oxide may be used in addition to the high-k dielectric material. The method for forming the structure includes forming an opening in an organic material, forming the high-k dielectric material and a conductive material within the opening and over the organic material then using chemical mechanical polishing to remove the high-k dielectric material and conductive material from regions outside the gate region.

Abstract: A self-aligned conductive spacer process for fabricating sidewall control gates on both sides of a floating gate for high-speed RAM applications, which can well define dimensions and profiles of the sidewall control gates. A conductive layer is formed on the dielectric layer to cover a floating gate patterned on a semiconductor substrate. Oxide spacer are formed on the conductive layer adjacent to the sidewalls of the floating gate. Performing an anisotropic etch process on the conductive layer and using the oxide spacers as a hard mask, a conductive spacers are self-aligned fabricated at both sides of the floating gate, serving as sidewall control gates.

Abstract: A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.

Abstract: The present invention provides a substrate having thereon a patterned small molecule organic semiconductor layer. The present invention also provides a method and a system for the production of the substrate having thereon a patterned small molecule organic semiconductor layer. The substrate with the patterned small molecule organic semiconductor layer is prepared by exposing a region of a substrate having thereon a film of a precursor of a small organic molecule to energy from an energy source to convert the film of a precursor of a small organic molecule to a patterned small molecule organic semiconductor layer.

Abstract: A method for forming multiple gate insulators on a strained semiconductor heterostructure, including the steps of oxidation and deposition.

Abstract: A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and is disposed under the gate electrode. The insulating material can be provided either as a layer or distributed within a gate dielectric material disposed under the gate electrode.

Abstract: A method for making a semiconductor device is described. That method includes forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. The dielectric layer is modified so that it will be compatible with a gate electrode to be formed on the dielectric layer, and then a gate electrode is formed on the dielectric layer.

Abstract: The silicon oxide film (106) and silicon nitride film (107) are formed by microwave plasma processing with a radial line slot antenna.

Abstract: A semiconductor device manufacturing method is provided including: forming a first impurity layer that becomes first wells in a high breakdown voltage transistor forming region in a semiconductor layer; forming a second impurity layer that becomes offset regions in the high breakdown voltage transistor forming region; forming the first wells and the offset regions by diffusing impurities of the first and second impurity layers by heat treating the semiconductor layer; forming element isolation regions by a trench element isolation method in the semiconductor layer, after forming the first wells and the offset regions; forming first gate dielectric layers in the high breakdown voltage transistor forming region; forming second wells in a low voltage driving transistor forming region in the semiconductor layer; forming second gate dielectric layers in the low voltage driving transistor forming region; and forming gate electrodes in the high breakdown voltage transistor forming region and the low voltage driving

Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer that contacts a metal oxide layer. The metal oxide layer is generated by forming a metal layer, then oxidizing the metal layer.

Abstract: Consistent with an example embodiment according to the invention, a material for the intermediate layer is chosen which can be selectively etched with respect to the dielectric layer. Before the deposition of the first conductor layer, the intermediate layer is removed at the location of the first channel region, and after the deposition of the first conductor layer and the removal thereof outside the first channel region and before the deposition of the second conductor layer, the intermediate layer is removed at the location of the second channel region. Thus, field effect transistors (FETs) are obtained in a simple manner and without damage to their gate dielectric. Preferably, a further intermediate layer is deposited on the intermediate layer which can be selectively etched with respect thereto.

Abstract: A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on the high-k gate dielectric layer, a second metal layer is formed on the first metal layer. At least part of the second metal layer is removed from above the dielectric layer using a polishing step, and additional material is removed from above the dielectric layer using an etch step.

Abstract: A semiconductor device and a method for forming it are described. The semiconductor device comprises a metal NMOS gate electrode that is formed on a first part of a substrate, and a silicide PMOS gate electrode that is formed on a second part of the substrate.

Abstract: In a metal gate replacement process, a cup-shaped gate metal oxide dielectric may have a vertical portion that may be exposed to a silicon ion implantation. As a result of the implantation, the dielectric constant of a vertical portion may be reduced, reducing fringe capacitance.

Abstract: A method for manufacturing an integrated circuit comprising a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor by covering the p-type field effect transistor with a mask, and oxidizing a portion of a gate polysilicon of the n-type field effect transistor, such that tensile mechanical stresses are formed within a channel of the n-type field effect transistor.

Abstract: An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric region formed over a channel region. A doped region is formed between a top portion and a bottom portion of the dielectric region. This doped region includes a suitable electron affinity material. A gate electrode is connected with the top of the dielectric region. In some embodiments, suitable electron affinity materials are introduced into the doped region using implantation techniques. In another embodiment, the electron affinity material is introduced into the doped region using plasma treatment of the dielectric region and the redeposition of additional dielectric material on top of the dielectric region and doped region.

Abstract: An electronic component is disclosed having a first layer of metallically conductive material, a second layer of semiconductor material, and a third layer between the first and second layers. The third layer comprises a dielectric and at least inhibits charge carrier transport both from the first to the second layer and also from the second to the first layer. The dielectric comprises praseodymium oxide of the form Pr2O3 in predominantly single crystal phase, and the second layer comprises silicon with a (001)- or with a (111)-crystal orientation at an interface with the third-layer.

Abstract: A semiconductor memory device which more reliably retains electrons trapped in its charge-trapping regions. A high-dielectric gate insulating film is grown on a semiconductor substrate. This gate insulating film is composed of first and second oxides, where the second oxide has a smaller bandgap than that of the first oxide and is scattered in dot-like form, surrounded by the first oxide. The memory cell is programmed by injecting electrons into a local potential minimum that is produced due to the bandgap difference between the phase-separated first and second oxides.

Abstract: A metal gate transistor may include a metal layer over a high dielectric constant dielectric layer. The dielectric layer abstracts electronegativity from said metal layer, altering its workfunction. The workfunction of the metal layer may be set to compensate for the dielectric layer abstraction.

Abstract: Aluminum oxide is deposited by atomic layer deposition to form a high-k dielectric for the interpoly dielectric layer of a non-volatile memory device. The increased capacitive coupling can allow a thicker oxide layer to be used between the floating gate and the control gate, resulting in improved reliability and longer lifetime of the memory cells fabricated according to this invention.

Abstract: The present invention relates to a method of selectively depositing an organic semiconductor material and a method of manufacturing an organic semiconductor thin film transistor array. Since the thin film transistor array is formed by locally performing a plasma process on a substrate before depositing an organic semiconductor active layer on the substrate, the organic semiconductor material is deposited on only the organic semiconductor active layer having an island shape. Therefore, it is not necessary to use a shadow mask method or a photolithography method to manufacture an active matrix array. Accordingly, the present invention has advantages in that it is possible to obtain a high resolution thin film transistor array and to prevent characteristics of the thin film transistors in the array from being deteriorated.

Abstract: In a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixedly mounted on a chip, a silicide layer is formed on the surfaces of the source and the drain of a MISFET of a direct peripheral circuit of the DRAM, the surfaces of the source and the drain of a MISFET of an indirect peripheral circuit of the DRAM, and the surfaces of the source and the drain of a MISFET of the logic integrated circuit, and the silicide layer is not formed on the surfaces of the source and the drain of a memory cell selective MISFET of the memory cell of the DRAM.

Abstract: A field effect semiconductor device comprising a high permittivity silicate gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A metal silicate gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Silicate layer 36 may be, e.g., hafnium silicate, such that the dielectric constant of the gate dielectric is significantly higher than the dielectric constant of silicon dioxide. However, the silicate gate dielectric may also be designed to have the advantages of silicon dioxide, e.g. high breakdown, low interface state density, and high stability. The present invention includes methods for depositing both amorphous and polycrystalline silicate layers, as well as graded composition silicate layers.

Abstract: A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

Abstract: A dielectric layer (50) is formed over a semiconductor (10) that contains a first region (20) and a second region (30). A polysilicon layer is formed over the dielectric layer (50) and over the first region (20) and the second region (30). The polysilicon layer can comprise 0 to 50 atomic percent of germanium. A metal layer is formed over the polysilicon layer and one of the regions and reacted with the underlying polysilicon layer to form a metal silicide or a metal germano silicide. The polysilicon and metal silicide or germano silicide regions are etched to form transistor gate regions (60) and (90) respectively. If desired a cladding layer (100) can be formed above the metal gate structures.

Abstract: A method for manufacturing a semiconductor device includes forming a first insulating film on a substrate, forming a second insulating film on the first insulating film, and forming a gate electrode on the second insulating film. Forming the second insulating film includes supplying film-forming materials and adsorbing the film-forming materials on the first insulating film, purging the film-forming materials that have not been adsorbed, supplying oxidants to oxidize the adsorbed film-forming materials, and purging the oxidants that have not contributed to oxidization. Forming the second insulating film is repeated in cycles, continuously, and the purging time of the oxidants in an initial number of the cycles is longer than the purging time of the oxidants in cycles following the initial number of cycles.

Abstract: Methods related to formation of a gate electrode are disclosed that employ a conductive hard mask as a protective layer during a photoresist removal process. In preferred embodiments, the conductive hard mask includes a metal containing conductor or a metal silicide. The invention prevents process damage on the gate dielectric during wet and/or dry resist strip, and since the conductive hard mask cannot be etched in typical resist strip chemistries, the invention also protects a metal electrode under the hard mask. The steps disclosed allow creation of a multiple work function metal gate electrode, or a mixed metal and polysilicon gate electrode, which do not suffer from the problems of the related art.

Abstract: There is disclosed a method of manufacturing a semiconductor device comprising forming a diffusion region containing arsenic impurity at a concentration of 1×1020 cm?3 or more in an element region of Si substrate which is isolated by an element isolating insulation film with a gate electrode being employed as a mask, depositing Ni metal all over the substrate, heat-treating the substrate at a temperature of less than 400° C., thereby forming a nickel silicide film containing Ni2Si on the diffusion region, removing unreacted Ni metal deposited on the element isolating insulation film, heat-treating the substrate at a temperature of 450° C. or more, thereby forming an NiSi film having a arsenic compound layer on the surface thereof, removing the arsenic compound layer by an alkaline liquid, depositing an interlayer insulating film the entire surface of the substrate, and forming a wiring layer piercing through the interlayer insulating film.

Abstract: Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic array includes a first logic and a second logic plan having a number of logic cells arranged in rows and columns that are interconnected to produce a number of logical outputs such that the in service programmable logic array implements a logical function. The logic cell includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5 and/or a Perovskite oxide tunnel barrier.

Abstract: A method for forming a semiconductor device (10) creates a dielectric layer (18) with high dielectric constant. An interfacial layer (14) is formed over a semiconductor substrate (12). A dielectric layer (16) is formed over the interfacial layer, wherein the dielectric layer has a high dielectric constant (K). The dielectric layer is thinned, such as by etching or chemical mechanical polishing, wherein a thickness of the thinned dielectric layer is less than a thickness of the dielectric layer prior to thinning. In one form, the method is used to form a transistor having a gate electrode layer formed over the thinned dielectric layer and source/drain diffusions (24, 26) within the semiconductor substrate.

Abstract: According to one exemplary embodiment, a method for forming a field-effect transistor on a substrate comprises a step of forming a buffer layer on the substrate, where the buffer layer comprises ALD silicon dioxide. The buffer layer can be formed by utilizing a silicon tetrachloride precursor in an atomic layer deposition process, for example. The buffer layer comprises substantially no pin-hole defects and may have a thickness, for example, that is less than approximately 5.0 Angstroms. The method further comprises forming a high-k dielectric layer over the buffer layer. The high-k dielectric layer may be, for example, hafnium oxide, zirconium oxide, or aluminum oxide. According to this exemplary embodiment, the method further comprises forming a gate electrode layer over the high-k dielectric layer. The gate electrode layer may be polycrystalline silicon, for example.

Abstract: A non-volatile memory is provided. The memory comprises a substrate, a dielectric layer, a conductive layer, an isolation layer, a buried bit line, a tunneling dielectric layer, a charge trapping layer, a barrier dielectric layer and a word line. Wherein, the dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. The isolation layer is disposed on the substrate and adjacent to the dielectric layer and the conductive layer. The buried bit line is disposed in the substrate and underneath the isolation layer. The tunneling dielectric layer is disposed on both the substrate and the sidewalls of the conductive layer and the isolation layer. The charge trapping layer is disposed on the tunneling dielectric layer and the barrier dielectric layer is disposed on the charge trapping layer. The word line is disposed on the substrate, crisscrossing with the buried bit line.

Abstract: A flash memory cell transistor and a method for fabricating the same compensates a work function difference of a pMOS and a nMOS with a triple gate insualting film by using electron density trapped in a pMOS gate insulating film. The flash memory cell transistor comprises a p-well region and a n-well region. The nMOS region comprises a nMOS channel ion-implantation region on the p-well region, a second gate oxide film on the nMOS channel ion-implantation region and a first n+ polysilicon gate electrode on the second gate oxide film. The pMOS region comprises a pMOS channel ion-implantation region on the n-well region, a first gate oxide film, an insulating film having an electron trap and the second gate oxide film which are sequentially formed on the pMOS channel ion-implantation region, and a second n+ polysilicon gate electrode on the second gate oxide film.

Abstract: Gate stacks with sidewall spacers having improved profiles to suppress or eliminate void formation between the gate stacks during gap-filling is disclosed, along with a method of forming the gate structures over a semiconductor substrate. A gate dielectric layer is formed on a semiconductor substrate. Then, a gate stack 24 having a sidewall is formed over the gate dielectric layer. The gate stack 24 comprises a conductive layer 28 and a hard mask 30 overlying the conductive layer 28. A liner 32 is selectively deposited over the gate stack 24 such that the liner 32 is deposited on the hard mask 30 at a rate lower than the rate of deposition on the conductive layer 28. Thus, the liner 32 is substantially thinner on the hard mask 30 than on the conductive layer 28. A nitride spacer is formed over 34 the liner 32. A PMD layer is formed over the resultant structure, filling the gaps between adjacent gate stacks and substantially free of voids.

Abstract: An etch resistant liner covering sidewalls of a transistor gate stack and along a portion of the substrate at a base of the transistor gate stack. The liner prevents silicide formation on the sidewalls of the gate stack, which may produce electrical shorting, and determines the location of silicide formation within source and drain regions within the substrate at the base of the transistor gate stack. The liner also covers a resistor gate stack preventing silicide formation within or adjacent to the resistor gate stack.

Abstract: A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal process chamber. The technique can be used, for example, in the formation of various elements in an integrated circuit, including gate dielectric films as well as capacitive elements. The tight temperature control provided by the RTP process allows the wet oxidation to be performed quickly so that the oxidizing species does not diffuse significantly through the dielectric film and diffuse into an underlying layer. In the case of capacitive elements, the technique also can help reduce the leakage current of the dielectric film without significantly reducing its capacitance.

Abstract: Memory cells are formed by preferably cylindrical recesses at the main surface of a semiconductor substrate, containing a memory layer sequence at sidewalls and a gate electrode and being provided with upper and lower source/drain regions connected in columns to first and second bit lines. Word lines are arranged above the first and second bit lines and connected to rows of gate electrodes. The vertical transistor structure facilitates a further shrinking of the cells and enables a required minimum effective channel length.

Abstract: A ZnO buffer layer having an electric conductivity of 1×10?9 S/cm or lower or alternatively a ZnO buffer layer having a diffraction peak of a crystal face other than (002) and (004) in X-ray diffraction is formed on a substrate by sputtering. A ZnO semiconductor layer is formed on the ZnO buffer layer. The ZnO semiconductor layer is formed under the condition that the flow rate ratio of an oxygen gas in a sputtering gas is lower than that in the formation of the ZnO buffer layer.

Abstract: The invention provides an integration scheme for a memory cell array, especially a charge-trapping memory cell array, comprising an architecture of local interconnects, which enables to avoid nitride insulations of wordline stacks and to produce CMOS devices of different structures and dimensions in standard technology along with the tinier memory cell transistors.

Abstract: In a capacitor of an MIM (Metal-Insulator-Metal) structure, a silicon-containing high dielectric film (e.g., a hafnium silicate film) containing a silicon atom, as well as a silicon-free high dielectric film (e.g., a tantalum oxide film) containing no silicon atom is interposed between a lower electrode film and an upper electrode film which are made of metal or metal compound. By adding the silicon-containing high dielectric film, a leak current can be suppressed and the change in capacitor capacity accompanied with the change in applied voltage can be reduced.