Doping Of Semiconductor Channel Region Beneath Gate Insulator (e.g., Threshold Voltage Adjustment, Etc.) Patents (Class 438/217)
  • Patent number: 10692731
    Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate having a first region and a second region; forming a first filling layer on the first region of the base substrate and a first hard mask layer on the first filling layer; performing a first treatment process on the second region of the base substrate using the first hard mask layer and the first filling layer as a mask; forming a second filling layer on the first region of the base substrate and a second mask on at least the second filling layer; removing the first hard mask layer and the first filling layer to expose the first region of the base substrate and to pattern the second hard mask layer on the second filling layer; and performing a second treatment process on the first region of the base substrate.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: June 23, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Cheng Long Zhang, Shi Liang Ji
  • Patent number: 10629451
    Abstract: Cyclic etch methods comprise the steps of: i) exposing a SiN layer covering a structure on a substrate in a reaction chamber to a plasma of hydrofluorocarbon (HFC) to form a polymer layer deposited on the SiN layer that modifies the surface of the SiN layer, the HFC having a formula CxHyFz where x=2-5, y>z, the HFC being a saturated or unsaturated, linear or cyclic HFC; ii) exposing the polymer layer deposited on the SiN layer to a plasma of an inert gas, the plasma of the inert gas removing the polymer layer deposited on the SiN layer and the modified surface of the SiN layer on an etch front; and iii) repeating the steps of i) and ii) until the SiN layer on the etch front is selectively removed, thereby forming a substantially vertically straight SiN spacer comprising the SiN layer on the sidewall of the structure.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: April 21, 2020
    Assignee: American Air Liquide, Inc.
    Inventors: Xiangyu Guo, James Royer, Venkateswara R. Pallem, Nathan Stafford
  • Patent number: 10504950
    Abstract: In order to improve the performance of a solid-state imaging device, the solid-state imaging device has a pixel including a photoelectric conversion unit and a transfer transistor, and fluorine is introduced to a gate electrode and a drain region (extension region and n+-type semiconductor region) of the transfer transistor included in the pixel.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: December 10, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Kamino, Fumitoshi Takahashi, Yotaro Goto
  • Patent number: 9960086
    Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having doping region self-aligned with a fin reveal position. A plurality of fins of a transistor is formed. A nitride cap layer on the plurality of fins is formed. An N-type doped region in a first portion of the plurality of fins. A P-type doped region in a second portion of the plurality of fins. A shallow trench isolation (STI) fill process for depositing an STI material on the plurality of fins. A fin reveal process for removing the STI material to a predetermined level. A cap strip process for removing the nitride cap layer for forming a fin reveal position that is self-aligned with the P-type and N-type doped regions.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: May 1, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mira Park, Kwan-Yong Lim, Steven Bentley, Amitabh Jain
  • Patent number: 9748145
    Abstract: Semiconductor device fabrication methods are provided which include: providing a structure with at least one region and including a dielectric layer disposed over a substrate; forming a multilayer stack structure including a threshold-voltage adjusting layer over the dielectric layer, the multilayer stack structure including a first threshold-voltage adjusting layer in a first region of the at least one region, and a second threshold-voltage adjusting layer in a second region of the at least one region; and annealing the structure to define a varying threshold voltage of the at least one region, the annealing facilitating diffusion of at least one threshold voltage adjusting species from the first threshold-voltage adjusting layer and the second threshold-voltage adjusting layer into the dielectric layer, where a threshold voltage of the first region is independent of the threshold voltage of the second region.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: August 29, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Balaji Kannan, Unoh Kwon, Siddarth Krishnan, Takashi Ando, Vijay Narayanan
  • Patent number: 9666483
    Abstract: An integrated circuit including a first transistor having a first gate dielectric layer with a first thickness. The integrated circuit also includes a second transistor having a second gate dielectric layer with a second thickness and the second transistor is configured to electrically connect to the first transistor. The integrated circuit also includes a third transistor having a third gate dielectric layer with a third thickness and the third transistor is configured to electrically connect to at least one of the first transistor or the second transistor. The first thickness, the second thickness and the third thickness of the integrated circuit are all different.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: May 30, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hung Lu, Song-Bor Lee, Ching-Kun Huang, Ching-Chen Hao
  • Patent number: 9607903
    Abstract: A method for forming field effect transistors comprises forming a first dummy gate stack over a first fin, forming a second dummy gate stack over a second fin, depositing a first layer of spacer material on the first dummy gate stack, the first fin, the second dummy gate stack, and the second fin, patterning a first masking layer on the first dummy gate stack and the first fin, etching to remove portions of the first layer of spacer material and form a spacer adjacent to the second dummy gate stack, removing the first masking layer, epitaxially growing a silicon material on the second fin, depositing a layer of oxide material on the first layer of spacer material, the first epitaxial material and the second dummy gate stack, and depositing a second layer of spacer material on the layer of oxide material.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: March 28, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Rama Kambhampati, Junli Wang, Ruilong Xie, Tenko Yamashita
  • Patent number: 9590105
    Abstract: A semiconductor device and methods of formation are provided. The semiconductor device includes a first metal alloy over a first active region of a fin and a second metal alloy over a second active region of the fin. A conductive layer is over a channel region of the fin. A semiconductive layer is over the conductive layer. The conductive layer over the channel region suppresses current leakage and the semiconductive layer over the conductive layer reduces electro flux from a source to a drain, as compared to a channel region that does not have such a conductive layer or a semiconductive layer over a conductive layer. The semiconductor device having the first metal alloy as at least one of the source or drain requires a lower activation temperature than a semiconductor device that does not have a metal alloy as a source or a drain.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: March 7, 2017
    Assignees: National Chiao-Tung University, Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chao-Hsin Chien, Cheng-Ting Chung, Che-Wei Chen
  • Patent number: 9484451
    Abstract: A method for fabricating a MOSFET having an active area and an edge termination area is disclosed. The method includes forming a first plurality of implants at the bottom of trenches located in the active area and in the edge termination area. A second plurality of implants is formed at the bottom of the trenches located in the active area. The second plurality of implants formed at the bottom of the trenches located in the active area causes the implants formed at the bottom of the trenches located in the active area to reach a predetermined concentration. In so doing, the breakdown voltage of both the active and edge termination areas can be made similar and thereby optimized while maintaining advantageous RDson.
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: November 1, 2016
    Assignee: VISHAY-SILICONIX
    Inventors: Qufei Chen, Kyle Terrill, Sharon Shi
  • Patent number: 9306013
    Abstract: A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: April 5, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey A. Babcock, Alexei Sadovnikov
  • Patent number: 9117675
    Abstract: A semiconductor device production method includes: forming a protection film on a semiconductor substrate; forming a first resist pattern on the protection film; implanting a first impurity ion into the semiconductor substrate using the first resist pattern as a mask; removing the first resist pattern; forming on the surface of the semiconductor substrate a chemical reaction layer that takes in surface atoms from the semiconductor substrate through chemical reaction, after the removing of the first resist pattern; removing the chemical reaction layer formed on the semiconductor substrate and removing the surface of the semiconductor substrate, after the forming of the chemical reaction layer; and growing a semiconductor layer epitaxially on the surface of the semiconductor substrate, after the removing of the surface of the semiconductor substrate.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: August 25, 2015
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Junji Oh, Masanori Terahara
  • Patent number: 9082789
    Abstract: An integrated circuit device and method for manufacturing an integrated circuit device is disclosed. The integrated circuit device comprises a core device and an input/output circuit. Each of the core device and input/output circuit includes a PMOS structure and an NMOS structure. Each of the PMOS includes a p-type metallic work function layer over a high-k dielectric layer, and each of the NMOS structure includes an n-type metallic work function layer over a high-k dielectric layer. There is an oxide layer under the high-k dielectric layer in the input/output circuit.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: July 14, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hung Huang, Yu-Hsien Lin, Ming-Yi Lin, Jyh-Huei Chen
  • Patent number: 9082699
    Abstract: A method of manufacturing a semiconductor device having a twin well structure is provided. The method includes ion-implanting of a first conductivity type impurity in a first region and a second region of a semiconductor substrate, the first and second regions being located adjacent to each other; forming a first resist pattern to cover the first region of the semiconductor substrate and to expose the second region of the semiconductor substrate; ion-implanting of a second conductivity type impurity at a higher concentration compared to the first conductivity type impurity in the second region of the semiconductor substrate, with the first resist pattern being used as a mask; and thermal-diffusing the first conductivity type of impurity and the second conductivity type of impurity.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: July 14, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobuyuki Suzuki, Tomohiro Migita, Satoshi Suzuki, Masanobu Ohmura, Takatoshi Nakahara, Keiichi Sasaki
  • Patent number: 9006789
    Abstract: A semiconductor device including a first lattice dimension III-V semiconductor layer present on a semiconductor substrate, and a second lattice dimension III-V semiconductor layer that present on the first lattice dimension III-V semiconductor layer, wherein the second lattice dimension III-V semiconductor layer has a greater lattice dimension than the first lattice dimension III-V semiconductor layer, and the second lattice dimension III-V semiconductor layer has a compressive strain present therein. A gate structure is present on a channel portion of the second lattice dimension III-V semiconductor layer, wherein the channel portion of second lattice dimension III-V semiconductor layer has the compressive strain. A source region and a drain region are present on opposing sides of the channel portion of the second lattice dimension III-V semiconductor layer.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9000501
    Abstract: A semiconductor integrated circuit includes a first semiconductor substrate in which a part of an analog circuit is formed between the analog circuit and a digital circuit which subjects an analog output signal output from the analog circuit to digital conversion; a second semiconductor substrate in which the remaining part of the analog circuit and the digital circuit are formed; and a substrate connection portion which connects the first and second semiconductor substrates to each other. The substrate connection portion transmits an analog signal which is generated by a part of the analog circuit of the first semiconductor substrate to the second semiconductor substrate.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: April 7, 2015
    Assignee: Sony Corporation
    Inventor: Yoshiharu Kudoh
  • Patent number: 8987081
    Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: March 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Kazunobu Ota, Hirokazu Sayama, Hidekazu Oda
  • Patent number: 8969969
    Abstract: Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Victor W. C. Chan, Narasimhulu Kanike, Huiling Shang, Varadarajan Vidya, Jun Yuan, Roger Allen Booth, Jr.
  • Patent number: 8969149
    Abstract: A structure is provided that includes at least one multilayered stacked semiconductor material structure located on a semiconductor substrate and at least one sacrificial gate material structure straddles a portion of the at least one multilayered stacked semiconductor structure. The at least one multilayered stacked semiconductor material structure includes alternating layers of sacrificial semiconductor material and semiconductor nanowire template material. End segments of each layer of sacrificial semiconductor material are then removed and filled with a dielectric spacer. Source/drain regions are formed from exposed sidewalls of each layer of semiconductor nanowire template material, and thereafter the at least one sacrificial gate material structure and remaining portions of the sacrificial semiconductor material are removed suspending each semiconductor material.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 8962410
    Abstract: A first transistor and a second transistor are formed with different threshold voltages. A first gate is formed over the first region of a substrate for a first transistor and a second gate over the second region for a second transistor. The first region is masked. A threshold voltage of the second transistor is adjusted by implanting through the second gate while masking the first region. Current electrode regions are formed on opposing sides of the first gate and current electrode regions on opposing sides of the second gate.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: February 24, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Da Zhang, Konstantin V. Loiko, Spencer E. Williams, Brian A. Winstead
  • Patent number: 8962417
    Abstract: A semiconductor structure including a p-channel field effect transistor (pFET) device located on a surface of a silicon germanium (SiGe) channel is provided in which the junction profile of the source/drain region is abrupt. The abrupt source/drain junctions for pFET devices are provided by forming an N- or C-doped Si layer directly beneath a SiGe channel layer which is located above a Si substrate. A structure is provided in which the N- or C-doped Si layer (sandwiched between the SiGe channel layer and the Si substrate) has approximately the same diffusion rate for a p-type dopant as the overlying SiGe channel layer. Since the N- or C-doped Si layer and the overlying SiGe channel layer have substantially the same diffusivity for a p-type dopant and because the N- or C-doped Si layer retards diffusion of the p-type dopant into the underlying Si substrate, abrupt source/drain junctions can be formed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kern Rim, William K. Henson, Yue Liang, Xinlin Wang
  • Publication number: 20150041910
    Abstract: Integrated circuits and methods of fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a bulk silicon substrate that is lightly-doped with a first dopant type divided into a first device region and a second device region, and a well region that is lightly-doped with a second dopant type formed in the second device region. The integrate circuit further includes heavily-doped source/drain extension regions of the first dopant type aligned to a first gate electrode structure and heavily-doped source/drain extension regions of the second dopant type aligned to a second gate electrode structure, and an intermediately-doped halo region of the second dopant type formed underneath the first gate electrode structure and an intermediately-doped halo regions of the first dopant type underneath the second gate electrode structure. Still further, the integrated circuit includes heavily-doped source/drain regions.
    Type: Application
    Filed: August 7, 2013
    Publication date: February 12, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Stefan Flachowksy, Juergen Faul, Jan Hoentschel
  • Patent number: 8951866
    Abstract: A semiconductor device includes a semiconductor substrate including isolation regions defining first and second active regions having a first and second conductivity type, respectively, first threshold voltage control regions in predetermined regions of the first active region, wherein the first threshold voltage control regions have the first conductivity type and a different impurity concentration from the first active region, a first gate trench extending across the first active region, wherein portions of side bottom portions of the first gate trench adjacent to the respective isolation region are disposed at a higher level than a central bottom portion of the first gate trench, and the first threshold voltage control regions remain in the first active region under the side bottom portions of the first gate trench adjacent to the respective isolation region, and a first gate pattern. Methods of manufacturing such semiconductor devices are also provided.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mueng-Ryul Lee, Sang-Bae Yi
  • Patent number: 8951857
    Abstract: The present invention provides various methods for implanting ions in a semiconductor device that substantially compensate for a difference in threshold voltages between a central portion and edge portions of a substrate generated while performing uniform ion implantation to entire surfaces of a substrate. Other methods for fabricating a semiconductor device improve distribution of transistor parameters across a substrate by forming a nonuniform channel doping layer or by forming a nonuniform junction profile, across the substrate.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: February 10, 2015
    Assignee: Sk hynix Inc.
    Inventors: Young-Sun Sohn, Seung-Woo Jin, Min-Yong Lee, Kyoung-Bong Rouh
  • Patent number: 8941092
    Abstract: Disclosed are a method which improves the performance of a semiconductor element, and a semiconductor element with improved performance. The method for forming a semiconductor element structure includes a heterojunction forming step in which a heterojunction is formed between a strained semiconductor layer (21) in which a strained state is maintained, and relaxed semiconductor layers (23, 25). The heterojunction is formed by performing ion implantation from the surface of a substrate (50) which has a strained semiconductor layer (20) partially covered with a covering layer (30) on an insulating oxide film (40), and altering the strained semiconductor layer (20) where there is no shielding from the covering layer (30) to relaxed semiconductor layers (23, 25) by relaxing the strained state of the strained semiconductor layer (20), while maintaining the strained state of the strained semiconductor layer (21) where there is shielding from the covering layer (30).
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: January 27, 2015
    Assignee: Kanagawa University
    Inventor: Tomohisa Mizuno
  • Patent number: 8927361
    Abstract: Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Roger Allen Booth, Jr., Victor W. C. Chan, Narasimhulu Kanike, Huiling Shang, Varadarajan Vidya, Jun Yuan
  • Patent number: 8927363
    Abstract: A structure including nFET and pFET devices is fabricated by depositing a germanium-containing layer on a crystalline silicon layer. The crystalline silicon layer is converted to silicon germanium in the pFET region to provide a thin silicon germanium channel for the pFET device fabricated thereon. Silicon trench isolation is provided subsequent to deposition of the germanium-containing layer. There is substantially no thickness variation in the silicon germanium layer across the pFET device width. Electrical degradation near the shallow trench isolation region bounding the pFET device is accordingly avoided. Shallow trench isolation may be provided prior to or after conversion of the silicon layer to silicon germanium in the pFET region. The germanium-containing layer is removed from the nFET region so that an nFET device can be formed on the crystalline silicon layer.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek
  • Publication number: 20140370672
    Abstract: In a method for fabricating a semiconductor device, a first gate electrode and a second gate electrode are provided on a substrate, the first gate electrode and the second gate electrode being formed in a first region and a second region of the substrate, respectively. A conductive buffer layer is formed along sidewalls of the first gate electrode and the second gate electrode and on upper surfaces of the first gate electrode and second gate electrode. A first mask pattern covering the first region of the substrate on the buffer layer is formed. A first impurity region is formed in the substrate at sides of the second gate electrode using the first mask pattern as a mask of an ion implantation process.
    Type: Application
    Filed: January 31, 2014
    Publication date: December 18, 2014
    Inventors: Ju-Youn Kim, Sang-Duk Park, Jae-Kyung Seo, Kwang-Sub Yoon, In-Gu Yoon
  • Patent number: 8907423
    Abstract: A high withstand voltage transistor is formed in a high withstand voltage region, and a low withstand voltage transistor is formed in a low withstand voltage region in a method of manufacturing a semiconductor device. The method includes forming a thermal oxide film and a silicon nitride film over the surface of a silicon substrate; forming an opening to the thermal oxide film and the silicon nitride film in each of the high withstand voltage region and the low withstand voltage region; etching the silicon substrate to form trenches; burying a buried oxide film in each of the trenches; removing the thermal oxide film and the silicon nitride film; and forming a thick gate oxide film and a thin oxide film. The depth of a tapered portion of the trench in the low withstand voltage region is shallower than that in the high withstand voltage region.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Tadahiro Miwatashi
  • Patent number: 8906767
    Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: December 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yue-Der Chih, Jam-Wem Lee, Cheng-Hsiung Kuo, Tsung-Che Tsai, Ming-Hsiang Song, Hung-Cheng Sung, Hung Cho Wang
  • Publication number: 20140357028
    Abstract: A method for fabricating an integrated circuit includes forming a first gate electrode structure above a first active region and a second gate electrode structure above a second active region, forming a sacrificial spacer on sidewalls of the first and second gate electrode structures, and forming deep drain and source regions selectively in the first and second active regions by using the sacrificial spacer as an implantation mask. The method further includes forming drain and source extension and halo regions in the first and second active regions after removal of the sacrificial spacer and forming a fluorine implant region in the halo region of the first active region before or after formation of the drain and source extension and halo regions.
    Type: Application
    Filed: May 31, 2013
    Publication date: December 4, 2014
    Inventors: Nicolas Sassiat, Shiang Yang Ong, Ran Yan, Torben Balzer
  • Patent number: 8900918
    Abstract: Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Phaedon Avouris, Kuan-Neng Chen, Damon Farmer, Yu-Ming Lin
  • Patent number: 8877579
    Abstract: Methods of manufacturing semiconductor devices include providing a substrate including a NMOS region and a PMOS region, implanting fluorine ions into an upper surface of the substrate, forming a first gate electrode of the NMOS region and a second gate electrode of the PMOS region on the substrate, forming a source region and a drain region in portions of the substrate, which are adjacent to two lateral surfaces of the first gate electrode and the second gate electrode, respectively, and performing a high-pressure heat-treatment process on an upper surface of the substrate by using non-oxidizing gas.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon-kyun Song, Ha-jin Lim, Moon-han Park, Jin-ho Do
  • Patent number: 8871583
    Abstract: A non-planar JFET device having a thin fin structure is provided. A fin is formed projecting upwardly from or through a top surface of a substrate, where the fin has a first semiconductor layer portion formed from a first semiconductor material of a first conductivity type. The first semiconductor layer portion has a source region and a drain region, a channel region extending between the source region and the drain region. Two or more channel control regions are formed adjoining the channel region for generating charge depletion zones at and extending into the channel region for thereby controlling current conduction through the channel region. A gate is provided so as to adjoin and short together the at least two channel control regions from the outer sides of the channel control regions.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: October 28, 2014
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Mieno Fumitake
  • Patent number: 8859360
    Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: October 14, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kazunobu Ota, Hirokazu Sayama, Hidekazu Oda
  • Patent number: 8853025
    Abstract: An embodiment method of controlling threshold voltages in a fin field effect transistor (FinFET) includes forming a dummy gate over a central portion of a fin, the central portion of the fin disposed between exterior portions of the fin unprotected by the dummy gate, removing the exterior portions of the fin and replacing the exterior portions of the fin with an epitaxially-grown silicon-containing material, applying a spin-on resist over the dummy gate and the epitaxially-grown silicon-containing material and then removing the spin-on resist over the hard mask of the dummy gate, etching away the hard mask and a polysilicon of the dummy gate to expose a gate oxide of the dummy gate, the gate oxide disposed over the central portion of the fin, and implanting ions into the central portion of the fin through the gate oxide disposed over the central portion of the fin.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying Zhang, Ziwei Fang, Jeffrey Junhao Xu
  • Publication number: 20140273367
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment of a method for fabricating integrated circuits, a P-type gate electrode structure and an N-type gate electrode structure are formed overlying a semiconductor substrate. The gate electrode structures each include a gate electrode that overlies a gate dielectric layer and a nitride cap that overlies the gate electrode. Conductivity determining ions are implanted into the semiconductor substrate using the P-type gate electrode structure and the N-type gate electrode structure as masks to form a source region and a drain region for the P-type gate electrode structure and the N-type gate electrode structure. The nitride cap remains overlying the N-type gate electrode structure during implantation of the conductivity determining ions into the semiconductor substrate to form the source region and the drain region for the N-type gate electrode structure.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: GLOBALFOUNDRIES, INC.
    Inventors: Peter Javorka, Ralf Richter, Stefan Flachowsky
  • Publication number: 20140252485
    Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.
    Type: Application
    Filed: March 7, 2013
    Publication date: September 11, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai Hao, Sameer Pendharkar, Amitava Chatterjee
  • Patent number: 8829616
    Abstract: A semiconductor device and method of making same. The device includes a substrate comprising a semiconductor layer on an insulating layer, the semiconductor layer including a semiconductor body having a body contact region and an abutting switching region; a bridged gate over the semiconductor body, the bridged gate having a bridge gate portion and an abutting gate portion, the bridge gate portion comprising a multilayer first gate stack and the gate portion comprising a multilayer second gate stack comprising the gate dielectric layer on the semiconductor body; first and second source/drains formed in the switching region on opposite sides of the channel; and wherein a first work function difference between the bridge portion and the body contact region is different from a second work function difference between the gate portion and the channel region.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Anthony I-Chih Chou, Murshed M. Chowdhury, Arvind Kumar, Shreesh Narasimha
  • Patent number: 8829623
    Abstract: According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: a contact region; a select gate region; and a memory cell region; a first element isolation region formed in the contact region and having a first depth; a second element isolation region formed in the select gate region and having a second depth; and a third element isolation region formed in the memory cell region and having a third depth which is smaller than the first depth.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: September 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobutoshi Aoki, Takashi Izumida, Masaki Kondo, Fumitaka Arai
  • Patent number: 8822280
    Abstract: A first transistor includes a first impurity layer of a first conduction type formed in a first region of a semiconductor substrate, a first epitaxial semiconductor layer formed above the first impurity layer, a first gate insulating film formed above the first epitaxial semiconductor layer, a first gate electrode formed above the first gate insulating film, and first source/drain regions of a second conduction type formed in the first epitaxial semiconductor layer and in the semiconductor substrate in the first region.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: September 2, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Kazushi Fujita
  • Patent number: 8778753
    Abstract: A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: July 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinho Do, Hajin Lim, WeonHong Kim, Kyungil Hong, Moonkyun Song
  • Patent number: 8765544
    Abstract: An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes an enhanced well region to effectively increase a voltage at which punch-through occurs when compared to a conventional semiconductor device. The enhanced well region includes a greater number of excess carriers when compared to a well region of the conventional semiconductor device. These larger number of excess carriers attract more carriers allowing more current to flow through a channel region of the semiconductor device before depleting the enhanced well region of the carriers. As a result, the semiconductor device may accommodate a greater voltage being applied to its drain region before the depletion region of the enhanced well region and a depletion region of a well region surrounding the drain region merge into a single depletion region.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: July 1, 2014
    Assignee: Broadcom Corporation
    Inventor: Akira Ito
  • Patent number: 8759872
    Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the VT setting within a precise range. This VT set range may be extended by appropriate selection of metals so that a very wide range of VT settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low ?VT) and VDD, so that the body bias can be tuned separately from VT for a given device.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: June 24, 2014
    Assignee: SuVolta, Inc.
    Inventors: Reza Arghavani, Pushkar Ranade, Lucian Shifren, Scott E. Thompson, Catherine de Villeneuve
  • Patent number: 8753932
    Abstract: A memory cell having N transistors including at least one pair of access transistors, one pair of pull-down transistors, and one pair of pull-up transistors to form a memory cell, wherein N is an integer at least equal to six, wherein each of the access transistors and each of the pull-down transistors is a same one of an n-type or a p-type transistor, and each of the pull-up transistors is the other of an n-type or a p-type transistor, wherein at least one of the pair of the pull down transistors and the pair of the pull up transistors are asymmetric.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Leland Chang, Jeffrey W. Sleight
  • Patent number: 8748245
    Abstract: An integrated circuit fabricated on a semiconductor-on-insulator transferred layer is described. The integrated circuit includes an interconnect layer fabricated on the back side of the insulator. This interconnect layer connects active devices to each other through holes etched in the insulator. This structure provides extra layout flexibility and lower capacitance, thus enabling higher speed and lower cost integrated circuits.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: June 10, 2014
    Assignee: IO Semiconductor, Inc.
    Inventors: Michael A. Stuber, Stuart B. Molin, Chris Brindle
  • Patent number: 8741720
    Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: June 3, 2014
    Assignee: Intel Corporation
    Inventors: Giuseppe Curello, Ian R. Post, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark T. Bohr
  • Patent number: 8722486
    Abstract: When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Moreover, the well dopant species is implanted after the recessing, thereby avoiding undue dopant loss. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: May 13, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Maciej Wiatr, Roman Boschke, Peter Javorka
  • Patent number: 8697498
    Abstract: A method of manufacturing a Three Dimensional (3D) semiconductor memory device can be provided by forming at least one trench in a plate stack structure to divide the plate stack structure into a plurality of sub-plate stack structures between forming a plurality of vertical active patterns in the plate stack structure and forming pads of a stepped structure from the plate stack structure.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byong-hyun Jang, Dongchul Yoo, Chanjin Park, Hanmei Choi
  • Patent number: 8691653
    Abstract: A semiconductor structure and a manufacturing process thereof are disclosed. The semiconductor structure includes a substrate having a first conductive type, a first well having a second conductive type formed in the substrate, a doped region having the second conductive type formed in the first well, a field oxide and a second well having the first conductive type. The doped region has a first net dopant concentration. The field oxide is formed on a surface area of the first well. The second well is disposed underneath the field oxide and connected to a side of the doped region. The second well has a second net dopant concentration smaller than the first net dopant concentration.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: April 8, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih-Chia Hsu, Yu-Hsien Chin, Yin-Fu Huang
  • Patent number: 8680623
    Abstract: Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Frank, Arvind Kumar, Vijay Narayanan, Vamsi K. Paruchuri, Jeffrey Sleight