Abstract: A process for fabricating a bipolar transistor on a silicon-on-insulator substrate which includes etching a bipolar transistor area into the substrate, wherein the bipolar transistor area has substantially vertical sidewalls and a bottom, and forming a buried collector in bottom of the bipolar transistor area. Polysilicon sidewalls are formed adjacent to the vertical sidewalls in the bipolar transistor area, wherein the polysilicon sidewalls are connected to the buried collector. The polysilicon sidewalls are oxidized to form a layer of oxidized polysilicon. Oxide sidewalls are formed on the oxidized polysilicon sidewalls, and epitaxial silicon is formed to fill the bipolar transistor area. A base and an emitter are formed for the bipolar transistor, within the epitaxial barrier.

Abstract: A high performance, high voltage non-epi bipolar transistor including a substrate (12) with an n-type conductivity well (13) and an insulative layer (14) with first (15), second (17) and third (18) openings exposing the substrate in the well. A first p-type volume (19) surrounding the first and second openings (15, 17) beneath the insulative layer (14), and a second n-type volume (22) surrounding the third opening (18) beneath the insulative layer (14). A p-type intrinsic base (25) in the first opening (15) and in contact with the first volume (19). A p-type extrinsic base (30) in the second opening (17) and in contact with the first volume (19). An n-type collector (32) in the third opening (18) and in contact with the second volume (22), and an n-type emitter layer (27) in the first opening in overlying contact with the intrinsic base (25).

Abstract: A process for manufacturing a BiCMOS integrated circuit is implemented by adapting the masking and doping steps used in forming CMOS devices. Thus simultaneous formation of both CMOS and bipolar device structures eliminates the need for any additional masking or process steps to form bipolar device structures. Collector regions 20 of NPN transistors are formed simultaneously with N-wells 18. Collector regions of PNP transistors, if required, are formed simultaneously with P-wells 16. Base regions 24 of the bipolar transistors are formed using threshold voltage implant steps and/or lightly doped drain implant steps of PMOS transistors. Emitter regions 59 are formed, when using a single polysilicon CMOS process, simultaneously with the CMOS gates 72, 74. When employing a double polysilicon CMOS process, the emitter regions 59 are formed concurrently with the second polysilicon layer interconnect structure and/or source/drain regions 50,52 of NMOS transistors.

Abstract: A BiDMOS device in which a bipolar transistor and a DMOS transistor are formed on the same substrate, thereby resulting in a high degree of integration, and a method of fabricating the same using a reduced number of process steps. A high voltage operating characteristic is achieved because the gate of the DMOS transistor isolates the base and collector of the bipolar transistor. In addition, the junction capacitance between the bipolar base and collector regions is considerably reduced due to the isolation provided by the DMOS gate polysilicon.

Abstract: An IC voltage clamp and a process for forming the voltage clamp. The voltage clamp includes an MGFO device having an n-type source region, an n-type drain region, and a p-type field implant diffusion between the source and drain regions. The voltage clamp further employs a parasitic NPN device having a collector region coincident with the MGFO drain region, an emitter region coincident with the MGFO source region, and a base region formed by the substrate. A metal gate electrode overlies and is insulated from the field implant diffusion, but electrically connects the source and emitter regions to ground. An input electrode contacts the drain region so as to electrically connect the drain and collector regions to the input voltage of an integrated circuit. The field implant diffusion and drain/collector regions are formed by overlapping their masks, such that a lower breakdown voltage is achieved between the NPN collector and the substrate and field implant diffusion (the NPN base).

Abstract: To enable a high speed operation and to increase the current gain, the disclosed a method of manufacturing a semiconductor device, comprising the steps of: forming a first semiconductor layer with a first-conductivity type in a semiconductor substrate; forming a second semiconductor layer with a second-conductivity type different from the first-conductivity type on the first semiconductor layer; insulation separating the formed second semiconductor layer into a first semiconductor region and a second semiconductor region by an insulating film; changing the second semiconductor region to the first-conductivity type; forming a pattern of an insulating film or a photoresist film having a hole at a partial area of the first semiconductor region of the semiconductor substrate; and implanting first-conductivity type impurities and second-conductivity type impurities at the first semiconductor region, respectively by use of the formed pattern as a mask, to form a first-conductivity type impurity region contacting wi

Abstract: High energy implantation through varying vertical thicknesses of one or more films is used to form a vertically modulated sub-collector, which simultaneously reduces both the vertical and lateral components of parasitic collector resistance in a vertically integrated bipolar device. The need for a sinker implant or other additional steps to reduce collector resistance is avoided. The necessary processing modifications may be readily integrated into conventional bipolar or BiCMOS process flows.

Abstract: In an NPN bipolar transistor having a special structure in which each impurity region is formed by ion implantation, a width of a base region is significantly reduced, and therefore, current amplification factor hfe is increased, resulting in improvement in performance thereof. Furthermore, a Bi-CMOS transistor can be manufactured using a CMOS process. The use of the bipolar transistor having a special structure for a driving circuit allows implementation of a driving circuit having large driving force with slight increase in cost.

Abstract: An active pixel sensor cell that will convert a quantum of light energy to an electronic signal representing the amplitude of the quantum of light energy is disclosed. The active pixel sensor cell is immune to image blooming and has a reset operation to reduce image lag. An active pixel sensor has a photodiode, a bipolar transistor and a MOS transistor. The photodiode has a cathode connected to a power supply voltage source and an anode to the MOS transistor. The quantum of light energy will impinge upon the anode and generate electric charges within the photodiode. The MOS transistor will prevent the image blooming by disconnecting the anode of the photodiode from the base of the bipolar transistor and connecting the anode of the photodiode to MOS transistor to allow the electric charges in the photodiode to flow through the MOS transistor. The bipolar transistor will amplify the electrical charges to create the electronic signal. The active pixel sensor further includes a parasitic MOS transistor.

Abstract: An n-type buried layer and an n-type epitaxial layer that becomes a collector layer of a pnp transistor are formed on a semiconductor substrate. A well and the collector layer are formed. Ions of an n-type impurity are implanted through a photoresist mask, to form an intrinsic base layer of the pnp transistor and a PT-VT diffusion layer with punchthrough stopper and threshold control functions of a pMOSFET. Ions of a p-type impurity are implanted through a photoresist mask at a shallow implantation depth than the previous step, to form an intrinsic base layer of an npn transistor and a channel dope layer of the pMOSFET. A buried channel is formed under the gate of the pMOSFET. Therefore pMOSFETs with good characteristics can be obtained. In this way, the present invention achieves bipolar transistors and MOSFETs with good characteristics, without having to increase the number of fabrication steps and the number of photoresist masks.

Abstract: A method for making self-aligned sub-micrometer bipolar transistors and FETs on a substrate for BiFET and BiCMOS circuits was achieved using a novel LOCOS structure as a self-aligned implant mask. This LOCOS structure uses a silicon nitride mask comprised of stripes with well defined widths and spacings to form a punchthrough oxide mask of varying thicknesses over the emitter, base, and collector of the bipolar transistor, while providing a thick field oxide elsewhere on the substrate. The oxide mask serves as a self-aligned implant mask for implanting the emitter, base, and collector of the bipolar transistor. The nitride mask can be patterned concurrently to form an implant mask for the FET. A series of ion implants is then used to form the emitter, base, and collector without requiring separate photoresist masks. An array of nitride stripes with well defined widths and spacings can be used to make larger transistors, such as bipolar power transistors.

Abstract: A method of forming BiCMOS circuitry includes, i) conducting a first common second conductivity type implant into, a) a first substrate area to comprise a second conductivity type well for a first area first conductivity type FET, and b) a third substrate area to comprise one of a bipolar transistor second conductivity type collector or emitter region; ii) providing field oxide regions and active area regions within first, second and third areas of the substrate; iii) conducting a first common first conductivity type implant into, a) the second substrate area to comprise a first conductivity type channel stop region beneath field oxide in the second area, and b) the third substrate area to comprise the bipolar transistor base; and iv) conducting a second common second conductivity type implant into, a) at least one of the first or the second substrate areas to comprise at least one of a source/drain implant or a graded junction implant for at least one of the first or second conductivity type FETs, and b) the

Abstract: The method for making a charge coupled device includes: forming a semiconductor region 24 of a first conductivity type; forming gate regions 28 and 30 overlying and separated from the semiconductor region 24; forming clocked barrier implants 36 and 38 of a second conductivity type in the semiconductor region 24 and aligned to the gate regions 36 and 38; depositing a semiconductor layer 70 overlying and separated from the semiconductor region 24 and the gate regions 28 and 30; removing a portion of the semiconductor layer 70 leaving semiconductor side walls 40 and 42 coupled to the gate regions 28 and 30.

Abstract: A BiCMOS device and a manufacturing method thereof according to the present invention has a gate insulating layer of NMOSFET having non-uniform thickness. The thickness of the end portion of the gate insulating layer, which is near LDD regions, is thicker than that of center portion. Therefore, the GIDL and the gate-drain overlap capacitance is reduced. In addition, in case of the bipolar transistor of the BiCMOS device, there exists a portion of an oxide film below the side portion of the emitter polysilicon and over the side portions of the emitter region. Since this structure serves as a gate of field effect transistor, N- channel is produced in the emitter region when the emitter-base junction is reversely biased and thus the hot carrier reliability is improved.

Abstract: A technique for providing a design window for scaled technologies in which good electrostatic discharge/electrical over stress damage and optimum transistor operation can be achieved without the use of additional masks or design steps. The M, beta, and R.sub.sub parameters of the NMOS transistor 13 and associated parasitic npn transistor 10 are selected to provide the design window.

Abstract: In a BiMOS semiconductor device, emitter and base electrodes formed by polycrystalline Si of a bipolar transistor are isolated from each other by way of a sidewall and an insulator layer. As this insulator layer acts as an offset during the formation of the sidewall, its layer thickness can be made larger. Further, as this insulator layer is not provided in a MOS region, its step can be made smaller. Consequently, parasitic capacitance can be reduced while the insulator layer can be made thicker. Thus, there can be achieved both fast operation and high reliability of the bipolar transistor and, moreover, reduction in the reliability of a MOS transistor can also be prevented.

Abstract: A process for doping a P-type substrate (50) by forming a layer (52) of silicon nitride, implanting N-type impurities through this layer (FIG. 7), forming a resist mask (54) which leaves at least one area of the substrate (FIG. 8) containing a part of the nitride layer exposed, implanting N-type impurities first with an insufficient energy and then with a sufficient energy to traverse the nitride layer, subjecting (FIG. 9) the substrate to a high temperature treatment in an oxidizing environment to form silicon dioxide pads (55) on the areas of the substrate not covered by the nitride layer, removing the nitride layer and performing an implantation of P-type impurities into the areas delimited by the pads. The process then continues with the removal of the pads and, in the conventional manner, with the formation of an epitaxial layer and selective doping of this to form P-type and N-type regions in it.

Abstract: To accomplish the above objectives, the present invention provides a method of fabricating a collector well in a semiconductor BiCMOS device. The method begins by providing a substrate having c-well areas, N-well areas, and P-well areas. The substrate has n-plug doped regions in said c-well areas. A stress release oxide layer is grown over the substrate surface. A first nitride layer 27 is formed over the stress release oxide layer 26. A C-well mask 29having C-well mask openings 28A is formed over C-well areas 28 and openings are formed in the first nitride layer. Impurities are implanted through the opening forming collector-well regions. The c-well mask is then removed. A n-well photoresist mask having n-well mask openings 42A is formed over the first nitride layer and openings are etched in the first nitride layer over N-well areas 40. Ions impurities are implanted through the n-well nitride opening 42A forming n-well regions 44 in the n-well area in the substrate 10. The n-well mask 42 is then removed.

Abstract: A bipolar transistor with MOS-controlled protection for a reverse-biased emitter-base junction is disclosed. A bipolar transistor and a MOS transistor are configured with the drain and the gate electrically coupled to the emitter, and the source and body electrically coupled to the base. A reverse-bias at the emitter-base junction, which is less than a breakdown voltage for the emitter-base junction, activates the MOS transistor which substantially reduces the resistance between the emitter and the base. Preferably, a first semiconductor region provides both the drain and the emitter, and a second semiconductor region provides both the body and the base, for reduced surface area on an integrated circuit chip.

Abstract: A method of manufacturing an improved bipolar transistor or BiCMOS having a phosphorus-doped polysilicon emitter electrode is disclosed. The method comprises forming an emitter electrode wherein a phosphorus-doped amorphous silicon film is deposited at temperature not higher than 540.degree. C. and then subjected to low temperature annealing treatment at a temperature of 600.degree. C. to 750.degree. C., under which the amorphous silicon is converted to a polysilicon and the phosphorus present in the amorphous silicon film is diffused into a base region to form an emitter region, followed by high temperature/short time annealing treatment at a temperature of 900.degree. C. to 950.degree. C. so that an activation rate of an impurity in a boron-doped polysilicon base electrode or source-drain regions of MOS.cndot.FET is improved.

Abstract: Fabrication of a high frequency bipolar transistor structure is integrated into a CMOS process flow with minimal additional cost. The polysilicon emitter of the bipolar device and the polysilicon gate of the MOS device use separate polysilicon layers and, therefore, allow the bipolar emitter and the MOS gate to be doped independently of each other. The process scheme does not require the MOS device to be subdivided.

Abstract: A BiCMOS semiconductor device comprising a substrate, a vertical bipolar transistor provided on the substrate and having a first conductive base terminal electrode formed in a portion of a first semiconductor film provided on the substrate, a second conductive semiconductor terminal electrode formed in a second semiconductor film provided through an insulating layer on the first semiconductor film, the first and second conductive electrodes being disposed such that portions thereof overlap each other, and an LDD (lightly doped drain)-type MOS transistor provided on the substrate and having a gate electrode formed in a portion of said first semiconductor film and a gate side wall formed on a side wall of said gate electrode, wherein the insulating layer is caused to exist selectively in a region in which the first and second conductive electrodes are overlapped, and constitutes at least a portion of the gate side wall.

Abstract: In the Bi-CMOS process of manufacturing a semiconductor device by an effective combination of a bipolar transistor manufacturing process and a CMOS transistor manufacturing process in the case of the formation of a silicide film on a Bi-CMOS device, in which the bipolar transistor having an inner base region made of a silicon film grown by epitaxy and the MOS transistor having silicide formed on the gate electrode, source region and drain region in a self-aligned manner therewith are formed on the same semiconductor substrate, while the silicon film of the inner base region is epitaxially grown in a step, a silicon film is also epitaxially grown on the source/drain regions at the same time in the same step.

Abstract: An electrostatic discharge protection device structure having a lightly doped drain area at the source to allow a faster time to start conduction in an electrostatic discharge event and an abrupt junction at the drain to allow for a low voltage during the conduction of an electrostatic discharge event. The electrostatic discharge protection device structure will be fabricated using standard lightly doped drain CMOS processing.

Abstract: A fabrication method that enables to realize a semiconductor integrated circuit device having capacitors, bipolar transistors and IGFETs at a lower fabrication cost and a higher fabrication yield than the case of the conventional ones. After a first patterned conductor film having contours of first capacitor electrodes and of base electrodes is formed, a first patterned insulator film is formed on the first capacitor electrodes to produce first dielectrics A second patterned conductor film having contours of second capacitor electrodes and of gate electrodes is then formed on the first capacitor electrodes and the gate insulators. A second patterned insulator film is formed on the second capacitor electrodes to produce second dielectrics. A third patterned conductor film having contours of third capacitor electrodes and of emitter electrodes is formed on the second dielectrics, the base regions and source/drain regions.

Abstract: It is the object of the invention to provide a method for fabricating a semiconductor device, such as a bipolar transistor, with improved characteristics when used in a semiconductor integrated circuit, without increasing the steps in fabricating process. In forming the graft base of the bipolar transistor, oxygen ions with higher energy than that of impurities are injected through the same mask. Thereafter, an insulating film is formed under the graft base region, by activating thermal treatment. Moreover, in a semiconductor integrated circuit of BiCMOS type, insulation films are formed under a source and a drain of a P-type transistor.