Heterojunction Bipolar Transistor Patents (Class 438/235)
  • Patent number: 10211328
    Abstract: A normally-off, heterojunction field effect transistor includes an intrinsic cubic-phase gallium nitride (c-GaN) substrate and an aluminum gallium nitride (AlGaN) capping layer disposed on the intrinsic c-GaN substrate. The AlGaN capping layer includes a first sublayer of intrinsic c-phase AlxGa1-xN disposed on the c-GaN substrate, wherein the first sublayer is of a first thickness; a second sublayer of doped c-phase AlxGa1-xN disposed on the first sublayer, and wherein the second sublayer is of a second thickness and is doped with a dopant. An insulating layer is disposed on the AlGaN capping layer, wherein the insulating layer is of a fourth thickness. A source electrode, a drain electrode, and a gate electrode are positioned adjacent to and on top of the insulating layer, respectively.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: February 19, 2019
    Assignee: Board of Trustees of the University of Illinois
    Inventors: Can Bayram, Ryan William Grady, Kihoon Park
  • Patent number: 9466688
    Abstract: The present invention provides a semiconductor with a multilayered contact structure. The multilayered structure includes a metal contact placed on an active region of a semiconductor and a metal contact extension placed on the metal contact.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: October 11, 2016
    Assignee: NXP B.V.
    Inventors: Soenke Habenicht, Detlef Oelgeschlager, Olrik Schumacher, Stefan Bengt Berglund
  • Patent number: 9276068
    Abstract: A silicon oxide film is formed on an epitaxial layer by dry thermal oxidation, an ohmic electrode is formed on a back surface of a SiC substrate, an ohmic junction is formed between the ohmic electrode and the back surface of the SiC substrate by annealing the SiC substrate, the silicon oxide film is removed, and a Schottky electrode is formed on the epitaxial layer. Then, a sintering treatment is performed to form a Schottky junction between the Schottky electrode and the epitaxial layer.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: March 1, 2016
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yoshinori Matsuno, Yoichiro Tarui
  • Patent number: 9059080
    Abstract: Methods for fabricating device structures, such as bipolar transistors and diodes. The method includes forming a trench extending through stacked semiconductor and insulator layers and into an underlying semiconductor substrate. The trench may be at least partially filled with a sacrificial plug containing a dopant with a conductivity type opposite to the conductivity type of the semiconductor substrate. Dopant is transported outwardly from the sacrificial plug into the semiconductor substrate surrounding the trench to define a doped region of the second conductivity type in the semiconductor substrate. A first contact is formed that extends through the semiconductor and insulator layers to a portion of the semiconductor substrate outside of the doped region. A second contact is formed that extends through the semiconductor and insulator layers to the doped region.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Publication number: 20150056767
    Abstract: A hybrid transistor is produced to have a substrate with a first (e.g., P type) well region and a second (e.g., N type) well region with an NP or PN junction therebetween. A MOS portion of the hybrid transistor has an (e.g., N type) source region in the first well region and a gate conductor overlying and insulated from the well regions. A drain or anode (D/A) portion in the second well region collects current from the source region, and includes a bipolar transistor having an (e.g., N+) emitter region, a (e.g., P type) base region and a (e.g., N type) collector region laterally separated from the junction. Different LDMOS-like or IGBT-like properties are obtained depending on whether the current is extracted from the hybrid transistor via the bipolar transistor base or emitter or both. The bipolar transistor is desirably a vertical hetero-junction transistor.
    Type: Application
    Filed: October 3, 2014
    Publication date: February 26, 2015
    Inventor: VISHAL P. TRIVEDI
  • Patent number: 8963253
    Abstract: A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates, one or more P+ doped plates, one or more field oxide (FOX) portions, and one or more field plates. A multi-emitter structure is also provided.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: February 24, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsin-Liang Chen, Shuo-Lun Tu
  • Patent number: 8957456
    Abstract: Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: February 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Renata Camillo-Castillo, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater
  • Patent number: 8941219
    Abstract: An integrated circuit package system includes: interconnection pads; a first device mounted below the interconnection pads; a bond wire, or a solder ball connecting the first device to the interconnection pads; a lead connected to the interconnection pad or to the first device; an encapsulation having a top surface encapsulating the first device; and a recess in the top surface of the encapsulation with the interconnection pads exposed therefrom.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: January 27, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay, Jairus Legaspi Pisigan
  • Patent number: 8912569
    Abstract: A hybrid transistor (58) has a substrate (42) with a first (e.g., P type) well region (46) and a second (e.g., N type) well region (44) with an NP or PN junction (43) therebetween. A MOS portion (70-3) of the hybrid transistor (58) has an (e.g., N type) source region (48) in the first well region (46) and a gate conductor (52) overlying and insulated from the well regions (46, 44) that extends laterally at least to the junction (43). A drain or anode (D/A) portion (71-3) in the second well region (44) collects current 56 from the source region (48), and includes a bipolar transistor (78) having an (e.g., N+) emitter region (64), a (e.g., P type) base region (59) and a (e.g., N type) collector region (62) laterally separated from the junction (43). Different LDMOS-like or IGBT-like properties are obtained depending on whether the current 56 is extracted from the hybrid transistor (58) via the bipolar transistor (78) base (59) or emitter (64) or both.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: December 16, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Vishal P. Trivedi
  • Patent number: 8901611
    Abstract: Bipolar field effect transistor (BiFET) structures and methods of forming the same are provided. In one embodiment, an apparatus includes a substrate and a plurality of epitaxial layers disposed over the substrate. The plurality of epitaxial layers includes a first epitaxial layer, a second epitaxial layer disposed over the first epitaxial layer, and a third epitaxial layer disposed over the second epitaxial layer. The first epitaxial layer includes at least a portion of a channel of a first field effect transistor (FET) and the third epitaxial layer includes at least a portion of a channel of a second FET.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: December 2, 2014
    Assignee: Skyworks Solutions, Inc.
    Inventors: Peter J. Zampardi, Jr., Hsiang-Chih Sun
  • Patent number: 8877574
    Abstract: Portions of a top compound semiconductor layer are recessed employing a gate electrode as an etch mask to form a source trench and a drain trench. A low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material in the source trench and the drain trench. Metallization is performed on physically exposed surfaces of the elemental semiconductor material portions in the source trench and the drain trench by depositing a metal and inducing interaction with the metal and the at least one elemental semiconductor material. A metal semiconductor alloy of the metal and the at least one elemental semiconductor material can be performed at a temperature lower than 600° C. to provide a high electron mobility transistor with a well-defined device profile and reliable metallization contacts.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Anirban Basu, Bahman Hekmatshoartabari, Davood Shahrjerdi
  • Patent number: 8872231
    Abstract: A semiconductor wafer includes a first semiconductor, and a second semiconductor formed directly or indirectly on the first semiconductor. The second semiconductor contains a first impurity atom exhibiting p-type or n-type conductivity, and a second impurity atom selected such that the Fermi level of the second semiconductor containing both the first and second impurity atoms is closer to the Fermi level of the second semiconductor containing neither the first impurity atom nor the second impurity atom, than the Fermi level of the second semiconductor containing the first impurity atom is. For example, the majority carrier of the second semiconductor is an electron, and the Fermi level of the second semiconductor containing the first and second impurity atoms is lower than the Fermi level of the second semiconductor containing the first impurity atom.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: October 28, 2014
    Assignee: Sumitomo Chemical Company, Limited
    Inventor: Osamu Ichikawa
  • Patent number: 8853043
    Abstract: A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Wade J. Hodge, Alvin J. Joseph, Rajendran Krishnasamy, Qizhi Liu, Bradley A. Orner
  • Patent number: 8846481
    Abstract: Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance Rb. Specifically, a metal silicide layer covers the extrinsic base, including the portion of the extrinsic base that extends below the upper portion of a T-shaped emitter. One exemplary technique for ensuring that the metal silicide layer covers this portion of the extrinsic base requires tapering the upper portion of the emitter. Such tapering allows a sacrificial layer below the upper portion of the emitter to be completely removed during processing, thereby exposing the extrinsic base below and allowing the metal layer required for silicidation to be deposited thereon. This metal layer can be deposited, for example, using a high pressure sputtering technique to ensure that all exposed surfaces of the extrinsic base, even those below the upper portion of the emitter, are covered.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Marc W. Cantell, Thai Doan, Jessica A. Levy, Qizhi Liu, William J. Murphy, Christa R. Willets
  • Patent number: 8841673
    Abstract: A thin-film transistor device includes: a gate electrode above a substrate; a gate insulating film on the gate electrode; a crystalline silicon thin film above the gate insulating film; a first semiconductor film above the crystalline silicon thin film; a pair of second semiconductor films above the first semiconductor film; a source electrode over one of the second semiconductor films; and a drain electrode over an other one of the second semiconductor films. The first semiconductor film is provided on the crystalline silicon thin film. A relationship ECP<EC1 is satisfied where ECP and EC1 denote energy levels at lower ends of conduction bands of the crystalline silicon thin film and the first semiconductor film, respectively.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: September 23, 2014
    Assignees: Panasonic Corporation, Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Arinobu Kanegae, Takahiro Kawashima, Hiroshi Hayashi, Genshirou Kawachi
  • Patent number: 8796149
    Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate. An intrinsic base is formed on the emitter. A collector is formed that is separated from the emitter by the intrinsic base. The collector includes a semiconductor material having an electronic bandgap greater than an electronic bandgap of a semiconductor material of the device region.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: James W. Adkisson, David L. Harame, Qizhi Liu
  • Patent number: 8790984
    Abstract: An NPN bipolar junction transistor is disclosed that exhibits a collector-to-emitter breakdown voltage greater than 10 volts and a beta greater than 300. The large value of beta is obtained by fabricating the transistor with an extra N-type layer that reduces recombination of electrons and holes.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 29, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Cheng-Chi Lin, Shuo-Lun Tu, Shih-Chin Lien
  • Patent number: 8748255
    Abstract: One embodiment of an electrostatic protection diode in an integrated circuit includes a base area having at least two bends therein.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: June 10, 2014
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Thomas R. Apel, Jeremy R. Middleton
  • Patent number: 8716756
    Abstract: A semiconductor device according to the present invention includes a substrate; a nitride semiconductor layer formed above the substrate and having a laminated structure including at least three layers; a heterojunction bipolar transistor formed in a region of the nitride semiconductor layer; and a field-effect transistor formed in a region of the nitride semiconductor layer, the region being different from the region in which the heterojunction bipolar transistor is formed.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: May 6, 2014
    Assignee: Panasonic Corporation
    Inventors: Kazushi Nakazawa, Akiyoshi Tamura
  • Patent number: 8697481
    Abstract: Multijunction solar cells having at least four subcells are disclosed, in which at least one of the subcells comprises a base layer formed of an alloy of one or more elements from group III on the periodic table, nitrogen, arsenic, and at least one element selected from the group consisting of Sb and Bi, and each of the subcells is substantially lattice matched. Methods of manufacturing solar cells and photovoltaic systems comprising at least one of the multijunction solar cells are also disclosed.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: April 15, 2014
    Assignee: Solar Junction Corporation
    Inventors: Rebecca Elizabeth Jones-Albertus, Pranob Misra, Michael J. Sheldon, Homan B. Yuen, Ting Liu, Daniel Derkacs, Vijit Sabnis, Micahel West Wiemer, Ferran Suarez
  • Publication number: 20140097472
    Abstract: Bipolar field effect transistor (BiFET) structures and methods of forming the same are provided. In one embodiment, an apparatus includes a substrate and a plurality of epitaxial layers disposed over the substrate. The plurality of epitaxial layers includes a first epitaxial layer, a second epitaxial layer disposed over the first epitaxial layer, and a third epitaxial layer disposed over the second epitaxial layer. The first epitaxial layer includes at least a portion of a channel of a first field effect transistor (FET) and the third epitaxial layer includes at least a portion of a channel of a second FET.
    Type: Application
    Filed: October 2, 2013
    Publication date: April 10, 2014
    Applicant: SKYWORKS SOLUTIONS, INC.
    Inventors: Peter J. Zampardi, JR., Hsiang-Chih Sun
  • Patent number: 8692288
    Abstract: Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The structure includes two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: April 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: James S. Dunn, Alvin J. Joseph, Anthony K. Stamper
  • Patent number: 8664698
    Abstract: High frequency performance of (e.g., silicon) bipolar devices is improved by reducing the extrinsic base resistance Rbx. An emitter, intrinsic base and collector are formed in a semiconductor body. An emitter contact has a region that overlaps a portion of an extrinsic base contact. A sidewall is formed in the extrinsic base contact proximate a lateral edge of the overlap region of the emitter contact. The sidewall is amorphized during or after formation so that when the emitter contact and the extrinsic base contact are, e.g., silicided, some of the metal atoms forming the silicide penetrate into the sidewall so that part of the highly conductive silicided extrinsic base contact extends under the edge of the overlap region of the emitter contact closer to the intrinsic base, thereby reducing Rbx. Smaller Rbx provides transistors with higher fMAX.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: March 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jay P. John, James A. Kirchgessner, Vishal P. Trivedi
  • Patent number: 8653627
    Abstract: A semiconductor crystal having a recombination-inhibiting semiconductor layer of a second conductive type that is disposed in the vicinity of the surface between a base contact region and emitter regions and that separates the semiconductor surface having a large number of surface states from the portion that primarily conducts the positive hole electric current and the electron current. Recombination is inhibited, and the current amplification factor is thereby improved and the ON voltage reduced.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: February 18, 2014
    Assignee: Honda Motor Co., Ltd.
    Inventor: Ken-ichi Nonaka
  • Publication number: 20140027817
    Abstract: A hybrid transistor (58) has a substrate (42) with a first (e.g., P type) well region (46) and a second (e.g., N type) well region (44) with an NP or PN junction (43) therebetween. A MOS portion (70-3) of the hybrid transistor (58) has an (e.g., N type) source region (48) in the first well region (46) and a gate conductor (52) overlying and insulated from the well regions (46, 44) that extends laterally at least to the junction (43). A drain or anode (D/A) portion (71-3) in the second well region (44) collects current (69) from the source region (48), and includes a bipolar transistor (78) having an (e.g., N+) emitter region (64), a (e.g., P type) base region (59) and a (e.g., N type) collector region (62) laterally separated from the junction (43). Different LDMOS-like or IGBT-like properties are obtained depending on whether the current (69) is extracted from the hybrid transistor (58) via the bipolar transistor (78) base (59) or emitter (64) or both.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Vishal P. Trivedi
  • Patent number: 8598627
    Abstract: An n-layer is arranged above a substrate, which can be GaAs, and a p-layer (4) is arranged on the n-layer. The p-layer is separated by a gate electrode into two separate portions forming source and drain. The gate electrode is insulated from the semiconductor material by a gate dielectric. Source/drain contacts are electrically conductively connected with the portions of the p-layer.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: December 3, 2013
    Assignee: EPCOS AG
    Inventor: Léon C. M. van den Oever
  • Patent number: 8597993
    Abstract: A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: December 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: Shunhua Chang, Kiran V. Chatty, Robert J. Gauthier, Jr., Mujahid Muhammad
  • Patent number: 8574982
    Abstract: A method and circuit for implementing an embedded dynamic random access memory (eDRAM), and a design structure on which the subject circuit resides are provided. The embedded dynamic random access memory (eDRAM) circuit includes a stacked field effect transistor (FET) and capacitor. The capacitor is fabricated directly on top of the FET to build the eDRAM.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: November 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Karl Robert Erickson, David Paul Paulsen, John Edward Sheets, II, Kelly L. Williams
  • Patent number: 8575659
    Abstract: A combinationally doped semiconductor layer, a double heterojunction bipolar transistor (DHBT) including a combinationally doped semiconductor layer, and a method of making a combinationally doped semiconductor layer employ a combination of carbon and beryllium doping. The combinationally doped semiconductor layer includes a first sublayer of a semiconductor material doped substantially with beryllium and a second sublayer of the semiconductor material doped substantially with carbon. The DHBT includes a carbon-beryllium combinationally doped semiconductor layer as a base layer. The method of making a combinationally doped semiconductor layer includes growing a first sublayer of the semiconductor layer, the first sublayer being doped substantially with beryllium and growing a second sublayer of the semiconductor layer, the second sublayer being doped substantially with carbon.
    Type: Grant
    Filed: August 13, 2011
    Date of Patent: November 5, 2013
    Assignee: HRL Laboratories, LLC
    Inventors: Steven S. Bui, Tahir Hussain, James Chingwei Li
  • Patent number: 8546917
    Abstract: A semiconductor structure and a manufacturing method and an operating method for the same are provided. The semiconductor structure comprises a first well region, a second well region, a first doped region, a second doped region, an anode, and a cathode. The second well region is adjacent to the first well region. The first doped region is on the second well region. The second doped region is on the first well region. The anode is coupled to the first doped region and the second well region. The cathode is coupled to the first well region and the second doped region. The first well region and the first doped region have a first conductivity type. The second well region and the second doped region have a second conductivity type opposite to the first conductivity type.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: October 1, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsin-Liang Chen, Wing-Chor Chan, Shyi-Yuan Wu
  • Patent number: 8546205
    Abstract: Apparatus and methods for detecting evaporation conditions in an evaporator for evaporating metal onto semiconductor wafers, such as GaAs wafers, are disclosed. One such apparatus can include a crystal monitor sensor configured to detect metal vapor associated with a metal source prior to metal deposition onto a semiconductor wafer. This apparatus can also include a shutter configured to remain in a closed position when the crystal monitor sensor detects an undesired condition, so as to prevent metal deposition onto the semiconductor wafer. In some implementations, the undesired condition can be indicative of a composition of a metal source, a deposition rate of a metal source, impurities of a metal source, position of a metal source, position of an electron beam, and/or intensity of an electron beam.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: October 1, 2013
    Assignee: Skyworks Solutions, Inc.
    Inventors: Lam T. Luu, Heather L. Knoedler, Richard S. Bingle, Daniel C. Weaver
  • Patent number: 8518771
    Abstract: A method is provided for manufacturing a solid-state imaging device including a semiconductor substrate having a photoelectric conversion portion, a pixel transistor region and a logic circuit region. The method includes the steps of forming a first gate electrode on the semiconductor substrate with a first gate insulating film therebetween, a second gate electrode in the pixel transistor region on the semiconductor substrate with a second gate insulating film therebetween; forming a first insulating layer to cover the first gate electrode, the second gate electrode, a floating diffusion region where a floating diffusion portion is to be formed, and the photoelectric conversion portion; and forming an offset spacer on a sidewall of the first gate electrode by etch back of the first insulating layer in a state where the photoelectric conversion portion, the pixel transistor region and the floating diffusion region are masked.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: August 27, 2013
    Assignee: Sony Corporation
    Inventors: Naohiko Kimizuka, Takuji Matsumoto
  • Patent number: 8519443
    Abstract: The invention concerns a heterojunction bipolar transistor comprising a support, and epitaxially grown from said support, at least: one collecting, respectively emitting, layer; at least one base layer; and at least one emitting, respectively collecting, layer. The collecting, respectively emitting, layer comprises: at least one first undercoat contacted with said base layer, substantially of similar composition as said emitting, respectively collecting, layer; and at least one second undercoat on the side opposite said base layer relative to said first undercoat.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: August 27, 2013
    Assignees: Centre National de la Recherche Scientifique-CNRS, S.O.I. Tec Silicon on Insulator Technologies
    Inventors: Jean-Luc Pelouard, Melania Lijadi, Christophe Dupuis, Fabrice Pardo, Philippe Bove
  • Patent number: 8513075
    Abstract: A manufacturing method for manufacturing a semiconductor device includes depositing a spacer material on a semiconductor substrate, the substrate includes an NMOS region and a PMOS region, each region has a gate formed thereon. The method further includes covering the NMOS region with a first mask, forming a spacer for the PMOS gate by etching the spacer material, forming a recess in the PMOS region by etching, and growing SiGe or SiGe with in-situ-doped B in the recess of the PMOS region to form a PMOS source/drain region. The method further includes performing an anisotropic wet etching on the recess. After growing SiGE or SiGe with in-situ-doped B, the method further includes covering the PMOS region with a second mask and forming a spacer for the NMOS gate by etching the spacer material. The spacer for the PMOS and NMOS gate has a different critical dimension.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: August 20, 2013
    Assignee: Semiconductor Manufacturing International Corporation
    Inventors: Yonggen He, Jingang Wu, Haibiao Yao
  • Patent number: 8460994
    Abstract: A semiconductor crystal includes a recombination-inhibiting semiconductor layer (17) of a second conductive type that is disposed in the vicinity of the surface between a base contact region (16) and emitter regions (14) and that separates the semiconductor surface having a large number of surface states from the portion that primarily conducts the positive hole electric current and the electron current. Recombination is inhibited, and the current amplification factor is thereby improved and the ON voltage reduced.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: June 11, 2013
    Assignee: Honda Motor Co., Ltd.
    Inventor: Ken-ichi Nonaka
  • Patent number: 8435852
    Abstract: A heterojunction bipolar transistor is formed with an emitter electrode that comprises an emitter epitaxy underlying an emitter metal cap and that has horizontal dimensions that are substantially equal to the emitter metal cap.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: May 7, 2013
    Assignee: HRL Laboratories, LLC
    Inventor: Charles H. Fields, Jr.
  • Patent number: 8436399
    Abstract: A semiconductor device according to the present invention includes a substrate; a nitride semiconductor layer formed above the substrate and having a laminated structure including at least three layers; a heterojunction bipolar transistor formed in a region of the nitride semiconductor layer; and a field-effect transistor formed in a region of the nitride semiconductor layer, the region being different from the region in which the heterojunction bipolar transistor is formed.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: May 7, 2013
    Assignee: Panasonic Corporation
    Inventors: Kazushi Nakazawa, Akiyoshi Tamura
  • Patent number: 8390027
    Abstract: A gallium nitride semiconductor device is disclosed that can be made by an easy manufacturing method. The device includes a silicon substrate, buffer layers formed on the top surface of the silicon substrate, and gallium nitride grown layers formed thereon. The silicon substrate has trenches 12 formed from the bottom surface, each trench having a depth reaching the gallium nitride grown layer through the silicon substrate and the buffer layers. The inside surface of each of the trenches and the bottom surface of the silicon substrate is covered with a drain electrode as a metal film. The vertical gallium nitride semiconductor device with this structure allows an electric current to flow in the direction of the thickness of the silicon substrate regardless of the resistance values of the gallium nitride grown layers and the buffer layers.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: March 5, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Noriyuki Iwamuro
  • Patent number: 8377788
    Abstract: A SiGe heterojunction bipolar transistor is fabricated by etching an epitaxially-formed structure to form a mesa that has a collector region, a cap region, and a notched SiGe base region that lies in between. A protective plug is formed in the notch of the SiGe base region so that thick non-conductive regions can be formed on the sides of the collector region and the cap region. Once the non-conductive regions have been formed, the protective plug is removed. An extrinsic base is then formed to lie in the notch and touch the base region, followed by the formation of isolation regions and an emitter region.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: February 19, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Wibo Van Noort, Jamal Ramdani, Andre Labonte, Donald Robertson Getchell
  • Patent number: 8350295
    Abstract: Methods and apparatuses for forming a device structure including a high-thermal-conductivity substrate are disclosed herein. A method forming such a device structure may comprise forming an active layer over a first substrate in a manner such that a frontside of the active layer faces the first substrate and a backside of the active layer faces away from the first substrate, forming a second substrate over the backside of the active layer, and removing the first substrate to expose the frontside of the active layer. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: January 8, 2013
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Paul Saunier, Edward Beam, Deep Dumka
  • Patent number: 8304302
    Abstract: A photovoltaic device and methods for forming the same. In one embodiment, the photovoltaic device has a silicon substrate, and a film comprising a plurality of single wall carbon nanotubes disposed on the silicon substrate, wherein the plurality of single wall carbon nanotubes forms a plurality of heterojunctions with the silicon in the substrate.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: November 6, 2012
    Assignee: Board of Trustees of the University of Arkansas
    Inventors: Alexandru S. Biris, Zhongrui Li
  • Patent number: 8247287
    Abstract: In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: August 21, 2012
    Assignee: Power Integrations, Inc.
    Inventors: Vijay Parthasarathy, Sujit Banerjee
  • Patent number: 8216910
    Abstract: A wafer comprising at least one high Ft HBT and at least one high BVceo HBT having various collector profiles on a common III-V compound semiconductor based wafer. The N+ implant in the collector varies the collector profiles of individual HBTs on the wafer. The method for preparing the device comprises forming of HBT layers up to and including collector layer on non-silicon based substrate, performing ion implantation, annealing for implant activation, and forming remaining HBT layers.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: July 10, 2012
    Assignee: HRL Laboratories, LLC
    Inventors: Mary Chen, Marko Sokolich
  • Patent number: 8143120
    Abstract: A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: March 27, 2012
    Assignee: Agere Systems Inc.
    Inventors: Daniel Charles Kerr, Michael Scott Carroll, Amal Ma Hamad, Thiet The Lai, Roger W. Key
  • Patent number: 8115196
    Abstract: A base structure for high performance Silicon Germanium:Carbon (SiGe:C) based heterojunction bipolar transistors (HBTs) with phosphorus atomic layer doping (ALD) is disclosed. The ALD process subjects the base substrate to nitrogen gas (in ambient temperature approximately equal to 500 degrees Celsius) and provides an additional SiGe:C spacer layer. During the ALD process, the percent concentrations of Germanium (Ge) and carbon (C) are substantially matched and phosphorus is a preferred dopant. The improved SiGe:C HBT is less sensitive to process temperature and exposure times, and exhibits lower dopant segregation and sharper base profiles.
    Type: Grant
    Filed: February 21, 2011
    Date of Patent: February 14, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Janial Ramdani, Craig Richard Printy, Thanas Budri
  • Patent number: 8058124
    Abstract: The semiconductor device, which provides reduced electric current leakage and parasitic resistance to achieve stable current gain, is provided. A first polycrystalline semiconductor layer is grown on a p-type polycrystalline silicon film exposed in a lower surface of a visor section composed of a multiple-layered film containing a p-type polycrystalline silicon film and a silicon nitride film, while growing the first semiconductor layer on a n-type collector layer, and then the first polycrystalline semiconductor layer is selectively removed.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: November 15, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Masataka Ono, Akiko Fujita
  • Patent number: 8048734
    Abstract: One or more embodiments of the invention relate to a method of making a heterojunction bipolar transistor, including: forming a collector layer; forming a stack of at least a second dielectric layer overlying a first dielectric layer, the stack formed over the collector layer; removing a portion of each of the dielectric layers to form an opening through the stack; and forming a base layer within the opening.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: November 1, 2011
    Assignee: Infineon Technologies AG
    Inventor: Detlef Wilhelm
  • Patent number: 8043910
    Abstract: An integrated semiconductor structure includes a heterojunction bipolar transistor and a Schottky diode. The structure has a substrate, the heterojunction bipolar transistor overlying and contacting the substrate, wherein the heterojunction bipolar transistor includes a transistor collector layer, and a Schottky diode overlying the substrate and overlying the transistor collector layer. The Schottky diode includes a Schottky diode barrier layer structure that desirably is not of the same material, doping, and thickness as the transistor collector layer.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: October 25, 2011
    Assignee: The Boeing Company
    Inventor: Berinder P. S. Brar
  • Publication number: 20110250726
    Abstract: Method for manufacturing a semiconductor device. A channel layer is formed by epitaxially growing a semiconductor layer, in which an ion species of a first conductivity is implanted on a semiconductor substrate. A source region, a drain region, and an emitter region which are of the first conductivity, are formed by activating, using annealing, a portion of the semiconductor substrate in which the ion species has been implanted. An emitter layer of the first conductivity, a base layer of a second conductivity having a band gap smaller than a band gap of the emitter layer, and a collector layer of the first conductivity or a non-doped collector layer are sequentially and epitaxially grown on the channel layer.
    Type: Application
    Filed: June 22, 2011
    Publication date: October 13, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Keiichi MURAYAMA, Akiyoshi TAMURA, Kenichi MIYAJIMA
  • Publication number: 20110241076
    Abstract: An n-layer is arranged above a substrate, which can be GaAs, and a p-layer (4) is arranged on the n-layer. The p-layer is separated by a gate electrode into two separate portions forming source and drain. The gate electrode is insulated from the semiconductor material by a gate dielectric. Source/drain contacts are electrically conductively connected with the portions of the p-layer.
    Type: Application
    Filed: November 12, 2009
    Publication date: October 6, 2011
    Applicant: EPCOS AG
    Inventor: Léon C. M. van den Oever