Abstract: A process for forming a bipolar junction transistor (BJT) in a semiconductor substrate and a BJT formed according to the process. A buried isolation region is formed underlying BJT structures to isolate the BJT structures from the p-type semi-conductor substrate. To reduce capacitance between a BJT subcollector and the buried isolation region, prior to implanting the subcollector spaced-apart structures are formed on a surface of the substrate. The subcollector is formed by implanting ions through the spaced-apart structures and through a region intermediate the spaced-apart structures. The formed BJT subcollector therefore comprises a body portion and end portions extending therefrom, with the end portions disposed at a shallower depth than the body portion, since the ions implanting the end portions must pass through the spaced-apart structures. The shallower depth of the end portions reduces the capacitance.

Abstract: A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains.

Abstract: An input/output (I/O) mixed-voltage drive circuit and electrostatic discharge protection device for coupling to an I/O pad. The device includes an NFET device having a gate, a drain, a source and body, the gate adapted for coupling to a pre-drive circuit, the source and the body being coupled to one another and to ground. The device also includes a bipolar junction transistor having a collector, an emitter and a base, the emitter being coupled to the drain of the NFET and the collector being coupled to the I/O pad.

Abstract: A semiconductor device is provided that includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, an isolation structure formed in the second region, at least one junction device formed proximate the isolation structure in the second region, and a stopping structure formed overlying the isolation structure in the second region.

Abstract: A biCMOS device including a bipolar transistor and a Polysilicon/Insulator/Polysilicon (PIP) capacitor is disclosed. A biCMOS device may have a relatively low series resistance at a bipolar transistor. A bipolar transistor may have a desirable amplification rate.

Abstract: A method for reducing an effective lateral resistance of a buried layer in an IC includes forming first and second circuit sections in a common substrate, the second circuit section being spaced laterally from the first circuit section. The method further includes forming an isolation buried layer in the substrate under at least a portion of the first circuit section and forming a conductive layer on a surface of the substrate, the conductive layer overlaying at least a portion of the first circuit section. A plurality of conductive plugs are formed in the substrate for operatively connecting the isolation buried layer to the conductive layer, whereby an effective lateral resistance of the isolation buried layer is reduced.

Abstract: A method is provided for forming bipolar (103) and MOS (105) semiconductor devices in a common substrate (46), comprising, forming a combination comprising an MOS device (105) in a first region (44) of the substrate (46) and a portion (50) of a collector region (82, 64, 62, 50) of the bipolar device (103) in a second portion (42) of the substrate (46), covering the MOS device (105) with differentially etchable dielectric layers (56, 58) and the combination with an etch-stop layer (68), completing formation of the bipolar device (103) without completely removing the etch-stop layer (68) from the MOS device (105), anisotropically etching the differentially etchable layers (56, 58) to form a gate sidewall (56?, 58?) of the MOS device (105), and applying contact electrodes (98) to the MOS (105) and bipolar (103) devices.

Abstract: A method of a semiconductor device, which includes an insulated-gate FET and an electronic element, includes three steps. The first step is the step of forming a trench gate of the insulated-gate FET in a first region of a semiconductor base and a trench element-isolation layer in a second region of the semiconductor base, simultaneously. The second step is the step of forming a first diffusion layer of the insulated-gate FET on a side of the trench gate and a second diffusion layer of the electronic element in a region surrounded by the trench element-isolation layer, simultaneously. The third step is the step of forming a third diffusion layer of the insulated-gate FET in the first diffusion layer and a fourth diffusion layer of the electronic element in the second diffusion layer, simultaneously.

Abstract: Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector, an intrinsic base above the collector, shallow trench isolation regions adjacent the collector, a raised extrinsic base above the intrinsic base, a T-shaped emitter above the extrinsic base, spacers adjacent the emitter, and a silicide layer that is separated from the emitter by the spacers.

Abstract: Techniques for forming a memory cell. An aspect of the invention includes forming FET gate stacks and sacrificial cell gate stacks over the substrate. Spacer layers are then formed around the FET gate stacks and around the sacrificial cell gate stacks. The sacrificial cell gate stacks are then removed such that the spacer layers around the sacrificial cell gate stacks are still intact. BJT cell stacks are then formed in the space between the spacer layers where the sacrificial cell gate stacks were formed and removed, the BJT cell stacks including an emitter layer. A phase change layer above the emitter contacts and an electrode above the phase change layer are then formed.

Abstract: A semiconductor device includes a semiconductor-on-insulator region on a substrate. The semiconductor-on-insulator region includes a first semiconductor region overlying a dielectric region. The device includes an MOS transistor and a bipolar transistor. The MOS transistor has a drain region, a body region, and a source region in the first semiconductor region. The MOS transistor also includes a gate. The device also includes a second semiconductor region overlying the substrate and adjacent to the drain region, and a third semiconductor region overlying the substrate and adjacent to the second semiconductor region. The bipolar transistor includes has the drain region of the MOS transistor as an emitter, the second semiconductor region as a base, and the third semiconductor region as a collector. Accordingly, the drain of the MOS transistor also functions as the emitter of the bipolar transistor. Additionally, the gate and the base are coupled by a resistive element.

Abstract: In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor material simultaneously. Other embodiments are described and claimed.

Abstract: A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry.

Abstract: One aspect of the invention relates to an edge structure for a semiconductor component having two electrodes arranged opposite one another on opposite sides of a semiconductor body having a doped zone of the first charge carrier type. The semiconductor body has at least one doped zone of the second charge carrier type extending from a surface into the depth of the semiconductor body and serving for forming a pn junction located in a central region surrounded by an edge region between the two electrodes. The edge region has at least one rectilinear edge section and at least one curved edge section and is formed in such a way that a breakdown voltage in the at least one rectilinear edge section is less than a breakdown voltage in the at least one curved edge section.

Abstract: A method of fabricating a semiconductor device includes a first step of forming a defect suppression film suppressing increase in a defect due to implantation of an impurity on a semiconductor substrate, a second step of forming an active region on a surface of the semiconductor substrate by implanting the impurity through the defect suppression film, a third step of removing the defect suppression film and a fourth step of forming an interface state suppression film suppressing increase in an interface state density of the active region on the active region.

Abstract: A method of manufacturing a CMOS-BJT semiconductor device comprises the steps of: forming a collector region of a first conductivity type and a first well of the first conductivity type, simultaneously in a semiconductor substrate; forming a second well of a second conductivity type opposite to said first conductivity type, in the semiconductor substrate; forming a base region of the second conductivity type in the collector region; forming first and second insulated gate structure on said first and second wells, and a junction protection structure having same constituent elements as said insulated gate structures on said base region; and forming second source/drain regions of the first conductivity type in said second well, and an emitter region of the first conductivity type in the base region, simultaneously, with an emitter-base junction reaching the principal surface below said junction protection structure.

Abstract: The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (1) comprising a bipolar transistor with in that order a collector region (2), a base region (3), and an emitter region (4), wherein the semiconductor body comprises a projecting mesa (5) comprising at least a portion of the collector region (2) and the base region (3), which mesa is surrounded by an isolation region (6). According to the invention, the semiconductor device (10) also comprises a field effect transistor with a source region, a drain region, an interposed channel region, a superimposed gate dielectric (7), and a gate region (8), which gate region (8) forms a highest part of the field effect transistor, and the height of the mesa (5) is greater than the height of the gate region (8). This device can be manufactured inexpensively and easily by a method according to the invention, and the bipolar transistor can have excellent high-frequency characteristics.

Abstract: Integrated circuits using buried layers under epitaxial layers present a challenge in aligning patterns for surface components to the buried layers, because the epitaxial material over the buried layer diminishes the visibility of and shifts the apparent position of the buried layer. A method of measuring the lateral offset, known as the epi pattern shift, between a buried layer and a pattern for a surface component using planar processing technology and commonly used semiconductor fabrication metrology tools is disclosed. The disclosed method may be used on a pilot wafer to provide optimization data for a production line running production wafers, or may be used on production wafers directly. An integrated circuit fabricated using the instant invention is also disclosed.

Abstract: Disclosed are a CMOS image sensor and a manufacturing method thereof.

Abstract: The invention relates to a semiconductor device (10) comprising a substrate (11) and a semiconductor body (1) of silicon having a semiconductor layer structure comprising, in succession, a first and a second semiconductor layer (2, 3), and having a surface region of a first conductivity type which is provided with a field effect transistor (M) with a channel of a second conductivity type, opposite to the first conductivity type, wherein the surface region is provided with source and drain regions (4A, 4B) of the second conductivity type for the field effect transistor (M) and with—interposed between said source and drain regions—a channel region (3A) with a lower doping concentration which forms part of the second semiconductor layer (3) and with a buried first-conductivity-type semiconductor region (2A), buried below the channel region (3A), with a doping concentration that is much higher than that of the channel region (3A) and which forms part of the first semiconductor layer (2).

Abstract: Bipolar transistors in complimentary MOS (CMOS) integrated circuits (ICs) are often fabricated as parasitic components, in which emitters of bipolar transistors are implanted in the same processes as CMOS sources/drains, to avoid manufacturing costs associated with dedicated implants for bipolar emitters. Energies and doses of CMOS source/drain implants are typically selected to optimize CMOS transistor performance, resulting in less than optimum values of bipolar parameters such as gain. CMOS ICs often include implanted resistors of a same type as the emitters of the bipolar transistors in the same ICs. This invention discloses bipolar transistors with emitters implanted by CMOS source/drain implants and resistor implants to improve bipolar transistor parameters, and a method for fabricating same.

Abstract: A high fT and fmax bipolar transistor includes an emitter, a base, and a collector. The emitter has a lower portion and an upper portion that extends beyond the lower portion. The base includes an intrinsic base and an extrinsic base. The intrinsic base is located between the lower portion of the emitter and the collector. The extrinsic base extends from the lower portion of the emitter beyond the upper portion of the emitter and includes a continuous conductor that extends from underneath the upper portion of the emitter and out from underneath the upper portion of the emitter. The continuous conductor provides a low electrical resistance path from a base contact (not shown) to the intrinsic base. The transistor may include a second conductor that does not extend underneath the upper portion of the emitter, but which further reduces the electrical resistance through the extrinsic base.

Abstract: A self-aligned silicon carbide power MESFET with improved current stability and a method of making the device are described. The device, which includes raised source and drain regions separated by a gate recess, has improved current stability as a result of reduced surface trapping effects even at low gate biases. The device can be made using a self-aligned process in which a substrate comprising an n+-doped SiC layer on an n-doped SiC channel layer is etched to define raised source and drain regions (e.g., raised fingers) using a metal etch mask. The metal etch mask is then annealed to form source and drain ohmic contacts. A single- or multilayer dielectric film is then grown or deposited and anisotropically etched. A Schottky contact layer and a final metal layer are subsequently deposited using evaporation or another anisotropic deposition technique followed by an optional isotropic etch of dielectric layer or layers.

Abstract: A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors.

Abstract: A method for decreasing a PN junction leakage current of a dynamic random access memory (DRAM), including the steps of: preparing an NMOS transistor formed on a P-type silicon substrate and comprising a drain; forming an insulation oxide layer on the P-type silicon substrate; etching the insulation oxide layer until the P-type silicon substrate is exposed so as to form a bit line contact hole on the drain; implanting arsenic ions into the P-type silicon substrate via the bit line contact hole to form an arsenic bit line contact window; and implanting phosphorus ions into the P-type silicon substrate via the bit line contact hole to form a phosphorus bit line contact window below the arsenic bit line contact window. In this way, a concentration gradient of N-type ions can be reduced at the bit line contact window, and further a PN junction leakage current can be reduced, thus lowing the power consumption of the DRAM when the DRAM is used for a low power consumption product.

Abstract: A method and apparatus for testing semiconductor wafers is disclosed in which a test circuit is used that includes a waveform generator. The test circuit can test a single transistor or can test multiple transistors. A testing method is disclosed in which a supply voltage is applied to the waveform generator to produce pulses that are applied to the gate of a transistor to be tested. A bias voltage is applied to the source and drain of the transistor to be tested, and the charge pumping current that is generated at the substrate is then measured. The process can be repeated at different bias voltage levels to obtain additional current measurements, indicating the maximum charge pumping current for the transistor that is being tested. The determined maximum charge pumping current can then be used for determining whether there is excessive 1/f noise in the device under test.

Abstract: A method of fabricating a transistor that includes a doped buried region within a semiconductor body. The doped buried region includes a portion having a first thickness and a second thickness, the first thickness being less than the second thickness. In one embodiment, the first thickness is about half the second thickness. The transistor also includes a collector region over the buried region, a base region within the collector region and an emitter region within the base region.

Abstract: A method of fabricating a semiconductor device includes steps of forming a gate electrode on the surface of a region of a semiconductor substrate provided with a first element, forming an insulating film to cover the surface of the gate electrode and another region of the semiconductor substrate provided with a second element and forming a sidewall insulating film covering the side surface of the gate electrode while leaving the insulating film on the region of the semiconductor substrate provided with the second element by a prescribed thickness by etching the insulating film up to an intermediate portion from the surface thereof.

Abstract: A dynamic random access memory (DRAM) cell is described, including a semiconductor pillar on a substrate, a capacitor on a lower portion of a sidewall of the pillar, and a vertical transistor on an upper portion of the sidewall of the pillar. The capacitor includes a first plate in the lower portion of the sidewall of the pillar, a second plate as an upper electrode at the periphery of the first plate, a third plate at the periphery of the second plate electrically connected with the first plate to form a lower electrode, and a dielectric layer separating the second plate from the first and third plates. A DRAM array based on the DRAM cell and a method for fabricating the DRAM array are also described.

Abstract: An electrostatic discharge protection device, and a method of fabricating the same, includes a substrate, an n-well formed in the substrate, a p-well formed on the n-well, an NMOS transistor formed on the p-well, the NMOS transistor including a gate electrode, an n+ source and an n+ drain, and a grounded p+ well pick-up formed in the p-well, wherein the n-well is connected to the n+ drain of the NMOS transistor and the n+ source is grounded. The n+ drain and the n-well are connected to decrease a voltage of a trigger and a current density of a surface of the substrate.

Abstract: Provided is a differential signal driver capable of operating at a high speed at a low voltage of 1.8V. The differential signal driver includes: a differential-signal driving circuit for switching input differential signals and outputting a common mode voltage through first and second output nodes; and a common-mode feedback circuit for providing a predetermined current to the differential-signal driving circuit or receiving a predetermined current from the differential-signal driving circuit in response to the common mode voltage. The differential-signal driving circuit includes a common-mode voltage output circuit for connecting the first output node to the second output node and generating the common mode voltage of the differential-signal driving circuit. The differential input signals are received through two bipolar transistors.

Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.

Abstract: The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) constructions. The base region of the bipolar device can be physically and electrically connected to one of the source/drain regions of the FET to act as a storage node for the memory cell. The semiconductor material of the SOI constructions can comprise Si/Ge, and the active region of the FET can extend into the Si/Ge. The SOI constructions can be formed over any of a number of substrates, including, for example, semiconductive materials, glass, aluminum oxide, silicon dioxide, metals and/or plastics.

Abstract: Embodiments discussed herein relate to processes of producing a field stop zone within a semiconductor substrate by implanting dopant atoms into the substrate to form a field stop zone between a channel region and a surface of the substrate, at least some of the dopant atoms having energy levels of at least 0.15 eV below the energy level of the conduction band edge of semiconductor substrate; and laser annealing the field stop zone.

Abstract: An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a P-well and an N-well for high voltage (HV) devices and a first well in a low voltage/medium voltage (LV/MV) region for a logic device, in a semiconductor substrate; simultaneously forming a second well in the LV/MV region for a logic device and a drift region for one of the HV devices using the same mask; and respectively forming gate oxide layers on the semiconductor substrate in the HV/MV/LV regions. According to the present invention, the number of photolithography processes can be reduced by replacing or combining an additional mask for forming an extended drain region of a high voltage depletion-enhancement CMOS (DECMOS) with a mask for forming a typical well of a logic device, so productivity of the total process of the device can be enhanced.

Abstract: An integrated circuit including a bipolar transistor with improved forward second breakdown is disclosed. In one embodiment, the bipolar transistor includes a base, a collector, a plurality of emitter sections coupled to a common emitter and a ballast emitter for each emitter section. Each ballast resistor is coupled between the common emitter and an associated emitter section. The size of each ballast resistor is selected so that the size of the ballast resistors vary across a two dimensional direction in relation to a lateral surface of the bipolar transistor.

Abstract: A method is provided for forming bipolar (103) and MOS (105) semiconductor devices in a common substrate (46), comprising, forming a combination comprising an MOS device (105) in a first region (44) of the substrate (46) and a portion (50) of a collector region (82, 64, 62, 50) of the bipolar device (103) in a second portion (42) of the substrate (46), covering the MOS device (105) with differentially etchable dielectric layers (56, 58) and the combination with an etch-stop layer (68), completing formation of the bipolar device (103) without completely removing the etch-stop layer (68) from the MOS device (105), anisotropically etching the differentially etchable layers (56, 58) to form a gate sidewall (56?, 58?) of the MOS device (105), and applying contact electrodes (98) to the MOS (105) and bipolar (103) devices.

Abstract: A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors may be provided using different doses or different material implants resulting in devices having different optimum unity current gain cutoff frequency (fT) and breakdown voltage (BVCEO and BVCBO) on a common wafer.

Abstract: A method of producing a semiconductor device includes the steps of: preparing a double SOI substrate, forming a deep trench, filling the deep trench, forming an opening, forming a cavity, depositing a polycrystalline silicon layer, and forming a bipolar transistor.

Abstract: A method forms a bipolar transistor in a semiconductor substrate of a first conductivity type. The method includes: forming on the substrate a single-crystal silicon-germanium layer; forming a heavily-doped single-crystal silicon layer of a second conductivity type; forming a silicon oxide layer; opening a window in the silicon oxide and silicon layers; forming on the walls of the window a silicon nitride spacer; removing the silicon-germanium layer from the bottom of the window; forming in the cavity resulting from the previous removal a heavily-doped single-crystal semiconductor layer of the second conductivity type; and forming in said window the emitter of the transistor.

Abstract: A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed.

Abstract: The present invention includes a circuit structure for ESD protection and methods of making the circuit structure. The circuit structure can be used in an ESD protection circuitry to protect certain devices in an integrated circuit, and can be fabricated without extra processing steps in addition to the processing steps for fabricating the ESD protected devices in the integrated circuit.

Abstract: A semiconductor device manufacturing method is provided which is capable of suppressing variation of the resistance value of resistive interconnection and preventing variation of transistor performance. A gate electrode and a resistive interconnection are formed on a substrate and impurity ions are implanted into the surface of the substrate to form source/drain regions (diffusion layers: 1A, 1B) on both sides of the gate electrode. Also, impurity ions are implanted to control the resistance value of the resistive interconnection. Next, a sidewall film is formed to cover the resistive interconnection. Then a heat treatment is performed to activate the source/drain regions (diffusion layers: 1A, 1B).

Abstract: The lateral pnp transistor encompasses a p-type semiconductor substrate, an n-type first buried region disposed on the semiconductor substrate, an n-type uniform base region disposed on the first buried region, an n-type first plug region disposed in the uniform base region, a p-type first emitter region and a first collector region disposed in and at the top surface of the uniform base region, a graded base region disposed in the uniform base region and a first base contact region disposed in the first plug region. The graded base region encloses the bottom and the side of the first main electrode region. The doping profile in the graded base region intervening between the first emitter region and the first collector region is such that the impurity concentration is gradually decreases towards the second main electrode region from the first main electrode region.

Abstract: A method for manufacturing a bipolar transistor, comprising the steps of: growing on the substrate a first semiconductor; depositing an encapsulation layer etchable with respect to the first semiconductor, forming a sacrificial block at the location of the base-emitter junction; exposing the first semiconductor around spacers formed around said block; forming a second semiconductor, then a third semiconductor etchable with respect to the second semiconductor layer, the encapsulation layer, and the spacers, the sum of the thicknesses of the second semiconductor and the sacrificial layer being substantially equal to the sum of the thicknesses of the encapsulation layer and of the sacrificial block; removing the block and the encapsulation layer; depositing a fourth semiconductor; removing the third semiconductor; and etching an insulating layer to maintain it on the emitter walls and between said emitter and the second semiconductor.

Abstract: Provided is a method of fabricating a silicon germanium (SiGe) Bi-CMOS device. In the fabrication method, the source and drain of the CMOS device is formed using a silicon germanium (SiGe) heterojunction, instead of silicon, thereby preventing a leakage current resulting from a parasitic bipolar operation. Further, since the source and drain is connected with an external interconnection through the nickel (Ni) silicide layer, the contact resistance is reduced, thereby preventing loss of a necessary voltage for a device operation and accordingly, making it possible to enable a low voltage and low power operation and securing a broad operation region even in a low voltage operation of an analogue circuit.

Abstract: A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with a first impurity to increase free carrier conductivity of a first type. The source region and the drain region are heavily dopes with the first impurity. A gate and a back gate are positioned along the side of the channel region and extending from the source region and is implanted with a second semiconductor with an energy gap greater than silicon and is implanted with an impurity to increase free carrier flow of a second type.

Abstract: The present invention provides SOI material which includes a top Si-containing layer which has regions of different thickness as well as a method of fabricating such SOI material. The inventive method includes a step of thinning predetermined regions of the top Si-containing layer by masked oxidation of silicon. SOI IC chips including the inventive SOI material having different types of CMOS devices build thereon as also disclosed.

Abstract: A method for fabricating a bipolar junction transistor on a wafer is disclosed. The wafer has a N-type doped area and a plurality of isolated structures. A protection layer is formed on the wafer and portions of the protection layer are then removed to expose portions of the doped area. A P-type epitaxy layer is formed on the protection layer and the first doped area and then portions of the epitaxy layer and the protection layer are removed. An insulation layer is formed and at least a collector opening and emitter opening are formed within the insulation layer. Following that, a polysilicon layer is formed to fill the collector opening and the emitter opening. A spacer is formed beside the polysilicon layer and the epitaxy layer followed by performing a self-aligned silicidation process to form a salicide layer on the polysilicon layer and portions of the epitaxy layer.

Abstract: The present invention provides a method for parallel production of an MOS transistor in an MOS area of a substrate and a bipolar transistor in a bipolar area of the substrate. The method includes generating an MOS preparation structure in the MOS area, wherein the MOS preparation structure includes an area provided for a channel, a gate dielectric, a gate electrode layer and a mask layer on the gate electrode layer. Further, a bipolar preparation structure is generated in the bipolar area, which includes a conductive layer and a mask layer on the conductive layer. For determining a gate electrode and a base terminal area, common structuring of the gate electrode layer and the conductive layer is performed. Further, the method includes simultaneous generation of isolating spacing layers on side walls of the gate electrode layer in the MOS area and the conductive layer in the bipolar area by depositing a first and second spacing layer.